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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: tlu_pib.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

////////////////////////////////////////////////////////////////////////

/*

//      Description:    Performance Instrumentation Block

//                      Performance monitoring 2 of the 9 possible events

//                      can be tracked per thread

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

`include        "sys.h" // system level definition file which contains the

                        // time scale definition

`include "tlu.h"

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

module  tlu_pib (/*AUTOARG*/

                 // input

                 ifu_tlu_imiss_e, ifu_tlu_immu_miss_m, ifu_tlu_thrid_d,

                 ifu_tlu_sraddr_d, ifu_tlu_rsr_inst_d, // ifu_tlu_wsr_inst_d, 

                 ifu_tlu_l2imiss, tlu_tcc_inst_w, lsu_tlu_wsr_inst_e,

                 ffu_tlu_fpu_tid, ffu_tlu_fpu_cmplt,

                 lsu_tlu_dmmu_miss_g, lsu_tlu_dcache_miss_w2, lsu_tlu_l2_dmiss,

                 lsu_tlu_stb_full_w2, exu_tlu_wsr_data_m, // tlu_tickcmp_sel, 

                 tlu_hpstate_priv, tlu_thread_inst_vld_g, tlu_wsr_inst_nq_g,

                 tlu_full_flush_pipe_w2,  tlu_pstate_priv, tlu_thread_wsel_g,

                 tlu_pib_rsr_data_e, tlu_hpstate_enb, ifu_tlu_flush_fd_w,

//

// reset was modified to abide to the Niagara reset methodology 

                 rclk, arst_l, grst_l, si, se, // tlu_rst_l, rst_tri_en, 

                 // output

// tlu_pcr_ut_e, tlu_pcr_st_e,

                 pib_picl_wrap, pich_wrap_flg, pich_onebelow_flg, pich_twobelow_flg,

                 tlu_pic_onebelow_e, tlu_pic_twobelow_e, pib_priv_act_trap_m,

                 tlu_wsr_data_w, tlu_pcr_ut, tlu_pcr_st, tlu_pic_wrap_e, so);

// Input section

// Events generated by IFU

input        ifu_tlu_imiss_e;      // icache misses -- New interface  

input            ifu_tlu_immu_miss_m;  // itlb misses 

input [1:0]       ifu_tlu_thrid_d;          //  thread id For instruction complete

input [`TLU_THRD_NUM-1:0] tlu_thread_inst_vld_g; // For instruction complete

input [`TLU_THRD_NUM-1:0] tlu_thread_wsel_g;  // thread of instruction fetched 

input [`TLU_THRD_NUM-1:0] ifu_tlu_l2imiss; // l2 imiss -- new interface 

// ASR register read/write requests

input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d;

input ifu_tlu_rsr_inst_d; // valid rd sr(st/pr)

// input ifu_tlu_wsr_inst_d; // valid wr sr(st/pr)

input lsu_tlu_wsr_inst_e; // valid wr sr(st/pr)

// input tlu_wsr_inst_g; // valid wr sr(st/pr)

// modified for timing

input tlu_wsr_inst_nq_g; // valid wr sr(st/pr)

input [`TLU_ASR_DATA_WIDTH-1:0] exu_tlu_wsr_data_m; // pr/st data to irf.

// modified due to timing

// input [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // this was the tlu_exu_rsr_data_e 

// LSU generated events - also include L2 miss

input [`TLU_THRD_NUM-1:0] lsu_tlu_dcache_miss_w2; // dcache miss -- new interface 

input [`TLU_THRD_NUM-1:0] lsu_tlu_l2_dmiss;           // l2 dmisses -- new interface 

input [`TLU_THRD_NUM-1:0] lsu_tlu_stb_full_w2;    // store buffer full -- new interface 

input lsu_tlu_dmmu_miss_g;       // dtlb misses 

// FFU generated events - also include L2 miss

input [1:0] ffu_tlu_fpu_tid;   // ThrdID for the FF instr_cmplt -- new 

input       ffu_tlu_fpu_cmplt; // FF instru complete -- new 

// TLU information for event filtering

//

input [`TLU_THRD_NUM-1:0] tlu_pstate_priv; // supervisor privilege information 

input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;// hypervisor privilege information

input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb; // hyperlite enabling 

input tlu_tcc_inst_w; // For instruction complete 

input tlu_full_flush_pipe_w2; // For instruction complete 

input ifu_tlu_flush_fd_w; // For instruction complete 

// Global signals

input rclk;

//

// reset was modified to abide to the Niagara reset methodology 

// input                        reset;          

// input tlu_rst_l;             

input           grst_l;                         // global reset - active log

input           arst_l;                         // global reset - active log

input           si;                                 // global scan-in 

input           se;                                 // global scan-out 

// input                rst_tri_en;                     // global reset - active log

// output section

// modified to make inst vld overflow trap precies

// output [`TLU_THRD_NUM-1:0] pib_pic_wrap;     // pic register wrap transition 

// output pib_rst_l;                            // local unit reset - active low

output [`TLU_THRD_NUM-1:0] pib_picl_wrap;       // pic register wrap transition 

output [`TLU_THRD_NUM-1:0] pich_wrap_flg;       // pic register wrap transition 

output [`TLU_THRD_NUM-1:0] pich_onebelow_flg;   // pic register wrap transition 

output [`TLU_THRD_NUM-1:0] pich_twobelow_flg;   // pic register wrap transition 

// output [`TLU_THRD_NUM-1:0] pich_threebelow_flg; // pic register wrap transition 

// modified due to timing fixes

output [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // rsr data register data 

output tlu_pic_onebelow_e, tlu_pic_twobelow_e, tlu_pic_wrap_e;

//

// modified for bug 5436 - Niagara 2.0

output [`TLU_THRD_NUM-1:0] tlu_pcr_ut;

output [`TLU_THRD_NUM-1:0] tlu_pcr_st;

wire tlu_pcr_ut_e, tlu_pcr_st_e;

// 

// output [`TLU_THRD_NUM-1:0] pib_priv_act_trap;  // access privilege violation for pics 

output [`TLU_THRD_NUM-1:0] pib_priv_act_trap_m;  // access privilege violation for pics 

// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_e; // Add in the final muxing of pib asr data 

output [`TLU_ASR_DATA_WIDTH-1:0] tlu_wsr_data_w;     // flopped version of exu_tlu_wsr_data_m 

// output [47:0] tlu_ifu_trappc_w2;  // temporary for timing 

// output [47:0] tlu_ifu_trapnpc_w2; // temporary for timing 

output   so;                                // global scan-out 

//==============================================================================

// Local signal defines 

//==============================================================================

// decoded address for pcr and pic

wire pcr_rw_e, pcr_rw_m, pcr_rw_g; // pcr_rw_d, 

wire pic_priv_rw_e, pic_priv_rw_m, pic_priv_rw_g; // pic_priv_rw_d,  

wire pic_npriv_rw_e, pic_npriv_rw_m, pic_npriv_rw_g;// pic_npriv_rw_d, 

//

// read/write to pcr, evq and pic 

wire [`TLU_THRD_NUM-1:0] wsr_thread_inst_g;

wire [`TLU_THRD_NUM-1:0] update_picl_sel, update_picl_wrap_en;

wire [`TLU_THRD_NUM-1:0] picl_cnt_wrap_datain;

wire [`TLU_THRD_NUM-1:0] update_pich_sel, update_pich_wrap_en;

wire [`TLU_THRD_NUM-1:0] pich_cnt_wrap_datain;

wire [`TLU_THRD_NUM-1:0] update_evq_sel;

wire [`TLU_THRD_NUM-1:0] wsr_pcr_sel;

wire [`TLU_THRD_NUM-1:0] wsr_pic_sel;

wire [`TLU_THRD_NUM-1:0] update_pich_ovf;

wire [`TLU_THRD_NUM-1:0] update_picl_ovf;

wire [`TLU_THRD_NUM-1:0] inst_vld_w2;

wire tcc_inst_w2;

// 

// added for bug 2919

wire [`TLU_THRD_NUM-1:0] pic_update_ctl;

wire [1:0] pic_update_sel_ctr;

wire [1:0] pic_update_sel_incr;

//

// modified for timing

// wire [`TLU_ASR_ADDR_WIDTH-1:0] pib_sraddr_d;      

wire [`TLU_ASR_ADDR_WIDTH-1:0] pib_sraddr_e;

wire tlu_rsr_inst_e, tlu_wsr_inst_e;

//

// picl masks

wire [`PICL_MASK_WIDTH-1:0] picl_mask0, picl_mask1, picl_mask2, picl_mask3;

wire [`PICL_MASK_WIDTH-1:0] picl_event0, picl_event1, picl_event2, picl_event3;

// added for bug2332

// wire incr_pich_onehot;

// pic counters

wire [`TLU_THRD_NUM-1:0] incr_pich;

wire [`TLU_THRD_NUM-1:0] pich_mux_sel;

wire [`TLU_THRD_NUM-1:0] pich_cnt_wrap;

wire [`TLU_THRD_NUM-1:0] picl_cnt_wrap;

wire [`TLU_THRD_NUM-2:0] thread_rsel_d;

wire [`TLU_THRD_NUM-2:0] thread_rsel_e;

wire [`TLU_THRD_NUM-1:0] pic_onebelow_e, pic_twobelow_e, pic_wrap_e;

wire [`PIB_PIC_CNT_WIDTH-1:0] picl_cnt0, picl_cnt1, picl_cnt2, picl_cnt3;

wire [`PIB_PIC_CNT_WIDTH-1:0] picl_cnt_din, picl_cnt_sum;

wire [`PIB_PIC_CNT_WIDTH-1:0] picl_wsr_data;

wire [`PIB_PIC_CNT_WIDTH-1:0] update_picl0_data, update_picl1_data;

wire [`PIB_PIC_CNT_WIDTH-1:0] update_picl2_data, update_picl3_data;

wire [`PIB_PIC_CNT_WIDTH-1:0] pich_cnt0, pich_cnt1, pich_cnt2, pich_cnt3;

wire [`PIB_PIC_CNT_WIDTH-1:0] pich_cnt_din, pich_cnt_sum;

wire [`PIB_PIC_CNT_WIDTH-1:0] pich_wsr_data;

wire [`PIB_PIC_CNT_WIDTH-1:0] update_pich0_data, update_pich1_data;

wire [`PIB_PIC_CNT_WIDTH-1:0] update_pich2_data, update_pich3_data;

wire [`TLU_ASR_DATA_WIDTH-1:0] pic_rdata_e;

wire [`TLU_ASR_DATA_WIDTH-1:0] pcr_rdata_e;

wire [`PIB_PCR_WIDTH-1:0] pcr_reg_rdata_e;

wire [`PIB_PCR_WIDTH-1:0] pcr_wdata_in;

wire [`TLU_THRD_NUM-1:0] picl_ovf_wdata_in;

wire [`TLU_THRD_NUM-1:0] pich_ovf_wdata_in;

// experiment

wire [`TLU_THRD_NUM-1:0] pich_fourbelow_din;

wire [`TLU_THRD_NUM-1:0] pich_fourbelow_flg;

// wire [`TLU_THRD_NUM-1:0] pich_threebelow_flg;

// modified due to timing

// wire [2:0] rsr_data_sel_e;

wire [1:0] rsr_data_sel_e;

// picl evqs 

wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0, picl_evq1, picl_evq2, picl_evq3;

wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0_sum, picl_evq1_sum;

wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq2_sum, picl_evq3_sum;

wire [`PIB_EVQ_CNT_WIDTH-1:0] update_evq0_data, update_evq1_data;

wire [`PIB_EVQ_CNT_WIDTH-1:0] update_evq2_data, update_evq3_data;

wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq_din;

wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0_din, picl_evq1_din;

wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq2_din, picl_evq3_din;

wire [`TLU_THRD_NUM-1:0] incr_evq_din, incr_evq;

// pcr registers

wire [`PIB_PCR_WIDTH-1:0] pcr0, pcr1, pcr2, pcr3;

// 

wire local_rst; // local active high reset

wire local_rst_l; // local active high reset

// counting enable indicator 

wire [`TLU_THRD_NUM-1:0] pic_cnt_en, pic_cnt_en_w2;

//

// staged icache and itlb misses

wire imiss_m, imiss_g;

wire immu_miss_g;

//

// threaded icache, itlb, and dtlb misses

wire [`TLU_THRD_NUM-1:0] imiss_thread_g;

wire [`TLU_THRD_NUM-1:0] immu_miss_thread_g;

wire [`TLU_THRD_NUM-1:0] dmmu_miss_thread_g;

wire [`TLU_THRD_NUM-1:0] fpu_cmplt_thread;

//

// clock rename

wire clk;

//==============================================================================

// Code starts here

//==============================================================================

//      reset

dffrl_async dffrl_local_rst_l(

    .din  (grst_l),

    .clk  (clk),

    .rst_l(arst_l),

    .q    (local_rst_l),

    .se   (se),

    `SIMPLY_RISC_SCANIN,

    .so   ()

);

assign local_rst = ~local_rst_l;

// assign pib_rst_l = local_rst_l;

// assign local_rst = ~tlu_rst_l;

//

// rename clock 

assign clk = rclk;

//

// privilege action trap due to user access of pic register when

// PRIV bit is set in pcr

// modified for timing fixes

/*

assign pib_priv_act_trap = (pic_npriv_rw_g ) &

           ((pcr0[`PIB_PCR_PRIV]  & tlu_thread_inst_vld_g[0]) &

             ~tlu_pstate_priv[0]) |

           ((pcr1[`PIB_PCR_PRIV]  & tlu_thread_inst_vld_g[1]) &

             ~tlu_pstate_priv[1]) |

           ((pcr2[`PIB_PCR_PRIV]  & tlu_thread_inst_vld_g[2]) &

             ~tlu_pstate_priv[2]) |

           ((pcr3[`PIB_PCR_PRIV]  & tlu_thread_inst_vld_g[3]) &

             ~tlu_pstate_priv[3]);

*/

assign pib_priv_act_trap_m[0] = pic_npriv_rw_m & pcr0[`PIB_PCR_PRIV];

assign pib_priv_act_trap_m[1] = pic_npriv_rw_m & pcr1[`PIB_PCR_PRIV];

assign pib_priv_act_trap_m[2] = pic_npriv_rw_m & pcr2[`PIB_PCR_PRIV];

assign pib_priv_act_trap_m[3] = pic_npriv_rw_m & pcr3[`PIB_PCR_PRIV];

//

// staging the exu_tlu_wsr_data_w signal for timing

//

dff_s #(`TLU_ASR_DATA_WIDTH) dff_tlu_wsr_data_w (

    .din (exu_tlu_wsr_data_m[`TLU_ASR_DATA_WIDTH-1:0]),

    .q   (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

//

//================================

// address decode for PCR and PICs 

//================================

// added and modified for timing

// assign pib_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0] =

//            ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0]; 

dff_s #(`TLU_ASR_ADDR_WIDTH) dff_pib_sraddr_e (

    .din (ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0]),

    .q   (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dffr_s dffr_tlu_rsr_inst_e (

    .din (ifu_tlu_rsr_inst_d),

    .q   (tlu_rsr_inst_e),

    .rst (local_rst),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

//

// modified for timing

/*

dffr_s dffr_tlu_wsr_inst_e (

    .din (ifu_tlu_wsr_inst_d),

    .q   (tlu_wsr_inst_e),

    .rst (local_rst),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

*/

assign tlu_wsr_inst_e = lsu_tlu_wsr_inst_e;

//

assign pcr_rw_e =

           (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PCR_ASR_ADDR);

assign pic_priv_rw_e =

           (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_PRIV_ADDR);

assign pic_npriv_rw_e =

           (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_NPRIV_ADDR) &

           (tlu_rsr_inst_e | tlu_wsr_inst_e);

//

// staging of the ASR decoded controls

//

// staging from d to e stage

// deleted for timing

/*

dff_s dff_pcr_rw_d_e (

    .din (pcr_rw_d),

    .q   (pcr_rw_e),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_pic_priv_rw_d_e (

    .din (pic_priv_rw_d),

    .q   (pic_priv_rw_e),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_pic_npriv_rw_d_e (

    .din (pic_npriv_rw_d),

    .q   (pic_npriv_rw_e),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

*/

//

// staging from e to m stage

dff_s dff_pcr_rw_e_m (

    .din (pcr_rw_e),

    .q   (pcr_rw_m),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_pic_priv_rw_e_m (

    .din (pic_priv_rw_e),

    .q   (pic_priv_rw_m),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_pic_npriv_rw_e_m (

    .din (pic_npriv_rw_e),

    .q   (pic_npriv_rw_m),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_imiss_e_m (

    .din (ifu_tlu_imiss_e),

    .q   (imiss_m),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

//

// staging from m to g stage

dff_s dff_pcr_rw_m_g (

    .din (pcr_rw_m),

    .q   (pcr_rw_g),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_pic_priv_rw_m_g (

    .din (pic_priv_rw_m),

    .q   (pic_priv_rw_g),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_pic_npriv_rw_m_g (

    .din (pic_npriv_rw_m),

    .q   (pic_npriv_rw_g),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_imiss_m_g (

    .din (imiss_m),

    .q   (imiss_g),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s dff_immu_miss_m_g (

    .din (ifu_tlu_immu_miss_m),

    .q   (immu_miss_g),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

//

//=========================

// update for PCR registers   

//=========================

//

assign wsr_thread_inst_g[0] =

           tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[0];

assign wsr_thread_inst_g[1] =

           tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[1];

assign wsr_thread_inst_g[2] =

           tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[2];

assign wsr_thread_inst_g[3] =

           tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[3];

// 

// extracting the relevant bits from the wsr data bus

assign pcr_wdata_in =

    {tlu_wsr_data_w[`WSR_PCR_CH_OVF:`WSR_PCR_CL_OVF],

     tlu_wsr_data_w[`WSR_PCR_SL_HI:`WSR_PCR_SL_LO],

     tlu_wsr_data_w[`WSR_PCR_UT:`WSR_PCR_PRIV]};

//

// thread 0

assign wsr_pcr_sel[0] = wsr_thread_inst_g[0] & pcr_rw_g;

assign update_picl_ovf[0] =

           (wsr_thread_inst_g[0] & pcr_rw_g) |

           (picl_cnt_wrap[0] ^ picl_cnt0[`PIB_PIC_CNT_WIDTH-1]);

assign update_pich_ovf[0] =

           (wsr_thread_inst_g[0] & pcr_rw_g) |

           (pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]);

//

// modified for bug 2291

dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr0 (

 //   .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),

    .din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),

    .q   (pcr0[`PIB_PCR_WIDTH-3:0]),

    .rst (local_rst),

    .en  (wsr_pcr_sel[0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

mux2ds mux_pcr0_picl_ovf (

        .in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),

        .in1(picl_cnt_wrap[0] ^ picl_cnt0[`PIB_PIC_CNT_WIDTH-1]),

        .sel0(wsr_pcr_sel[0]),

        .sel1(~wsr_pcr_sel[0]),

        .dout(picl_ovf_wdata_in[0])

);

// added for the new bug 2588

dffre_s dffre_pcr0_picl_ovf (

    .din (picl_ovf_wdata_in[0]),

    .q   (pcr0[`PIB_PCR_CL_OVF]),

    .clk (clk),

    .en  (update_picl_ovf[0]),

    .rst (local_rst),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

mux2ds mux_pcr0_pich_ovf (

        .in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),

        .in1(pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]),

        .sel0(wsr_pcr_sel[0]),

        .sel1(~wsr_pcr_sel[0]),

        .dout(pich_ovf_wdata_in[0])

);

dffre_s dffre_pcr0_pich_ovf (

    .din (pich_ovf_wdata_in[0]),

    .q   (pcr0[`PIB_PCR_CH_OVF]),

    .clk (clk),

    .en  (update_pich_ovf[0]),

    .rst (local_rst),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

// 

// thread 1

assign wsr_pcr_sel[1] = wsr_thread_inst_g[1] & pcr_rw_g;

assign update_picl_ovf[1] =

           (wsr_thread_inst_g[1] & pcr_rw_g) |

           (picl_cnt_wrap[1] ^ picl_cnt1[`PIB_PIC_CNT_WIDTH-1]);

assign update_pich_ovf[1] =

           (wsr_thread_inst_g[1] & pcr_rw_g) |

           (pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]);

dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr1 (

 //   .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),

    .din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),

    .q   (pcr1[`PIB_PCR_WIDTH-3:0]),

    .rst (local_rst),

    .en  (wsr_pcr_sel[1]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

mux2ds mux_pcr1_picl_ovf (

        .in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),

        .in1(picl_cnt_wrap[1] ^ picl_cnt1[`PIB_PIC_CNT_WIDTH-1]),

        .sel0(wsr_pcr_sel[1]),

        .sel1(~wsr_pcr_sel[1]),

        .dout(picl_ovf_wdata_in[1])

);

// added for the new bug 2588

dffre_s dffre_pcr1_picl_ovf (

    .din (picl_ovf_wdata_in[1]),

    .q   (pcr1[`PIB_PCR_CL_OVF]),

    .clk (clk),

    .en  (update_picl_ovf[1]),

    .rst (local_rst),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

mux2ds mux_pcr1_pich_ovf (

        .in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),

        .in1(pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]),

        .sel0(wsr_pcr_sel[1]),

        .sel1(~wsr_pcr_sel[1]),

        .dout(pich_ovf_wdata_in[1])

);

dffre_s dffre_pcr1_pich_ovf (

    .din (pich_ovf_wdata_in[1]),

    .q   (pcr1[`PIB_PCR_CH_OVF]),

    .clk (clk),

    .en  (update_pich_ovf[1]),

    .rst (local_rst),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

// 

// thread 2

assign wsr_pcr_sel[2] = wsr_thread_inst_g[2] & pcr_rw_g;

assign update_picl_ovf[2] =

           (wsr_thread_inst_g[2] & pcr_rw_g) |

           (picl_cnt_wrap[2] ^ picl_cnt2[`PIB_PIC_CNT_WIDTH-1]);

assign update_pich_ovf[2] =

           (wsr_thread_inst_g[2] & pcr_rw_g) |

           (pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]);

dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr2 (

 //   .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),

    .din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),

    .q   (pcr2[`PIB_PCR_WIDTH-3:0]),

    .rst (local_rst),

    .en  (wsr_pcr_sel[2]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

mux2ds mux_pcr2_picl_ovf (

        .in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),