OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [tlu_pib.v] - Blame information for rev 113

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 95 fafa1971 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: tlu_pib.v
4 
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5 
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6 
//
7 
// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
9 
// License version 2 as published by the Free Software Foundation.
10 
//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
17 
// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19 
//
20 
// ========== Copyright Header End ============================================
21 113 albert.wat 
`ifdef SIMPLY_RISC_TWEAKS
22 
`define SIMPLY_RISC_SCANIN .si(0)
23 
`else
24 
`define SIMPLY_RISC_SCANIN .si()
25 
`endif
26 95 fafa1971 
////////////////////////////////////////////////////////////////////////
27 
/*
28 
//      Description:    Performance Instrumentation Block
29 
//                      Performance monitoring 2 of the 9 possible events
30 
//                      can be tracked per thread
31 
*/
32 
////////////////////////////////////////////////////////////////////////
33 
// Global header file includes
34 
////////////////////////////////////////////////////////////////////////
35 113 albert.wat 
`include        "sys.h" // system level definition file which contains the
36 95 fafa1971 
                        // time scale definition
37 
 
38 113 albert.wat 
`include "tlu.h"
39 95 fafa1971 
 
40 
////////////////////////////////////////////////////////////////////////
41 
// Local header file includes / local defines
42 
////////////////////////////////////////////////////////////////////////
43 
 
44 
module  tlu_pib (/*AUTOARG*/
45 
                 // input
46 
                 ifu_tlu_imiss_e, ifu_tlu_immu_miss_m, ifu_tlu_thrid_d,
47 
                 ifu_tlu_sraddr_d, ifu_tlu_rsr_inst_d, // ifu_tlu_wsr_inst_d,
48 
                 ifu_tlu_l2imiss, tlu_tcc_inst_w, lsu_tlu_wsr_inst_e,
49 
                 ffu_tlu_fpu_tid, ffu_tlu_fpu_cmplt,
50 
                 lsu_tlu_dmmu_miss_g, lsu_tlu_dcache_miss_w2, lsu_tlu_l2_dmiss,
51 
                 lsu_tlu_stb_full_w2, exu_tlu_wsr_data_m, // tlu_tickcmp_sel,
52 
                 tlu_hpstate_priv, tlu_thread_inst_vld_g, tlu_wsr_inst_nq_g,
53 
                 tlu_full_flush_pipe_w2,  tlu_pstate_priv, tlu_thread_wsel_g,
54 
                 tlu_pib_rsr_data_e, tlu_hpstate_enb, ifu_tlu_flush_fd_w,
55 
//
56 
// reset was modified to abide to the Niagara reset methodology
57 
                 rclk, arst_l, grst_l, si, se, // tlu_rst_l, rst_tri_en,
58 
                 // output
59 
 
60 
// tlu_pcr_ut_e, tlu_pcr_st_e,
61 
                 pib_picl_wrap, pich_wrap_flg, pich_onebelow_flg, pich_twobelow_flg,
62 
                 tlu_pic_onebelow_e, tlu_pic_twobelow_e, pib_priv_act_trap_m,
63 
                 tlu_wsr_data_w, tlu_pcr_ut, tlu_pcr_st, tlu_pic_wrap_e, so);
64 
 
65 
// Input section
66 
// Events generated by IFU
67 
input        ifu_tlu_imiss_e;      // icache misses -- New interface
68 
input            ifu_tlu_immu_miss_m;  // itlb misses
69 
input [1:0]       ifu_tlu_thrid_d;          //  thread id For instruction complete
70 113 albert.wat 
input [`TLU_THRD_NUM-1:0] tlu_thread_inst_vld_g; // For instruction complete
71 
input [`TLU_THRD_NUM-1:0] tlu_thread_wsel_g;  // thread of instruction fetched
72 
input [`TLU_THRD_NUM-1:0] ifu_tlu_l2imiss; // l2 imiss -- new interface
73 95 fafa1971 
 
74 
// ASR register read/write requests
75 113 albert.wat 
input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d;
76 95 fafa1971 
input ifu_tlu_rsr_inst_d; // valid rd sr(st/pr)
77 
// input ifu_tlu_wsr_inst_d; // valid wr sr(st/pr)
78 
input lsu_tlu_wsr_inst_e; // valid wr sr(st/pr)
79 
// input tlu_wsr_inst_g; // valid wr sr(st/pr)
80 
// modified for timing
81 
input tlu_wsr_inst_nq_g; // valid wr sr(st/pr)
82 113 albert.wat 
input [`TLU_ASR_DATA_WIDTH-1:0] exu_tlu_wsr_data_m; // pr/st data to irf.
83 95 fafa1971 
// modified due to timing
84 
// input [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // this was the tlu_exu_rsr_data_e
85 
 
86 
// LSU generated events - also include L2 miss
87 113 albert.wat 
input [`TLU_THRD_NUM-1:0] lsu_tlu_dcache_miss_w2; // dcache miss -- new interface
88 
input [`TLU_THRD_NUM-1:0] lsu_tlu_l2_dmiss;           // l2 dmisses -- new interface
89 
input [`TLU_THRD_NUM-1:0] lsu_tlu_stb_full_w2;    // store buffer full -- new interface
90 95 fafa1971 
input lsu_tlu_dmmu_miss_g;       // dtlb misses
91 
// FFU generated events - also include L2 miss
92 
input [1:0] ffu_tlu_fpu_tid;   // ThrdID for the FF instr_cmplt -- new
93 
input       ffu_tlu_fpu_cmplt; // FF instru complete -- new
94 
// TLU information for event filtering
95 
//
96 113 albert.wat 
input [`TLU_THRD_NUM-1:0] tlu_pstate_priv; // supervisor privilege information
97 
input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;// hypervisor privilege information
98 
input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb; // hyperlite enabling
99 95 fafa1971 
input tlu_tcc_inst_w; // For instruction complete
100 
input tlu_full_flush_pipe_w2; // For instruction complete
101 
input ifu_tlu_flush_fd_w; // For instruction complete
102 
// Global signals
103 
input rclk;
104 
//
105 
// reset was modified to abide to the Niagara reset methodology
106 
// input                        reset;
107 
// input tlu_rst_l;
108 
input           grst_l;                         // global reset - active log
109 
input           arst_l;                         // global reset - active log
110 
input           si;                                 // global scan-in
111 
input           se;                                 // global scan-out
112 
// input                rst_tri_en;                     // global reset - active log
113 
 
114 
// output section
115 
// modified to make inst vld overflow trap precies
116 
// output [`TLU_THRD_NUM-1:0] pib_pic_wrap;     // pic register wrap transition
117 
// output pib_rst_l;                            // local unit reset - active low
118 113 albert.wat 
output [`TLU_THRD_NUM-1:0] pib_picl_wrap;       // pic register wrap transition
119 
output [`TLU_THRD_NUM-1:0] pich_wrap_flg;       // pic register wrap transition
120 
output [`TLU_THRD_NUM-1:0] pich_onebelow_flg;   // pic register wrap transition
121 
output [`TLU_THRD_NUM-1:0] pich_twobelow_flg;   // pic register wrap transition
122 95 fafa1971 
// output [`TLU_THRD_NUM-1:0] pich_threebelow_flg; // pic register wrap transition
123 
// modified due to timing fixes
124 113 albert.wat 
output [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // rsr data register data
125 95 fafa1971 
output tlu_pic_onebelow_e, tlu_pic_twobelow_e, tlu_pic_wrap_e;
126 
//
127 
// modified for bug 5436 - Niagara 2.0
128 113 albert.wat 
output [`TLU_THRD_NUM-1:0] tlu_pcr_ut;
129 
output [`TLU_THRD_NUM-1:0] tlu_pcr_st;
130 95 fafa1971 
wire tlu_pcr_ut_e, tlu_pcr_st_e;
131 
 
132 
 
133 
//
134 
// output [`TLU_THRD_NUM-1:0] pib_priv_act_trap;  // access privilege violation for pics
135 113 albert.wat 
output [`TLU_THRD_NUM-1:0] pib_priv_act_trap_m;  // access privilege violation for pics
136 95 fafa1971 
// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_e; // Add in the final muxing of pib asr data
137 113 albert.wat 
output [`TLU_ASR_DATA_WIDTH-1:0] tlu_wsr_data_w;     // flopped version of exu_tlu_wsr_data_m
138 95 fafa1971 
// output [47:0] tlu_ifu_trappc_w2;  // temporary for timing
139 
// output [47:0] tlu_ifu_trapnpc_w2; // temporary for timing
140 
output   so;                                // global scan-out
141 
 
142 
//==============================================================================
143 
// Local signal defines
144 
//==============================================================================
145 
// decoded address for pcr and pic
146 
wire pcr_rw_e, pcr_rw_m, pcr_rw_g; // pcr_rw_d,
147 
wire pic_priv_rw_e, pic_priv_rw_m, pic_priv_rw_g; // pic_priv_rw_d,
148 
wire pic_npriv_rw_e, pic_npriv_rw_m, pic_npriv_rw_g;// pic_npriv_rw_d,
149 
//
150 
// read/write to pcr, evq and pic
151 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] wsr_thread_inst_g;
152 
wire [`TLU_THRD_NUM-1:0] update_picl_sel, update_picl_wrap_en;
153 
wire [`TLU_THRD_NUM-1:0] picl_cnt_wrap_datain;
154 
wire [`TLU_THRD_NUM-1:0] update_pich_sel, update_pich_wrap_en;
155 
wire [`TLU_THRD_NUM-1:0] pich_cnt_wrap_datain;
156 
wire [`TLU_THRD_NUM-1:0] update_evq_sel;
157 
wire [`TLU_THRD_NUM-1:0] wsr_pcr_sel;
158 
wire [`TLU_THRD_NUM-1:0] wsr_pic_sel;
159 
wire [`TLU_THRD_NUM-1:0] update_pich_ovf;
160 
wire [`TLU_THRD_NUM-1:0] update_picl_ovf;
161 
wire [`TLU_THRD_NUM-1:0] inst_vld_w2;
162 95 fafa1971 
wire tcc_inst_w2;
163 
//
164 
// added for bug 2919
165 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] pic_update_ctl;
166 95 fafa1971 
wire [1:0] pic_update_sel_ctr;
167 
wire [1:0] pic_update_sel_incr;
168 
//
169 
// modified for timing
170 
// wire [`TLU_ASR_ADDR_WIDTH-1:0] pib_sraddr_d;
171 113 albert.wat 
wire [`TLU_ASR_ADDR_WIDTH-1:0] pib_sraddr_e;
172 95 fafa1971 
wire tlu_rsr_inst_e, tlu_wsr_inst_e;
173 
//
174 
// picl masks
175 113 albert.wat 
wire [`PICL_MASK_WIDTH-1:0] picl_mask0, picl_mask1, picl_mask2, picl_mask3;
176 
wire [`PICL_MASK_WIDTH-1:0] picl_event0, picl_event1, picl_event2, picl_event3;
177 95 fafa1971 
// added for bug2332
178 
// wire incr_pich_onehot;
179 
// pic counters
180 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] incr_pich;
181 
wire [`TLU_THRD_NUM-1:0] pich_mux_sel;
182 
wire [`TLU_THRD_NUM-1:0] pich_cnt_wrap;
183 
wire [`TLU_THRD_NUM-1:0] picl_cnt_wrap;
184 
wire [`TLU_THRD_NUM-2:0] thread_rsel_d;
185 
wire [`TLU_THRD_NUM-2:0] thread_rsel_e;
186 
wire [`TLU_THRD_NUM-1:0] pic_onebelow_e, pic_twobelow_e, pic_wrap_e;
187 
wire [`PIB_PIC_CNT_WIDTH-1:0] picl_cnt0, picl_cnt1, picl_cnt2, picl_cnt3;
188 
wire [`PIB_PIC_CNT_WIDTH-1:0] picl_cnt_din, picl_cnt_sum;
189 
wire [`PIB_PIC_CNT_WIDTH-1:0] picl_wsr_data;
190 
wire [`PIB_PIC_CNT_WIDTH-1:0] update_picl0_data, update_picl1_data;
191 
wire [`PIB_PIC_CNT_WIDTH-1:0] update_picl2_data, update_picl3_data;
192 
wire [`PIB_PIC_CNT_WIDTH-1:0] pich_cnt0, pich_cnt1, pich_cnt2, pich_cnt3;
193 
wire [`PIB_PIC_CNT_WIDTH-1:0] pich_cnt_din, pich_cnt_sum;
194 
wire [`PIB_PIC_CNT_WIDTH-1:0] pich_wsr_data;
195 
wire [`PIB_PIC_CNT_WIDTH-1:0] update_pich0_data, update_pich1_data;
196 
wire [`PIB_PIC_CNT_WIDTH-1:0] update_pich2_data, update_pich3_data;
197 
wire [`TLU_ASR_DATA_WIDTH-1:0] pic_rdata_e;
198 
wire [`TLU_ASR_DATA_WIDTH-1:0] pcr_rdata_e;
199 
wire [`PIB_PCR_WIDTH-1:0] pcr_reg_rdata_e;
200 
wire [`PIB_PCR_WIDTH-1:0] pcr_wdata_in;
201 
wire [`TLU_THRD_NUM-1:0] picl_ovf_wdata_in;
202 
wire [`TLU_THRD_NUM-1:0] pich_ovf_wdata_in;
203 95 fafa1971 
// experiment
204 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] pich_fourbelow_din;
205 
wire [`TLU_THRD_NUM-1:0] pich_fourbelow_flg;
206 95 fafa1971 
// wire [`TLU_THRD_NUM-1:0] pich_threebelow_flg;
207 
// modified due to timing
208 
// wire [2:0] rsr_data_sel_e;
209 
wire [1:0] rsr_data_sel_e;
210 
// picl evqs
211 113 albert.wat 
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0, picl_evq1, picl_evq2, picl_evq3;
212 
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0_sum, picl_evq1_sum;
213 
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq2_sum, picl_evq3_sum;
214 
wire [`PIB_EVQ_CNT_WIDTH-1:0] update_evq0_data, update_evq1_data;
215 
wire [`PIB_EVQ_CNT_WIDTH-1:0] update_evq2_data, update_evq3_data;
216 
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq_din;
217 
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq0_din, picl_evq1_din;
218 
wire [`PIB_EVQ_CNT_WIDTH-1:0] picl_evq2_din, picl_evq3_din;
219 
wire [`TLU_THRD_NUM-1:0] incr_evq_din, incr_evq;
220 95 fafa1971 
// pcr registers
221 113 albert.wat 
wire [`PIB_PCR_WIDTH-1:0] pcr0, pcr1, pcr2, pcr3;
222 95 fafa1971 
//
223 
wire local_rst; // local active high reset
224 
wire local_rst_l; // local active high reset
225 
// counting enable indicator
226 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] pic_cnt_en, pic_cnt_en_w2;
227 95 fafa1971 
//
228 
// staged icache and itlb misses
229 
wire imiss_m, imiss_g;
230 
wire immu_miss_g;
231 
//
232 
// threaded icache, itlb, and dtlb misses
233 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] imiss_thread_g;
234 
wire [`TLU_THRD_NUM-1:0] immu_miss_thread_g;
235 
wire [`TLU_THRD_NUM-1:0] dmmu_miss_thread_g;
236 
wire [`TLU_THRD_NUM-1:0] fpu_cmplt_thread;
237 95 fafa1971 
//
238 
// clock rename
239 
wire clk;
240 
 
241 
//==============================================================================
242 
// Code starts here
243 
//==============================================================================
244 
//      reset
245 
 
246 
dffrl_async dffrl_local_rst_l(
247 
    .din  (grst_l),
248 
    .clk  (clk),
249 
    .rst_l(arst_l),
250 
    .q    (local_rst_l),
251 
    .se   (se),
252 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
253 95 fafa1971 
    .so   ()
254 
);
255 
 
256 
assign local_rst = ~local_rst_l;
257 
// assign pib_rst_l = local_rst_l;
258 
// assign local_rst = ~tlu_rst_l;
259 
//
260 
// rename clock
261 
assign clk = rclk;
262 
 
263 
//
264 
// privilege action trap due to user access of pic register when
265 
// PRIV bit is set in pcr
266 
// modified for timing fixes
267 
/*
268 
assign pib_priv_act_trap = (pic_npriv_rw_g ) &
269 
           ((pcr0[`PIB_PCR_PRIV]  & tlu_thread_inst_vld_g[0]) &
270 
             ~tlu_pstate_priv[0]) |
271 
           ((pcr1[`PIB_PCR_PRIV]  & tlu_thread_inst_vld_g[1]) &
272 
             ~tlu_pstate_priv[1]) |
273 
           ((pcr2[`PIB_PCR_PRIV]  & tlu_thread_inst_vld_g[2]) &
274 
             ~tlu_pstate_priv[2]) |
275 
           ((pcr3[`PIB_PCR_PRIV]  & tlu_thread_inst_vld_g[3]) &
276 
             ~tlu_pstate_priv[3]);
277 
*/
278 113 albert.wat 
assign pib_priv_act_trap_m[0] = pic_npriv_rw_m & pcr0[`PIB_PCR_PRIV];
279 
assign pib_priv_act_trap_m[1] = pic_npriv_rw_m & pcr1[`PIB_PCR_PRIV];
280 
assign pib_priv_act_trap_m[2] = pic_npriv_rw_m & pcr2[`PIB_PCR_PRIV];
281 
assign pib_priv_act_trap_m[3] = pic_npriv_rw_m & pcr3[`PIB_PCR_PRIV];
282 95 fafa1971 
 
283 
//
284 
// staging the exu_tlu_wsr_data_w signal for timing
285 
//
286 113 albert.wat 
dff_s #(`TLU_ASR_DATA_WIDTH) dff_tlu_wsr_data_w (
287 
    .din (exu_tlu_wsr_data_m[`TLU_ASR_DATA_WIDTH-1:0]),
288 
    .q   (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0]),
289 95 fafa1971 
    .clk (clk),
290 
    .se  (se),
291 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
292 95 fafa1971 
    .so  ()
293 
);
294 
//
295 
//================================
296 
// address decode for PCR and PICs
297 
//================================
298 
// added and modified for timing
299 
// assign pib_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0] =
300 
//            ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0];
301 
 
302 113 albert.wat 
dff_s #(`TLU_ASR_ADDR_WIDTH) dff_pib_sraddr_e (
303 
    .din (ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0]),
304 
    .q   (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0]),
305 95 fafa1971 
    .clk (clk),
306 
    .se  (se),
307 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
308 95 fafa1971 
    .so  ()
309 
);
310 
 
311 113 albert.wat 
dffr_s dffr_tlu_rsr_inst_e (
312 95 fafa1971 
    .din (ifu_tlu_rsr_inst_d),
313 
    .q   (tlu_rsr_inst_e),
314 
    .rst (local_rst),
315 
    .clk (clk),
316 
    .se  (se),
317 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
318 95 fafa1971 
    .so  ()
319 
);
320 
//
321 
// modified for timing
322 
/*
323 113 albert.wat 
dffr_s dffr_tlu_wsr_inst_e (
324 95 fafa1971 
    .din (ifu_tlu_wsr_inst_d),
325 
    .q   (tlu_wsr_inst_e),
326 
    .rst (local_rst),
327 
    .clk (clk),
328 
    .se  (se),
329 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
330 95 fafa1971 
    .so  ()
331 
);
332 
*/
333 
assign tlu_wsr_inst_e = lsu_tlu_wsr_inst_e;
334 
//
335 
assign pcr_rw_e =
336 113 albert.wat 
           (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PCR_ASR_ADDR);
337 95 fafa1971 
assign pic_priv_rw_e =
338 113 albert.wat 
           (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_PRIV_ADDR);
339 95 fafa1971 
assign pic_npriv_rw_e =
340 113 albert.wat 
           (pib_sraddr_e[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_NPRIV_ADDR) &
341 95 fafa1971 
           (tlu_rsr_inst_e | tlu_wsr_inst_e);
342 
//
343 
// staging of the ASR decoded controls
344 
//
345 
// staging from d to e stage
346 
// deleted for timing
347 
/*
348 113 albert.wat 
dff_s dff_pcr_rw_d_e (
349 95 fafa1971 
    .din (pcr_rw_d),
350 
    .q   (pcr_rw_e),
351 
    .clk (clk),
352 
    .se  (se),
353 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
354 95 fafa1971 
    .so  ()
355 
);
356 
 
357 113 albert.wat 
dff_s dff_pic_priv_rw_d_e (
358 95 fafa1971 
    .din (pic_priv_rw_d),
359 
    .q   (pic_priv_rw_e),
360 
    .clk (clk),
361 
    .se  (se),
362 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
363 95 fafa1971 
    .so  ()
364 
);
365 
 
366 113 albert.wat 
dff_s dff_pic_npriv_rw_d_e (
367 95 fafa1971 
    .din (pic_npriv_rw_d),
368 
    .q   (pic_npriv_rw_e),
369 
    .clk (clk),
370 
    .se  (se),
371 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
372 95 fafa1971 
    .so  ()
373 
);
374 
*/
375 
//
376 
// staging from e to m stage
377 113 albert.wat 
dff_s dff_pcr_rw_e_m (
378 95 fafa1971 
    .din (pcr_rw_e),
379 
    .q   (pcr_rw_m),
380 
    .clk (clk),
381 
    .se  (se),
382 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
383 95 fafa1971 
    .so  ()
384 
);
385 
 
386 113 albert.wat 
dff_s dff_pic_priv_rw_e_m (
387 95 fafa1971 
    .din (pic_priv_rw_e),
388 
    .q   (pic_priv_rw_m),
389 
    .clk (clk),
390 
    .se  (se),
391 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
392 95 fafa1971 
    .so  ()
393 
);
394 
 
395 113 albert.wat 
dff_s dff_pic_npriv_rw_e_m (
396 95 fafa1971 
    .din (pic_npriv_rw_e),
397 
    .q   (pic_npriv_rw_m),
398 
    .clk (clk),
399 
    .se  (se),
400 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
401 95 fafa1971 
    .so  ()
402 
);
403 
 
404 113 albert.wat 
dff_s dff_imiss_e_m (
405 95 fafa1971 
    .din (ifu_tlu_imiss_e),
406 
    .q   (imiss_m),
407 
    .clk (clk),
408 
    .se  (se),
409 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
410 95 fafa1971 
    .so  ()
411 
);
412 
//
413 
// staging from m to g stage
414 113 albert.wat 
dff_s dff_pcr_rw_m_g (
415 95 fafa1971 
    .din (pcr_rw_m),
416 
    .q   (pcr_rw_g),
417 
    .clk (clk),
418 
    .se  (se),
419 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
420 95 fafa1971 
    .so  ()
421 
);
422 
 
423 113 albert.wat 
dff_s dff_pic_priv_rw_m_g (
424 95 fafa1971 
    .din (pic_priv_rw_m),
425 
    .q   (pic_priv_rw_g),
426 
    .clk (clk),
427 
    .se  (se),
428 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
429 95 fafa1971 
    .so  ()
430 
);
431 
 
432 113 albert.wat 
dff_s dff_pic_npriv_rw_m_g (
433 95 fafa1971 
    .din (pic_npriv_rw_m),
434 
    .q   (pic_npriv_rw_g),
435 
    .clk (clk),
436 
    .se  (se),
437 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
438 95 fafa1971 
    .so  ()
439 
);
440 
 
441 113 albert.wat 
dff_s dff_imiss_m_g (
442 95 fafa1971 
    .din (imiss_m),
443 
    .q   (imiss_g),
444 
    .clk (clk),
445 
    .se  (se),
446 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
447 95 fafa1971 
    .so  ()
448 
);
449 
 
450 113 albert.wat 
dff_s dff_immu_miss_m_g (
451 95 fafa1971 
    .din (ifu_tlu_immu_miss_m),
452 
    .q   (immu_miss_g),
453 
    .clk (clk),
454 
    .se  (se),
455 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
456 95 fafa1971 
    .so  ()
457 
);
458 
 
459 
//
460 
//=========================
461 
// update for PCR registers
462 
//=========================
463 
//
464 
assign wsr_thread_inst_g[0] =
465 
           tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[0];
466 
assign wsr_thread_inst_g[1] =
467 
           tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[1];
468 
assign wsr_thread_inst_g[2] =
469 
           tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[2];
470 
assign wsr_thread_inst_g[3] =
471 
           tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w & tlu_thread_wsel_g[3];
472 
//
473 
// extracting the relevant bits from the wsr data bus
474 
assign pcr_wdata_in =
475 113 albert.wat 
    {tlu_wsr_data_w[`WSR_PCR_CH_OVF:`WSR_PCR_CL_OVF],
476 
     tlu_wsr_data_w[`WSR_PCR_SL_HI:`WSR_PCR_SL_LO],
477 
     tlu_wsr_data_w[`WSR_PCR_UT:`WSR_PCR_PRIV]};
478 95 fafa1971 
//
479 
// thread 0
480 
assign wsr_pcr_sel[0] = wsr_thread_inst_g[0] & pcr_rw_g;
481 
 
482 
assign update_picl_ovf[0] =
483 
           (wsr_thread_inst_g[0] & pcr_rw_g) |
484 113 albert.wat 
           (picl_cnt_wrap[0] ^ picl_cnt0[`PIB_PIC_CNT_WIDTH-1]);
485 95 fafa1971 
 
486 
assign update_pich_ovf[0] =
487 
           (wsr_thread_inst_g[0] & pcr_rw_g) |
488 113 albert.wat 
           (pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]);
489 95 fafa1971 
//
490 
// modified for bug 2291
491 113 albert.wat 
dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr0 (
492 95 fafa1971 
 //   .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),
493 113 albert.wat 
    .din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),
494 
    .q   (pcr0[`PIB_PCR_WIDTH-3:0]),
495 95 fafa1971 
    .rst (local_rst),
496 
    .en  (wsr_pcr_sel[0]),
497 
    .clk (clk),
498 
    .se  (se),
499 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
500 95 fafa1971 
    .so  ()
501 
);
502 
 
503 
mux2ds mux_pcr0_picl_ovf (
504 113 albert.wat 
        .in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),
505 
        .in1(picl_cnt_wrap[0] ^ picl_cnt0[`PIB_PIC_CNT_WIDTH-1]),
506 95 fafa1971 
        .sel0(wsr_pcr_sel[0]),
507 
        .sel1(~wsr_pcr_sel[0]),
508 
        .dout(picl_ovf_wdata_in[0])
509 
);
510 
 
511 
// added for the new bug 2588
512 113 albert.wat 
dffre_s dffre_pcr0_picl_ovf (
513 95 fafa1971 
    .din (picl_ovf_wdata_in[0]),
514 113 albert.wat 
    .q   (pcr0[`PIB_PCR_CL_OVF]),
515 95 fafa1971 
    .clk (clk),
516 
    .en  (update_picl_ovf[0]),
517 
    .rst (local_rst),
518 
    .se  (se),
519 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
520 95 fafa1971 
    .so  ()
521 
);
522 
 
523 
mux2ds mux_pcr0_pich_ovf (
524 113 albert.wat 
        .in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),
525 
        .in1(pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]),
526 95 fafa1971 
        .sel0(wsr_pcr_sel[0]),
527 
        .sel1(~wsr_pcr_sel[0]),
528 
        .dout(pich_ovf_wdata_in[0])
529 
);
530 
 
531 113 albert.wat 
dffre_s dffre_pcr0_pich_ovf (
532 95 fafa1971 
    .din (pich_ovf_wdata_in[0]),
533 113 albert.wat 
    .q   (pcr0[`PIB_PCR_CH_OVF]),
534 95 fafa1971 
    .clk (clk),
535 
    .en  (update_pich_ovf[0]),
536 
    .rst (local_rst),
537 
    .se  (se),
538 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
539 95 fafa1971 
    .so  ()
540 
);
541 
//
542 
// thread 1
543 
 
544 
assign wsr_pcr_sel[1] = wsr_thread_inst_g[1] & pcr_rw_g;
545 
 
546 
assign update_picl_ovf[1] =
547 
           (wsr_thread_inst_g[1] & pcr_rw_g) |
548 113 albert.wat 
           (picl_cnt_wrap[1] ^ picl_cnt1[`PIB_PIC_CNT_WIDTH-1]);
549 95 fafa1971 
 
550 
assign update_pich_ovf[1] =
551 
           (wsr_thread_inst_g[1] & pcr_rw_g) |
552 113 albert.wat 
           (pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]);
553 95 fafa1971 
 
554 113 albert.wat 
dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr1 (
555 95 fafa1971 
 //   .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),
556 113 albert.wat 
    .din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),
557 
    .q   (pcr1[`PIB_PCR_WIDTH-3:0]),
558 95 fafa1971 
    .rst (local_rst),
559 
    .en  (wsr_pcr_sel[1]),
560 
    .clk (clk),
561 
    .se  (se),
562 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
563 95 fafa1971 
    .so  ()
564 
);
565 
 
566 
mux2ds mux_pcr1_picl_ovf (
567 113 albert.wat 
        .in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),
568 
        .in1(picl_cnt_wrap[1] ^ picl_cnt1[`PIB_PIC_CNT_WIDTH-1]),
569 95 fafa1971 
        .sel0(wsr_pcr_sel[1]),
570 
        .sel1(~wsr_pcr_sel[1]),
571 
        .dout(picl_ovf_wdata_in[1])
572 
);
573 
// added for the new bug 2588
574 113 albert.wat 
dffre_s dffre_pcr1_picl_ovf (
575 95 fafa1971 
    .din (picl_ovf_wdata_in[1]),
576 113 albert.wat 
    .q   (pcr1[`PIB_PCR_CL_OVF]),
577 95 fafa1971 
    .clk (clk),
578 
    .en  (update_picl_ovf[1]),
579 
    .rst (local_rst),
580 
    .se  (se),
581 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
582 95 fafa1971 
    .so  ()
583 
);
584 
 
585 
mux2ds mux_pcr1_pich_ovf (
586 113 albert.wat 
        .in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),
587 
        .in1(pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]),
588 95 fafa1971 
        .sel0(wsr_pcr_sel[1]),
589 
        .sel1(~wsr_pcr_sel[1]),
590 
        .dout(pich_ovf_wdata_in[1])
591 
);
592 
 
593 113 albert.wat 
dffre_s dffre_pcr1_pich_ovf (
594 95 fafa1971 
    .din (pich_ovf_wdata_in[1]),
595 113 albert.wat 
    .q   (pcr1[`PIB_PCR_CH_OVF]),
596 95 fafa1971 
    .clk (clk),
597 
    .en  (update_pich_ovf[1]),
598 
    .rst (local_rst),
599 
    .se  (se),
600 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
601 95 fafa1971 
    .so  ()
602 
);
603 
//
604 
// thread 2
605 
 
606 
assign wsr_pcr_sel[2] = wsr_thread_inst_g[2] & pcr_rw_g;
607 
 
608 
assign update_picl_ovf[2] =
609 
           (wsr_thread_inst_g[2] & pcr_rw_g) |
610 113 albert.wat 
           (picl_cnt_wrap[2] ^ picl_cnt2[`PIB_PIC_CNT_WIDTH-1]);
611 95 fafa1971 
 
612 
assign update_pich_ovf[2] =
613 
           (wsr_thread_inst_g[2] & pcr_rw_g) |
614 113 albert.wat 
           (pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]);
615 95 fafa1971 
 
616 113 albert.wat 
dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr2 (
617 95 fafa1971 
 //   .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),
618 113 albert.wat 
    .din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),
619 
    .q   (pcr2[`PIB_PCR_WIDTH-3:0]),
620 95 fafa1971 
    .rst (local_rst),
621 
    .en  (wsr_pcr_sel[2]),
622 
    .clk (clk),
623 
    .se  (se),
624 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
625 95 fafa1971 
    .so  ()
626 
);
627 
 
628 
mux2ds mux_pcr2_picl_ovf (
629 113 albert.wat 
        .in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),
630 
        .in1(picl_cnt_wrap[2] ^ picl_cnt2[`PIB_PIC_CNT_WIDTH-1]),
631 95 fafa1971 
        .sel0(wsr_pcr_sel[2]),
632 
        .sel1(~wsr_pcr_sel[2]),
633 
        .dout(picl_ovf_wdata_in[2])
634 
);
635 
 
636 
// added for the new bug 2588
637 113 albert.wat 
dffre_s dffre_pcr2_picl_ovf (
638 95 fafa1971 
    .din (picl_ovf_wdata_in[2]),
639 113 albert.wat 
    .q   (pcr2[`PIB_PCR_CL_OVF]),
640 95 fafa1971 
    .clk (clk),
641 
    .en  (update_picl_ovf[2]),
642 
    .rst (local_rst),
643 
    .se  (se),
644 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
645 95 fafa1971 
    .so  ()
646 
);
647 
 
648 
mux2ds mux_pcr2_pich_ovf (
649 113 albert.wat 
        .in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),
650 
        .in1(pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]),
651 95 fafa1971 
        .sel0(wsr_pcr_sel[2]),
652 
        .sel1(~wsr_pcr_sel[2]),
653 
        .dout(pich_ovf_wdata_in[2])
654 
);
655 
 
656 113 albert.wat 
dffre_s dffre_pcr2_pich_ovf (
657 95 fafa1971 
    .din (pich_ovf_wdata_in[2]),
658 113 albert.wat 
    .q   (pcr2[`PIB_PCR_CH_OVF]),
659 95 fafa1971 
    .clk (clk),
660 
    .en  (update_pich_ovf[2]),
661 
    .rst (local_rst),
662 
    .se  (se),
663 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
664 95 fafa1971 
    .so  ()
665 
);
666 
//
667 
// thread 3
668 
 
669 
assign wsr_pcr_sel[3] = wsr_thread_inst_g[3] & pcr_rw_g;
670 
 
671 
assign update_picl_ovf[3] =
672 
           (wsr_thread_inst_g[3] & pcr_rw_g) |
673 113 albert.wat 
           (picl_cnt_wrap[3] ^ picl_cnt3[`PIB_PIC_CNT_WIDTH-1]);
674 95 fafa1971 
 
675 
assign update_pich_ovf[3] =
676 
           (wsr_thread_inst_g[3] & pcr_rw_g) |
677 113 albert.wat 
           (pich_cnt_wrap[3] ^ pich_cnt3[`PIB_PIC_CNT_WIDTH-1]);
678 95 fafa1971 
 
679 113 albert.wat 
dffre_s #(`PIB_PCR_WIDTH-2) dffre_pcr3 (
680 95 fafa1971 
 //   .din (tlu_wsr_data_w[`PIB_PCR_WIDTH-1:0]),
681 113 albert.wat 
    .din (pcr_wdata_in[`PIB_PCR_WIDTH-3:0]),
682 
    .q   (pcr3[`PIB_PCR_WIDTH-3:0]),
683 95 fafa1971 
    .rst (local_rst),
684 
    .en  (wsr_pcr_sel[3]),
685 
    .clk (clk),
686 
    .se  (se),
687 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
688 95 fafa1971 
    .so  ()
689 
);
690 
 
691 
mux2ds mux_pcr3_picl_ovf (
692 113 albert.wat 
        .in0(pcr_wdata_in[`PIB_PCR_CL_OVF]),
693 
        .in1(picl_cnt_wrap[3] ^ picl_cnt3[`PIB_PIC_CNT_WIDTH-1]),
694 95 fafa1971 
        .sel0(wsr_pcr_sel[3]),
695 
        .sel1(~wsr_pcr_sel[3]),
696 
        .dout(picl_ovf_wdata_in[3])
697 
);
698 
 
699 
// added for the new bug 2588
700 113 albert.wat 
dffre_s dffre_pcr3_picl_ovf (
701 95 fafa1971 
    .din (picl_ovf_wdata_in[3]),
702 113 albert.wat 
    .q   (pcr3[`PIB_PCR_CL_OVF]),
703 95 fafa1971 
    .clk (clk),
704 
    .en  (update_picl_ovf[3]),
705 
    .rst (local_rst),
706 
    .se  (se),
707 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
708 95 fafa1971 
    .so  ()
709 
);
710 
 
711 
mux2ds mux_pcr3_pich_ovf (
712 113 albert.wat 
        .in0(pcr_wdata_in[`PIB_PCR_CH_OVF]),
713 
        .in1(pich_cnt_wrap[3] ^ pich_cnt3[`PIB_PIC_CNT_WIDTH-1]),
714 95 fafa1971 
        .sel0(wsr_pcr_sel[3]),
715 
        .sel1(~wsr_pcr_sel[3]),
716 
        .dout(pich_ovf_wdata_in[3])
717 
);
718 
 
719 113 albert.wat 
dffre_s dffre_pcr3_pich_ovf (
720 95 fafa1971 
    .din (pich_ovf_wdata_in[3]),
721 113 albert.wat 
    .q   (pcr3[`PIB_PCR_CH_OVF]),
722 95 fafa1971 
    .clk (clk),
723 
    .en  (update_pich_ovf[3]),
724 
    .rst (local_rst),
725 
    .se  (se),
726 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
727 95 fafa1971 
    .so  ()
728 
);
729 
 
730 
//
731 
//====================
732 
// threading of events
733 
//====================
734 
//
735 
// icache misses
736 
assign imiss_thread_g[0] = imiss_g & tlu_thread_wsel_g[0];
737 
assign imiss_thread_g[1] = imiss_g & tlu_thread_wsel_g[1];
738 
assign imiss_thread_g[2] = imiss_g & tlu_thread_wsel_g[2];
739 
assign imiss_thread_g[3] = imiss_g & tlu_thread_wsel_g[3];
740 
//
741 
// itlb misses
742 
assign immu_miss_thread_g[0] = immu_miss_g & tlu_thread_wsel_g[0];
743 
assign immu_miss_thread_g[1] = immu_miss_g & tlu_thread_wsel_g[1];
744 
assign immu_miss_thread_g[2] = immu_miss_g & tlu_thread_wsel_g[2];
745 
assign immu_miss_thread_g[3] = immu_miss_g & tlu_thread_wsel_g[3];
746 
//
747 
// dtlb misses
748 
assign dmmu_miss_thread_g[0] = lsu_tlu_dmmu_miss_g & tlu_thread_wsel_g[0];
749 
assign dmmu_miss_thread_g[1] = lsu_tlu_dmmu_miss_g & tlu_thread_wsel_g[1];
750 
assign dmmu_miss_thread_g[2] = lsu_tlu_dmmu_miss_g & tlu_thread_wsel_g[2];
751 
assign dmmu_miss_thread_g[3] = lsu_tlu_dmmu_miss_g & tlu_thread_wsel_g[3];
752 
//
753 
// itlb misses
754 
assign fpu_cmplt_thread[0] =
755 
           ffu_tlu_fpu_cmplt & (~ffu_tlu_fpu_tid[0] & ~ffu_tlu_fpu_tid[1]);
756 
assign fpu_cmplt_thread[1] =
757 
           ffu_tlu_fpu_cmplt & (ffu_tlu_fpu_tid[0]  & ~ffu_tlu_fpu_tid[1]);
758 
assign fpu_cmplt_thread[2] =
759 
           ffu_tlu_fpu_cmplt & (~ffu_tlu_fpu_tid[0] &  ffu_tlu_fpu_tid[1]);
760 
assign fpu_cmplt_thread[3] =
761 
           ffu_tlu_fpu_cmplt & (ffu_tlu_fpu_tid[0]  &  ffu_tlu_fpu_tid[1]);
762 
 
763 
//====================
764 
// assigning of events
765 
//====================
766 
//
767 
// thread 0
768 113 albert.wat 
assign picl_event0[`PICL_MASK_SB_FULL]   = lsu_tlu_stb_full_w2[0];
769 
assign picl_event0[`PICL_MASK_FP_INST]   = fpu_cmplt_thread[0];
770 
assign picl_event0[`PICL_MASK_IC_MISS]   = imiss_thread_g[0];
771 
assign picl_event0[`PICL_MASK_DC_MISS]   = lsu_tlu_dcache_miss_w2[0];
772 
assign picl_event0[`PICL_MASK_ITLB_MISS] = immu_miss_thread_g[0];
773 
assign picl_event0[`PICL_MASK_DTLB_MISS] = dmmu_miss_thread_g[0];
774 
assign picl_event0[`PICL_MASK_L2_IMISS]  = ifu_tlu_l2imiss[0];
775 
assign picl_event0[`PICL_MASK_L2_DMISS]  = lsu_tlu_l2_dmiss[0];
776 95 fafa1971 
//
777 
// thread 1
778 113 albert.wat 
assign picl_event1[`PICL_MASK_SB_FULL]   = lsu_tlu_stb_full_w2[1];
779 
assign picl_event1[`PICL_MASK_FP_INST]   = fpu_cmplt_thread[1];
780 
assign picl_event1[`PICL_MASK_IC_MISS]   = imiss_thread_g[1];
781 
assign picl_event1[`PICL_MASK_DC_MISS]   = lsu_tlu_dcache_miss_w2[1];
782 
assign picl_event1[`PICL_MASK_ITLB_MISS] = immu_miss_thread_g[1];
783 
assign picl_event1[`PICL_MASK_DTLB_MISS] = dmmu_miss_thread_g[1];
784 
assign picl_event1[`PICL_MASK_L2_IMISS]  = ifu_tlu_l2imiss[1];
785 
assign picl_event1[`PICL_MASK_L2_DMISS]  = lsu_tlu_l2_dmiss[1];
786 95 fafa1971 
//
787 
// thread 2
788 113 albert.wat 
assign picl_event2[`PICL_MASK_SB_FULL]   = lsu_tlu_stb_full_w2[2];
789 
assign picl_event2[`PICL_MASK_FP_INST]   = fpu_cmplt_thread[2];
790 
assign picl_event2[`PICL_MASK_IC_MISS]   = imiss_thread_g[2];
791 
assign picl_event2[`PICL_MASK_DC_MISS]   = lsu_tlu_dcache_miss_w2[2];
792 
assign picl_event2[`PICL_MASK_ITLB_MISS] = immu_miss_thread_g[2];
793 
assign picl_event2[`PICL_MASK_DTLB_MISS] = dmmu_miss_thread_g[2];
794 
assign picl_event2[`PICL_MASK_L2_IMISS]  = ifu_tlu_l2imiss[2];
795 
assign picl_event2[`PICL_MASK_L2_DMISS]  = lsu_tlu_l2_dmiss[2];
796 95 fafa1971 
//
797 
// thread 3
798 113 albert.wat 
assign picl_event3[`PICL_MASK_SB_FULL]   = lsu_tlu_stb_full_w2[3];
799 
assign picl_event3[`PICL_MASK_FP_INST]   = fpu_cmplt_thread[3];
800 
assign picl_event3[`PICL_MASK_IC_MISS]   = imiss_thread_g[3];
801 
assign picl_event3[`PICL_MASK_DC_MISS]   = lsu_tlu_dcache_miss_w2[3];
802 
assign picl_event3[`PICL_MASK_ITLB_MISS] = immu_miss_thread_g[3];
803 
assign picl_event3[`PICL_MASK_DTLB_MISS] = dmmu_miss_thread_g[3];
804 
assign picl_event3[`PICL_MASK_L2_IMISS]  = ifu_tlu_l2imiss[3];
805 
assign picl_event3[`PICL_MASK_L2_DMISS]  = lsu_tlu_l2_dmiss[3];
806 95 fafa1971 
 
807 
//======================
808 
// decode for PIC events
809 
//======================
810 
//
811 
// thread 0
812 
 
813 
assign pic_cnt_en[0] =
814 113 albert.wat 
            (~tlu_hpstate_priv[0] & ~tlu_pstate_priv[0] & pcr0[`PIB_PCR_UT])   |
815 
            (~tlu_hpstate_enb[0]  & tlu_hpstate_priv[0] & pcr0[`PIB_PCR_ST])   |
816 95 fafa1971 
            (tlu_hpstate_enb[0]   & tlu_pstate_priv[0]  & ~tlu_hpstate_priv[0] &
817 113 albert.wat 
             pcr0[`PIB_PCR_ST]);
818 95 fafa1971 
//
819 
// picl mask decodes
820 113 albert.wat 
assign picl_mask0[`PICL_MASK_SB_FULL] =
821 
           ((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_SB_FULL_CNT) &
822 95 fafa1971 
             pic_cnt_en[0]);
823 113 albert.wat 
assign picl_mask0[`PICL_MASK_FP_INST] =
824 
           ((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_FP_INST_CNT) &
825 95 fafa1971 
             pic_cnt_en[0]);
826 113 albert.wat 
assign picl_mask0[`PICL_MASK_IC_MISS] =
827 
           ((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_IC_MISS_CNT) &
828 95 fafa1971 
             pic_cnt_en[0]);
829 113 albert.wat 
assign picl_mask0[`PICL_MASK_DC_MISS] =
830 
           ((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DC_MISS_CNT) &
831 95 fafa1971 
             pic_cnt_en[0]);
832 113 albert.wat 
assign picl_mask0[`PICL_MASK_ITLB_MISS] =
833 
           ((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_ITLB_MISS_CNT) &
834 95 fafa1971 
             pic_cnt_en[0]);
835 113 albert.wat 
assign picl_mask0[`PICL_MASK_DTLB_MISS] =
836 
           ((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DTLB_MISS_CNT) &
837 95 fafa1971 
             pic_cnt_en[0]);
838 113 albert.wat 
assign picl_mask0[`PICL_MASK_L2_IMISS] =
839 
           ((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_IMISS_CNT) &
840 95 fafa1971 
             pic_cnt_en[0]);
841 113 albert.wat 
assign picl_mask0[`PICL_MASK_L2_DMISS] =
842 
           ((pcr0[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_DMISS_CNT) &
843 95 fafa1971 
             pic_cnt_en[0]);
844 
//
845 
// thread 1
846 
 
847 
assign pic_cnt_en[1] =
848 113 albert.wat 
            (~tlu_hpstate_priv[1] & ~tlu_pstate_priv[1] & pcr1[`PIB_PCR_UT])   |
849 
            (~tlu_hpstate_enb[1]  & tlu_hpstate_priv[1] & pcr1[`PIB_PCR_ST])   |
850 95 fafa1971 
            (tlu_hpstate_enb[1]   & tlu_pstate_priv[1]  & ~tlu_hpstate_priv[1] &
851 113 albert.wat 
             pcr1[`PIB_PCR_ST]);
852 95 fafa1971 
//
853 
// picl mask decodes
854 113 albert.wat 
assign picl_mask1[`PICL_MASK_SB_FULL] =
855 
           ((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_SB_FULL_CNT) &
856 95 fafa1971 
             pic_cnt_en[1]);
857 113 albert.wat 
assign picl_mask1[`PICL_MASK_FP_INST] =
858 
           ((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_FP_INST_CNT) &
859 95 fafa1971 
             pic_cnt_en[1]);
860 113 albert.wat 
assign picl_mask1[`PICL_MASK_IC_MISS] =
861 
           ((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_IC_MISS_CNT) &
862 95 fafa1971 
             pic_cnt_en[1]);
863 113 albert.wat 
assign picl_mask1[`PICL_MASK_DC_MISS] =
864 
           ((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DC_MISS_CNT) &
865 95 fafa1971 
             pic_cnt_en[1]);
866 113 albert.wat 
assign picl_mask1[`PICL_MASK_ITLB_MISS] =
867 
           ((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_ITLB_MISS_CNT) &
868 95 fafa1971 
             pic_cnt_en[1]);
869 113 albert.wat 
assign picl_mask1[`PICL_MASK_DTLB_MISS] =
870 
           ((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DTLB_MISS_CNT) &
871 95 fafa1971 
             pic_cnt_en[1]);
872 113 albert.wat 
assign picl_mask1[`PICL_MASK_L2_IMISS] =
873 
           ((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_IMISS_CNT) &
874 95 fafa1971 
             pic_cnt_en[1]);
875 113 albert.wat 
assign picl_mask1[`PICL_MASK_L2_DMISS] =
876 
           ((pcr1[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_DMISS_CNT) &
877 95 fafa1971 
             pic_cnt_en[1]);
878 
//
879 
// thread 2
880 
 
881 
assign pic_cnt_en[2] =
882 113 albert.wat 
            (~tlu_hpstate_priv[2] & ~tlu_pstate_priv[2] & pcr2[`PIB_PCR_UT])   |
883 
            (~tlu_hpstate_enb[2]  & tlu_hpstate_priv[2] & pcr2[`PIB_PCR_ST])   |
884 95 fafa1971 
            (tlu_hpstate_enb[2]   & tlu_pstate_priv[2]  & ~tlu_hpstate_priv[2] &
885 113 albert.wat 
             pcr2[`PIB_PCR_ST]);
886 95 fafa1971 
//
887 
// picl mask decodes
888 113 albert.wat 
assign picl_mask2[`PICL_MASK_SB_FULL] =
889 
           ((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_SB_FULL_CNT) &
890 95 fafa1971 
             pic_cnt_en[2]);
891 113 albert.wat 
assign picl_mask2[`PICL_MASK_FP_INST] =
892 
           ((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_FP_INST_CNT) &
893 95 fafa1971 
             pic_cnt_en[2]);
894 113 albert.wat 
assign picl_mask2[`PICL_MASK_IC_MISS] =
895 
           ((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_IC_MISS_CNT) &
896 95 fafa1971 
             pic_cnt_en[2]);
897 113 albert.wat 
assign picl_mask2[`PICL_MASK_DC_MISS] =
898 
           ((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DC_MISS_CNT) &
899 95 fafa1971 
             pic_cnt_en[2]);
900 113 albert.wat 
assign picl_mask2[`PICL_MASK_ITLB_MISS] =
901 
           ((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_ITLB_MISS_CNT) &
902 95 fafa1971 
             pic_cnt_en[2]);
903 113 albert.wat 
assign picl_mask2[`PICL_MASK_DTLB_MISS] =
904 
           ((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DTLB_MISS_CNT) &
905 95 fafa1971 
             pic_cnt_en[2]);
906 113 albert.wat 
assign picl_mask2[`PICL_MASK_L2_IMISS] =
907 
           ((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_IMISS_CNT) &
908 95 fafa1971 
             pic_cnt_en[2]);
909 113 albert.wat 
assign picl_mask2[`PICL_MASK_L2_DMISS] =
910 
           ((pcr2[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_DMISS_CNT) &
911 95 fafa1971 
             pic_cnt_en[2]);
912 
//
913 
// thread 3
914 
 
915 
assign pic_cnt_en[3] =
916 113 albert.wat 
            (~tlu_hpstate_priv[3] & ~tlu_pstate_priv[3] & pcr3[`PIB_PCR_UT])   |
917 
            (~tlu_hpstate_enb[3]  & tlu_hpstate_priv[3] & pcr3[`PIB_PCR_ST])   |
918 95 fafa1971 
            (tlu_hpstate_enb[3]   & tlu_pstate_priv[3]  & ~tlu_hpstate_priv[3] &
919 113 albert.wat 
             pcr3[`PIB_PCR_ST]);
920 95 fafa1971 
//
921 
// added for timing
922 113 albert.wat 
dff_s #(`TLU_THRD_NUM) dff_pic_cnt_en_w2 (
923 
    .din (pic_cnt_en[`TLU_THRD_NUM-1:0]),
924 
    .q   (pic_cnt_en_w2[`TLU_THRD_NUM-1:0]),
925 95 fafa1971 
    .clk (clk),
926 
    .se  (se),
927 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
928 95 fafa1971 
    .so  ()
929 
);
930 
 
931 
//
932 
// picl mask decodes
933 113 albert.wat 
assign picl_mask3[`PICL_MASK_SB_FULL] =
934 
           ((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_SB_FULL_CNT) &
935 95 fafa1971 
             pic_cnt_en[3]);
936 113 albert.wat 
assign picl_mask3[`PICL_MASK_FP_INST] =
937 
           ((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_FP_INST_CNT) &
938 95 fafa1971 
             pic_cnt_en[3]);
939 113 albert.wat 
assign picl_mask3[`PICL_MASK_IC_MISS] =
940 
           ((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_IC_MISS_CNT) &
941 95 fafa1971 
             pic_cnt_en[3]);
942 113 albert.wat 
assign picl_mask3[`PICL_MASK_DC_MISS] =
943 
           ((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DC_MISS_CNT) &
944 95 fafa1971 
             pic_cnt_en[3]);
945 113 albert.wat 
assign picl_mask3[`PICL_MASK_ITLB_MISS] =
946 
           ((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_ITLB_MISS_CNT) &
947 95 fafa1971 
             pic_cnt_en[3]);
948 113 albert.wat 
assign picl_mask3[`PICL_MASK_DTLB_MISS] =
949 
           ((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_DTLB_MISS_CNT) &
950 95 fafa1971 
             pic_cnt_en[3]);
951 113 albert.wat 
assign picl_mask3[`PICL_MASK_L2_IMISS] =
952 
           ((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_IMISS_CNT) &
953 95 fafa1971 
             pic_cnt_en[3]);
954 113 albert.wat 
assign picl_mask3[`PICL_MASK_L2_DMISS] =
955 
           ((pcr3[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO] == `PIB_L2_DMISS_CNT) &
956 95 fafa1971 
             pic_cnt_en[3]);
957 
 
958 
//==================================================================
959 
// update the picls - could be sperated into a dp block if needed
960 
//==================================================================
961 
// added for bug 2919
962 
// rrobin scheduler to choose thread to update
963 113 albert.wat 
dffr_s #(2) dffr_pic_update_sel_ctr (
964 95 fafa1971 
    .din (pic_update_sel_incr[1:0]),
965 
    .q   (pic_update_sel_ctr[1:0]),
966 
    .rst (local_rst),
967 
    .clk (clk),
968 
    .se  (se),
969 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
970 95 fafa1971 
    .so  ()
971 
);
972 
 
973 
assign pic_update_sel_incr[1:0] =
974 
           pic_update_sel_ctr[1:0] + 2'b01;
975 
 
976 
assign pic_update_ctl[0] =
977 
           ~|(pic_update_sel_incr[1:0]);
978 
assign pic_update_ctl[1] =
979 
           ~pic_update_sel_incr[1] &  pic_update_sel_incr[0];
980 
assign pic_update_ctl[2] =
981 
           pic_update_sel_incr[1]  & ~pic_update_sel_incr[0];
982 
assign pic_update_ctl[3] =
983 
           &(pic_update_sel_incr[1:0]);
984 
//
985 
// EVQs for PICL
986 
//
987 
// masking events for increment for picl evq update
988 
assign incr_evq_din[0] =
989 113 albert.wat 
           (|(picl_mask0[`PICL_MASK_WIDTH-1:0] &
990 
             picl_event0[`PICL_MASK_WIDTH-1:0]));
991 95 fafa1971 
assign incr_evq_din[1] =
992 113 albert.wat 
           (|(picl_mask1[`PICL_MASK_WIDTH-1:0] &
993 
             picl_event1[`PICL_MASK_WIDTH-1:0]));
994 95 fafa1971 
assign incr_evq_din[2] =
995 113 albert.wat 
           (|(picl_mask2[`PICL_MASK_WIDTH-1:0] &
996 
             picl_event2[`PICL_MASK_WIDTH-1:0]));
997 95 fafa1971 
assign incr_evq_din[3] =
998 113 albert.wat 
           (|(picl_mask3[`PICL_MASK_WIDTH-1:0] &
999 
             picl_event3[`PICL_MASK_WIDTH-1:0]));
1000 95 fafa1971 
//
1001 
// added due to timing
1002 113 albert.wat 
dff_s #(`TLU_THRD_NUM) dff_incr_evq (
1003 
    .din (incr_evq_din[`TLU_THRD_NUM-1:0]),
1004 
    .q   (incr_evq[`TLU_THRD_NUM-1:0]),
1005 95 fafa1971 
    .clk (clk),
1006 
    .se  (se),
1007 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1008 95 fafa1971 
    .so  ()
1009 
);
1010 
//
1011 
// constructing controls to update the picl_evq
1012 
assign update_evq_sel[0] = (local_rst | pic_update_ctl[0] | incr_evq[0]);
1013 
assign update_evq_sel[1] = (local_rst | pic_update_ctl[1] | incr_evq[1]);
1014 
assign update_evq_sel[2] = (local_rst | pic_update_ctl[2] | incr_evq[2]);
1015 
assign update_evq_sel[3] = (local_rst | pic_update_ctl[3] | incr_evq[3]);
1016 
//
1017 
// increment evq count for each thread
1018 
// thread 0
1019 113 albert.wat 
tlu_addern_32 #(`PIB_EVQ_CNT_WIDTH,1) picl_evq0_adder (
1020 
    .din  (picl_evq0[`PIB_EVQ_CNT_WIDTH-1:0]),
1021 95 fafa1971 
    .incr (1'b1),
1022 113 albert.wat 
    .sum  (picl_evq0_sum[`PIB_EVQ_CNT_WIDTH-1:0])
1023 95 fafa1971 
) ;
1024 
 
1025 113 albert.wat 
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_update_evq0_data (
1026 
       .in0  ({`PIB_EVQ_CNT_WIDTH{1'b0}}),
1027 
       .in1  (picl_evq0_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
1028 95 fafa1971 
       .sel0 (local_rst | pic_update_ctl[0]),
1029 
       .sel1 (~(local_rst | pic_update_ctl[0])),
1030 113 albert.wat 
       .dout (update_evq0_data[`PIB_EVQ_CNT_WIDTH-1:0])
1031 95 fafa1971 
);
1032 
 
1033 113 albert.wat 
dffe_s #(`PIB_EVQ_CNT_WIDTH) dff_picl_evq0 (
1034 
    .din (update_evq0_data[`PIB_EVQ_CNT_WIDTH-1:0]),
1035 
    .q   (picl_evq0[`PIB_EVQ_CNT_WIDTH-1:0]),
1036 95 fafa1971 
    .clk (clk),
1037 
    .en  (update_evq_sel[0]),
1038 
    .se  (se),
1039 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1040 95 fafa1971 
    .so  ()
1041 
);
1042 
//
1043 
// thread 1
1044 113 albert.wat 
tlu_addern_32 #(`PIB_EVQ_CNT_WIDTH,1) picl_evq1_adder (
1045 
    .din  (picl_evq1[`PIB_EVQ_CNT_WIDTH-1:0]),
1046 95 fafa1971 
    .incr (1'b1),
1047 113 albert.wat 
    .sum  (picl_evq1_sum[`PIB_EVQ_CNT_WIDTH-1:0])
1048 95 fafa1971 
) ;
1049 
 
1050 113 albert.wat 
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_update_evq1_data (
1051 
       .in0  ({`PIB_EVQ_CNT_WIDTH{1'b0}}),
1052 
       .in1  (picl_evq1_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
1053 95 fafa1971 
       .sel0 (local_rst | pic_update_ctl[1]),
1054 
       .sel1 (~(local_rst | pic_update_ctl[1])),
1055 113 albert.wat 
       .dout (update_evq1_data[`PIB_EVQ_CNT_WIDTH-1:0])
1056 95 fafa1971 
);
1057 
 
1058 113 albert.wat 
dffe_s #(`PIB_EVQ_CNT_WIDTH) dff_picl_evq1 (
1059 
    .din (update_evq1_data[`PIB_EVQ_CNT_WIDTH-1:0]),
1060 
    .q   (picl_evq1[`PIB_EVQ_CNT_WIDTH-1:0]),
1061 95 fafa1971 
    .clk (clk),
1062 
    .en  (update_evq_sel[1]),
1063 
    .se  (se),
1064 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1065 95 fafa1971 
    .so  ()
1066 
);
1067 
//
1068 
// thread 2
1069 113 albert.wat 
tlu_addern_32 #(`PIB_EVQ_CNT_WIDTH,1) picl_evq2_adder (
1070 
    .din  (picl_evq2[`PIB_EVQ_CNT_WIDTH-1:0]),
1071 95 fafa1971 
    .incr (1'b1),
1072 113 albert.wat 
    .sum  (picl_evq2_sum[`PIB_EVQ_CNT_WIDTH-1:0])
1073 95 fafa1971 
) ;
1074 
 
1075 113 albert.wat 
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_update_evq2_data (
1076 
       .in0  ({`PIB_EVQ_CNT_WIDTH{1'b0}}),
1077 
       .in1  (picl_evq2_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
1078 95 fafa1971 
       .sel0 (local_rst | pic_update_ctl[2]),
1079 
       .sel1 (~(local_rst | pic_update_ctl[2])),
1080 113 albert.wat 
       .dout (update_evq2_data[`PIB_EVQ_CNT_WIDTH-1:0])
1081 95 fafa1971 
);
1082 
 
1083 113 albert.wat 
dffe_s #(`PIB_EVQ_CNT_WIDTH) dff_picl_evq2 (
1084 
    .din (update_evq2_data[`PIB_EVQ_CNT_WIDTH-1:0]),
1085 
    .q   (picl_evq2[`PIB_EVQ_CNT_WIDTH-1:0]),
1086 95 fafa1971 
    .clk (clk),
1087 
    .en  (update_evq_sel[2]),
1088 
    .se  (se),
1089 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1090 95 fafa1971 
    .so  ()
1091 
);
1092 
//
1093 
// thread 3
1094 113 albert.wat 
tlu_addern_32 #(`PIB_EVQ_CNT_WIDTH,1) picl_evq3_adder (
1095 
    .din  (picl_evq3[`PIB_EVQ_CNT_WIDTH-1:0]),
1096 95 fafa1971 
    .incr (1'b1),
1097 113 albert.wat 
    .sum  (picl_evq3_sum[`PIB_EVQ_CNT_WIDTH-1:0])
1098 95 fafa1971 
) ;
1099 
 
1100 113 albert.wat 
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_update_evq3_data (
1101 
       .in0  ({`PIB_EVQ_CNT_WIDTH{1'b0}}),
1102 
       .in1  (picl_evq3_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
1103 95 fafa1971 
       .sel0 (local_rst | pic_update_ctl[3]),
1104 
       .sel1 (~(local_rst | pic_update_ctl[3])),
1105 113 albert.wat 
       .dout (update_evq3_data[`PIB_EVQ_CNT_WIDTH-1:0])
1106 95 fafa1971 
);
1107 
 
1108 113 albert.wat 
dffe_s #(`PIB_EVQ_CNT_WIDTH) dff_picl_evq3 (
1109 
    .din (update_evq3_data[`PIB_EVQ_CNT_WIDTH-1:0]),
1110 
    .q   (picl_evq3[`PIB_EVQ_CNT_WIDTH-1:0]),
1111 95 fafa1971 
    .clk (clk),
1112 
    .en  (update_evq_sel[3]),
1113 
    .se  (se),
1114 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1115 95 fafa1971 
    .so  ()
1116 
);
1117 
//
1118 
// selelcting the thread for incrementing for picl
1119 
//
1120 113 albert.wat 
mux4ds #(`PIB_PIC_CNT_WIDTH) mux_picl_cnt_din (
1121 
       .in0  (picl_cnt0[`PIB_PIC_CNT_WIDTH-1:0]),
1122 
       .in1  (picl_cnt1[`PIB_PIC_CNT_WIDTH-1:0]),
1123 
       .in2  (picl_cnt2[`PIB_PIC_CNT_WIDTH-1:0]),
1124 
       .in3  (picl_cnt3[`PIB_PIC_CNT_WIDTH-1:0]),
1125 95 fafa1971 
       .sel0 (pic_update_ctl[0]),
1126 
       .sel1 (pic_update_ctl[1]),
1127 
       .sel2 (pic_update_ctl[2]),
1128 
       .sel3 (pic_update_ctl[3]),
1129 113 albert.wat 
       .dout (picl_cnt_din[`PIB_PIC_CNT_WIDTH-1:0])
1130 95 fafa1971 
);
1131 
//
1132 
// selecting the correct input for incrementing the picl
1133 
// thread0
1134 113 albert.wat 
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq0_din (
1135 
       .in0  (picl_evq0_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
1136 
       .in1  (picl_evq0[`PIB_EVQ_CNT_WIDTH-1:0]),
1137 95 fafa1971 
       .sel0 (incr_evq[0]),
1138 
       .sel1 (~incr_evq[0]),
1139 113 albert.wat 
       .dout (picl_evq0_din[`PIB_EVQ_CNT_WIDTH-1:0])
1140 95 fafa1971 
);
1141 
//
1142 
// thread1
1143 113 albert.wat 
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq1_din (
1144 
       .in0  (picl_evq1_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
1145 
       .in1  (picl_evq1[`PIB_EVQ_CNT_WIDTH-1:0]),
1146 95 fafa1971 
       .sel0 (incr_evq[1]),
1147 
       .sel1 (~incr_evq[1]),
1148 113 albert.wat 
       .dout (picl_evq1_din[`PIB_EVQ_CNT_WIDTH-1:0])
1149 95 fafa1971 
);
1150 
//
1151 
// thread2
1152 113 albert.wat 
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq2_din (
1153 
       .in0  (picl_evq2_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
1154 
       .in1  (picl_evq2[`PIB_EVQ_CNT_WIDTH-1:0]),
1155 95 fafa1971 
       .sel0 (incr_evq[2]),
1156 
       .sel1 (~incr_evq[2]),
1157 113 albert.wat 
       .dout (picl_evq2_din[`PIB_EVQ_CNT_WIDTH-1:0])
1158 95 fafa1971 
);
1159 
//
1160 
// thread3
1161 113 albert.wat 
mux2ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq3_din (
1162 
       .in0  (picl_evq3_sum[`PIB_EVQ_CNT_WIDTH-1:0]),
1163 
       .in1  (picl_evq3[`PIB_EVQ_CNT_WIDTH-1:0]),
1164 95 fafa1971 
       .sel0 (incr_evq[3]),
1165 
       .sel1 (~incr_evq[3]),
1166 113 albert.wat 
       .dout (picl_evq3_din[`PIB_EVQ_CNT_WIDTH-1:0])
1167 95 fafa1971 
);
1168 
 
1169 
//
1170 113 albert.wat 
mux4ds #(`PIB_EVQ_CNT_WIDTH) mux_picl_evq_din (
1171 
       .in0  (picl_evq0_din[`PIB_EVQ_CNT_WIDTH-1:0]),
1172 
       .in1  (picl_evq1_din[`PIB_EVQ_CNT_WIDTH-1:0]),
1173 
       .in2  (picl_evq2_din[`PIB_EVQ_CNT_WIDTH-1:0]),
1174 
       .in3  (picl_evq3_din[`PIB_EVQ_CNT_WIDTH-1:0]),
1175 95 fafa1971 
       .sel0 (pic_update_ctl[0]),
1176 
       .sel1 (pic_update_ctl[1]),
1177 
       .sel2 (pic_update_ctl[2]),
1178 
       .sel3 (pic_update_ctl[3]),
1179 113 albert.wat 
       .dout (picl_evq_din[`PIB_EVQ_CNT_WIDTH-1:0])
1180 95 fafa1971 
);
1181 
//
1182 
// picl incrementor  - shared between four threads
1183 
//
1184 113 albert.wat 
tlu_addern_32 #(`PIB_PIC_CNT_WIDTH,`PIB_EVQ_CNT_WIDTH) picl_adder (
1185 
    .din  (picl_cnt_din[`PIB_PIC_CNT_WIDTH-1:0]),
1186 
    .incr (picl_evq_din[`PIB_EVQ_CNT_WIDTH-1:0]),
1187 
    .sum  (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0])
1188 95 fafa1971 
) ;
1189 
//
1190 
// construction mux selects for picl update
1191 
 
1192 
assign wsr_pic_sel[0] = wsr_thread_inst_g[0] & (pic_npriv_rw_g | pic_priv_rw_g);
1193 
assign wsr_pic_sel[1] = wsr_thread_inst_g[1] & (pic_npriv_rw_g | pic_priv_rw_g);
1194 
assign wsr_pic_sel[2] = wsr_thread_inst_g[2] & (pic_npriv_rw_g | pic_priv_rw_g);
1195 
assign wsr_pic_sel[3] = wsr_thread_inst_g[3] & (pic_npriv_rw_g | pic_priv_rw_g);
1196 
 
1197 
assign update_picl_sel[0] = (local_rst | pic_update_ctl[0] | wsr_pic_sel[0]);
1198 
assign update_picl_sel[1] = (local_rst | pic_update_ctl[1] | wsr_pic_sel[1]);
1199 
assign update_picl_sel[2] = (local_rst | pic_update_ctl[2] | wsr_pic_sel[2]);
1200 
assign update_picl_sel[3] = (local_rst | pic_update_ctl[3] | wsr_pic_sel[3]);
1201 
 
1202 
// constructing the selects to choose to update the pich wrap - added for bug 2588
1203 
assign update_picl_wrap_en[0] =
1204 
           update_picl_sel[0] | wsr_pcr_sel[0];
1205 
assign update_picl_wrap_en[1] =
1206 
           update_picl_sel[1] | wsr_pcr_sel[1];
1207 
assign update_picl_wrap_en[2] =
1208 
           update_picl_sel[2] | wsr_pcr_sel[2];
1209 
assign update_picl_wrap_en[3] =
1210 
           update_picl_sel[3] | wsr_pcr_sel[3];
1211 
//
1212 
// extracting the wsr_data information to update the picls
1213 
//
1214 113 albert.wat 
assign picl_wsr_data = {1'b0, tlu_wsr_data_w[`PIB_PICL_CNT_HI:`PIB_PICL_CNT_LO]};
1215 95 fafa1971 
//
1216 
// selecting the data for picl update
1217 
// thread 0
1218 113 albert.wat 
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_picl0_data (
1219 
       .in0  ({`PIB_PIC_CNT_WIDTH{1'b0}}),
1220 
       .in1  (picl_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
1221 
       .in2  (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
1222 95 fafa1971 
       .sel0 (local_rst),
1223 
       .sel1 (wsr_pic_sel[0] & ~local_rst),
1224 
       .sel2 (~(wsr_pic_sel[0] | local_rst)),
1225 113 albert.wat 
       .dout (update_picl0_data[`PIB_PIC_CNT_WIDTH-1:0])
1226 95 fafa1971 
);
1227 
 
1228 113 albert.wat 
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_picl_cnt0 (
1229 
    .din (update_picl0_data[`PIB_PIC_CNT_WIDTH-1:0]),
1230 
    .q   (picl_cnt0[`PIB_PIC_CNT_WIDTH-1:0]),
1231 95 fafa1971 
    .clk (clk),
1232 
    .en  (update_picl_sel[0]),
1233 
    .se  (se),
1234 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1235 95 fafa1971 
    .so  ()
1236 
);
1237 
//
1238 
// thread 1
1239 113 albert.wat 
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_picl1_data (
1240 
       .in0  ({`PIB_PIC_CNT_WIDTH{1'b0}}),
1241 
       .in1  (picl_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
1242 
       .in2  (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
1243 95 fafa1971 
       .sel0 (local_rst),
1244 
       .sel1 (wsr_pic_sel[1] & ~local_rst),
1245 
       .sel2 (~(wsr_pic_sel[1] | local_rst)),
1246 113 albert.wat 
       .dout (update_picl1_data[`PIB_PIC_CNT_WIDTH-1:0])
1247 95 fafa1971 
);
1248 
 
1249 113 albert.wat 
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_picl_cnt1 (
1250 
    .din (update_picl1_data[`PIB_PIC_CNT_WIDTH-1:0]),
1251 
    .q   (picl_cnt1[`PIB_PIC_CNT_WIDTH-1:0]),
1252 95 fafa1971 
    .clk (clk),
1253 
    .en  (update_picl_sel[1]),
1254 
    .se  (se),
1255 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1256 95 fafa1971 
    .so  ()
1257 
);
1258 
//
1259 
// thread 2
1260 113 albert.wat 
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_picl2_data (
1261 
       .in0  ({`PIB_PIC_CNT_WIDTH{1'b0}}),
1262 
       .in1  (picl_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
1263 
       .in2  (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
1264 95 fafa1971 
       .sel0 (local_rst),
1265 
       .sel1 (wsr_pic_sel[2] & ~local_rst),
1266 
       .sel2 (~(wsr_pic_sel[2] | local_rst)),
1267 113 albert.wat 
       .dout (update_picl2_data[`PIB_PIC_CNT_WIDTH-1:0])
1268 95 fafa1971 
);
1269 
 
1270 113 albert.wat 
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_picl_cnt2 (
1271 
    .din (update_picl2_data[`PIB_PIC_CNT_WIDTH-1:0]),
1272 
    .q   (picl_cnt2[`PIB_PIC_CNT_WIDTH-1:0]),
1273 95 fafa1971 
    .clk (clk),
1274 
    .en  (update_picl_sel[2]),
1275 
    .se  (se),
1276 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1277 95 fafa1971 
    .so  ()
1278 
);
1279 
//
1280 
// thread 3
1281 113 albert.wat 
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_picl3_data (
1282 
       .in0  ({`PIB_PIC_CNT_WIDTH{1'b0}}),
1283 
       .in1  (picl_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
1284 
       .in2  (picl_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
1285 95 fafa1971 
       .sel0 (local_rst),
1286 
       .sel1 (wsr_pic_sel[3] & ~local_rst),
1287 
       .sel2 (~(wsr_pic_sel[3] | local_rst)),
1288 113 albert.wat 
       .dout (update_picl3_data[`PIB_PIC_CNT_WIDTH-1:0])
1289 95 fafa1971 
);
1290 
 
1291 113 albert.wat 
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_picl_cnt3 (
1292 
    .din (update_picl3_data[`PIB_PIC_CNT_WIDTH-1:0]),
1293 
    .q   (picl_cnt3[`PIB_PIC_CNT_WIDTH-1:0]),
1294 95 fafa1971 
    .clk (clk),
1295 
    .en  (update_picl_sel[3]),
1296 
    .se  (se),
1297 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1298 95 fafa1971 
    .so  ()
1299 
);
1300 
 
1301 
//==================================================================
1302 
// update the pichs - could be sperated into a dp block if needed
1303 
//==================================================================
1304 
//
1305 113 albert.wat 
dffr_s #(`TLU_THRD_NUM) dffr_inst_vld_w2 (
1306 
    .din (tlu_thread_inst_vld_g[`TLU_THRD_NUM-1:0]),
1307 
    .q   (inst_vld_w2[`TLU_THRD_NUM-1:0]),
1308 95 fafa1971 
    .clk (clk),
1309 
    .rst (local_rst),
1310 
    .se  (se),
1311 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1312 95 fafa1971 
    .so  ()
1313 
);
1314 
//
1315 
// added for bug 4395
1316 113 albert.wat 
dffr_s dffr_tcc_inst_w2 (
1317 95 fafa1971 
    .din (tlu_tcc_inst_w),
1318 
    .q   (tcc_inst_w2),
1319 
    .clk (clk),
1320 
    .rst (local_rst),
1321 
    .se  (se),
1322 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1323 95 fafa1971 
    .so  ()
1324 
);
1325 
//
1326 
// modified for bug 4478
1327 
assign incr_pich[0] = pic_cnt_en_w2[0] & inst_vld_w2[0] &
1328 
                      (~tlu_full_flush_pipe_w2 | tcc_inst_w2);
1329 
assign incr_pich[1] = pic_cnt_en_w2[1] & inst_vld_w2[1] &
1330 
                      (~tlu_full_flush_pipe_w2 | tcc_inst_w2);
1331 
assign incr_pich[2] = pic_cnt_en_w2[2] & inst_vld_w2[2] &
1332 
                      (~tlu_full_flush_pipe_w2 | tcc_inst_w2);
1333 
assign incr_pich[3] = pic_cnt_en_w2[3] & inst_vld_w2[3] &
1334 
                      (~tlu_full_flush_pipe_w2 | tcc_inst_w2);
1335 
 
1336 
assign pich_mux_sel[0] = pic_cnt_en_w2[0] & inst_vld_w2[0];
1337 
assign pich_mux_sel[1] = pic_cnt_en_w2[1] & inst_vld_w2[1];
1338 
assign pich_mux_sel[2] = pic_cnt_en_w2[2] & inst_vld_w2[2];
1339 
assign pich_mux_sel[3] = pic_cnt_en_w2[3] & inst_vld_w2[3];
1340 
 
1341 
// added for to make inst count overflow trap precise.
1342 
// added for bug 4314
1343 
assign pich_wrap_flg[0] =
1344 113 albert.wat 
           (pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]) & pic_cnt_en_w2[0];
1345 95 fafa1971 
assign pich_wrap_flg[1] =
1346 113 albert.wat 
           (pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]) & pic_cnt_en_w2[1];
1347 95 fafa1971 
assign pich_wrap_flg[2] =
1348 113 albert.wat 
           (pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]) & pic_cnt_en_w2[2];
1349 95 fafa1971 
assign pich_wrap_flg[3] =
1350 113 albert.wat 
           (pich_cnt_wrap[3] ^ pich_cnt3[`PIB_PIC_CNT_WIDTH-1]) & pic_cnt_en_w2[3];
1351 95 fafa1971 
 
1352 
// modified for bug 4270
1353 
// pic experiment
1354 
assign pich_fourbelow_din[0] =
1355 113 albert.wat 
           (&pich_cnt0[`PIB_PIC_CNT_WIDTH-2:2]) & pic_cnt_en_w2[0];
1356 95 fafa1971 
assign pich_fourbelow_din[1] =
1357 113 albert.wat 
           (&pich_cnt1[`PIB_PIC_CNT_WIDTH-2:2]) & pic_cnt_en_w2[1];
1358 95 fafa1971 
assign pich_fourbelow_din[2] =
1359 113 albert.wat 
           (&pich_cnt2[`PIB_PIC_CNT_WIDTH-2:2]) & pic_cnt_en_w2[2];
1360 95 fafa1971 
assign pich_fourbelow_din[3] =
1361 113 albert.wat 
           (&pich_cnt3[`PIB_PIC_CNT_WIDTH-2:2]) & pic_cnt_en_w2[3];
1362 95 fafa1971 
//
1363 113 albert.wat 
dff_s #(`TLU_THRD_NUM) dff_pich_fourbelow_flg (
1364 
    .din (pich_fourbelow_din[`TLU_THRD_NUM-1:0]),
1365 
    .q   (pich_fourbelow_flg[`TLU_THRD_NUM-1:0]),
1366 95 fafa1971 
    .clk (clk),
1367 
    .se  (se),
1368 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1369 95 fafa1971 
    .so  ()
1370 
);
1371 
 
1372 
// modified for bug 4270
1373 
assign pich_onebelow_flg[0] =
1374 
       (pich_fourbelow_flg[0] & pich_cnt0[1] & pich_cnt0[0]) & pic_cnt_en_w2[0];
1375 
assign pich_onebelow_flg[1] =
1376 
       (pich_fourbelow_flg[1] & pich_cnt1[1] & pich_cnt1[0]) & pic_cnt_en_w2[1];
1377 
assign pich_onebelow_flg[2] =
1378 
       (pich_fourbelow_flg[2] & pich_cnt2[1] & pich_cnt2[0]) & pic_cnt_en_w2[2];
1379 
assign pich_onebelow_flg[3] =
1380 
       (pich_fourbelow_flg[3] & pich_cnt3[1] & pich_cnt3[0]) & pic_cnt_en_w2[3];
1381 
//
1382 
assign pich_twobelow_flg[0] =
1383 
       (pich_fourbelow_flg[0] & pich_cnt0[1] & ~pich_cnt0[0]) & pic_cnt_en_w2[0];
1384 
assign pich_twobelow_flg[1] =
1385 
       (pich_fourbelow_flg[1] & pich_cnt1[1] & ~pich_cnt1[0]) & pic_cnt_en_w2[1];
1386 
assign pich_twobelow_flg[2] =
1387 
       (pich_fourbelow_flg[2] & pich_cnt2[1] & ~pich_cnt2[0]) & pic_cnt_en_w2[2];
1388 
assign pich_twobelow_flg[3] =
1389 
       (pich_fourbelow_flg[3] & pich_cnt3[1] & ~pich_cnt3[0]) & pic_cnt_en_w2[3];
1390 
//
1391 
/*
1392 
assign pich_threebelow_flg[0] =
1393 
       (pich_fourbelow_flg[0] & ~pich_cnt0[1] & pich_cnt0[0]) & pic_cnt_en_w2[0];
1394 
assign pich_threebelow_flg[1] =
1395 
       (pich_fourbelow_flg[1] & ~pich_cnt1[1] & pich_cnt1[0]) & pic_cnt_en_w2[1];
1396 
assign pich_threebelow_flg[2] =
1397 
       (pich_fourbelow_flg[2] & ~pich_cnt2[1] & pich_cnt2[0]) & pic_cnt_en_w2[2];
1398 
assign pich_threebelow_flg[3] =
1399 
       (pich_fourbelow_flg[3] & ~pich_cnt3[1] & pich_cnt3[0]) & pic_cnt_en_w2[3];
1400 
*/
1401 
//
1402 
// added for bug 4836
1403 
assign pic_twobelow_e[0] =
1404 
       pich_mux_sel[0]? (pich_fourbelow_flg[0] & ~pich_cnt0[1] & pich_cnt0[0]):
1405 
       (pich_fourbelow_flg[0] & pich_cnt0[1] & ~pich_cnt0[0]);
1406 
assign pic_twobelow_e[1] =
1407 
       pich_mux_sel[1]? (pich_fourbelow_flg[1] & ~pich_cnt1[1] & pich_cnt1[0]):
1408 
       (pich_fourbelow_flg[1] & pich_cnt1[1] & ~pich_cnt1[0]);
1409 
assign pic_twobelow_e[2] =
1410 
       pich_mux_sel[2]? (pich_fourbelow_flg[2] & ~pich_cnt2[1] & pich_cnt2[0]):
1411 
       (pich_fourbelow_flg[2] & pich_cnt2[1] & ~pich_cnt2[0]);
1412 
assign pic_twobelow_e[3] =
1413 
       pich_mux_sel[3]? (pich_fourbelow_flg[3] & ~pich_cnt3[1] & pich_cnt3[0]):
1414 
       (pich_fourbelow_flg[3] & pich_cnt3[1] & ~pich_cnt3[0]);
1415 
 
1416 
assign tlu_pic_twobelow_e =
1417 
           (thread_rsel_e[0]) ? pic_twobelow_e[0]:
1418 
           (thread_rsel_e[1]) ? pic_twobelow_e[1]:
1419 
           (thread_rsel_e[2]) ? pic_twobelow_e[2]:
1420 
            pic_twobelow_e[3];
1421 
//
1422 
assign pic_onebelow_e[0] =
1423 
       pich_mux_sel[0]? (pich_fourbelow_flg[0] & pich_cnt0[1] & ~pich_cnt0[0]):
1424 
       (pich_fourbelow_flg[0] & pich_cnt0[1] & pich_cnt0[0]);
1425 
assign pic_onebelow_e[1] =
1426 
       pich_mux_sel[1]? (pich_fourbelow_flg[1] & pich_cnt1[1] & ~pich_cnt1[0]):
1427 
       (pich_fourbelow_flg[1] & pich_cnt1[1] & pich_cnt1[0]);
1428 
assign pic_onebelow_e[2] =
1429 
       pich_mux_sel[2]? (pich_fourbelow_flg[2] & pich_cnt2[1] & ~pich_cnt2[0]):
1430 
       (pich_fourbelow_flg[2] & pich_cnt2[1] & pich_cnt2[0]);
1431 
assign pic_onebelow_e[3] =
1432 
       pich_mux_sel[3]? (pich_fourbelow_flg[3] & pich_cnt3[1] & ~pich_cnt3[0]):
1433 
       (pich_fourbelow_flg[3] & pich_cnt3[1] & pich_cnt3[0]);
1434 
 
1435 
assign tlu_pic_onebelow_e =
1436 
           (thread_rsel_e[0]) ? pic_onebelow_e[0]:
1437 
           (thread_rsel_e[1]) ? pic_onebelow_e[1]:
1438 
           (thread_rsel_e[2]) ? pic_onebelow_e[2]:
1439 
            pic_onebelow_e[3];
1440 
//
1441 
assign pic_wrap_e[0] =
1442 
       pich_mux_sel[0]? (pich_fourbelow_flg[0] & pich_cnt0[1] & pich_cnt0[0]):
1443 113 albert.wat 
       (pich_cnt_wrap[0] ^ pich_cnt0[`PIB_PIC_CNT_WIDTH-1]);
1444 95 fafa1971 
assign pic_wrap_e[1] =
1445 
       pich_mux_sel[1]? (pich_fourbelow_flg[1] & pich_cnt1[1] & pich_cnt1[0]):
1446 113 albert.wat 
       (pich_cnt_wrap[1] ^ pich_cnt1[`PIB_PIC_CNT_WIDTH-1]);
1447 95 fafa1971 
assign pic_wrap_e[2] =
1448 
       pich_mux_sel[2]? (pich_fourbelow_flg[2] & pich_cnt2[1] & pich_cnt2[0]):
1449 113 albert.wat 
       (pich_cnt_wrap[2] ^ pich_cnt2[`PIB_PIC_CNT_WIDTH-1]);
1450 95 fafa1971 
assign pic_wrap_e[3] =
1451 
       pich_mux_sel[3]? (pich_fourbelow_flg[3] & pich_cnt3[1] & pich_cnt3[0]):
1452 113 albert.wat 
       (pich_cnt_wrap[3] ^ pich_cnt3[`PIB_PIC_CNT_WIDTH-1]);
1453 95 fafa1971 
 
1454 
assign tlu_pic_wrap_e =
1455 
           (thread_rsel_e[0]) ? pic_wrap_e[0]:
1456 
           (thread_rsel_e[1]) ? pic_wrap_e[1]:
1457 
           (thread_rsel_e[2]) ? pic_wrap_e[2]:
1458 
            pic_wrap_e[3];
1459 
//
1460 
//
1461 
// modified for bug 5436: Niagara 2.0
1462 113 albert.wat 
assign tlu_pcr_ut[0] = pcr0[`PIB_PCR_UT];
1463 
assign tlu_pcr_ut[1] = pcr1[`PIB_PCR_UT];
1464 
assign tlu_pcr_ut[2] = pcr2[`PIB_PCR_UT];
1465 
assign tlu_pcr_ut[3] = pcr3[`PIB_PCR_UT];
1466 95 fafa1971 
//
1467 113 albert.wat 
assign tlu_pcr_st[0] = pcr0[`PIB_PCR_ST];
1468 
assign tlu_pcr_st[1] = pcr1[`PIB_PCR_ST];
1469 
assign tlu_pcr_st[2] = pcr2[`PIB_PCR_ST];
1470 
assign tlu_pcr_st[3] = pcr3[`PIB_PCR_ST];
1471 95 fafa1971 
 
1472 
assign tlu_pcr_ut_e =
1473 113 albert.wat 
           (thread_rsel_e[0]) ? pcr0[`PIB_PCR_UT]:
1474 
           (thread_rsel_e[1]) ? pcr1[`PIB_PCR_UT]:
1475 
           (thread_rsel_e[2]) ? pcr2[`PIB_PCR_UT]:
1476 
            pcr3[`PIB_PCR_UT];
1477 95 fafa1971 
 
1478 
assign tlu_pcr_st_e =
1479 113 albert.wat 
           (thread_rsel_e[0]) ? pcr0[`PIB_PCR_ST]:
1480 
           (thread_rsel_e[1]) ? pcr1[`PIB_PCR_ST]:
1481 
           (thread_rsel_e[2]) ? pcr2[`PIB_PCR_ST]:
1482 
            pcr3[`PIB_PCR_ST];
1483 95 fafa1971 
 
1484 
 
1485 
// reporting over-flow trap - needed to be precise, therefore
1486 
// bypassing tlb-miss traps
1487 
//
1488 
// selelcting the thread for incrementing for pich
1489 
// added for bug2332
1490 
//
1491 
// one-hot mux change
1492 113 albert.wat 
assign pich_cnt_din[`PIB_PIC_CNT_WIDTH-1:0] =
1493 
       (pich_mux_sel[1])? pich_cnt1[`PIB_PIC_CNT_WIDTH-1:0]:
1494 
       (pich_mux_sel[2])? pich_cnt2[`PIB_PIC_CNT_WIDTH-1:0]:
1495 
       (pich_mux_sel[3])? pich_cnt3[`PIB_PIC_CNT_WIDTH-1:0]:
1496 
       pich_cnt0[`PIB_PIC_CNT_WIDTH-1:0];
1497 95 fafa1971 
/*
1498 
assign incr_pich_onehot = ~(|incr_pich[3:1]) | rst_tri_en;
1499 
mux4ds #(`PIB_PIC_CNT_WIDTH) mux_pich_cnt_din (
1500 
       .in0  (pich_cnt0[`PIB_PIC_CNT_WIDTH-1:0]),
1501 
       .in1  (pich_cnt1[`PIB_PIC_CNT_WIDTH-1:0]),
1502 
       .in2  (pich_cnt2[`PIB_PIC_CNT_WIDTH-1:0]),
1503 
       .in3  (pich_cnt3[`PIB_PIC_CNT_WIDTH-1:0]),
1504 
       .sel0 (incr_pich_onehot),
1505 
       .sel1 (incr_pich[1] & ~rst_tri_en),
1506 
       .sel2 (incr_pich[2] & ~rst_tri_en),
1507 
       .sel3 (incr_pich[3] & ~rst_tri_en),
1508 
       .dout (pich_cnt_din[`PIB_PIC_CNT_WIDTH-1:0])
1509 
);
1510 
*/
1511 
//
1512 
// pich incrementor  - shared between four threads
1513 
//
1514 113 albert.wat 
tlu_addern_32 #(`PIB_PIC_CNT_WIDTH,1) pich_adder (
1515 
    .din  (pich_cnt_din[`PIB_PIC_CNT_WIDTH-1:0]),
1516 95 fafa1971 
    .incr (1'b1),
1517 113 albert.wat 
    .sum  (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0])
1518 95 fafa1971 
) ;
1519 
//
1520 
// extracting the wsr_data information to update the picls
1521 
//
1522 113 albert.wat 
assign pich_wsr_data = {1'b0, tlu_wsr_data_w[`PIB_PICH_CNT_HI:`PIB_PICH_CNT_LO]};
1523 95 fafa1971 
 
1524 
// constructing the selects to choose to update the pich
1525 
assign update_pich_sel[0] = (local_rst | incr_pich[0] | wsr_pic_sel[0]);
1526 
assign update_pich_sel[1] = (local_rst | incr_pich[1] | wsr_pic_sel[1]);
1527 
assign update_pich_sel[2] = (local_rst | incr_pich[2] | wsr_pic_sel[2]);
1528 
assign update_pich_sel[3] = (local_rst | incr_pich[3] | wsr_pic_sel[3]);
1529 
 
1530 
// constructing the selects to choose to update the pich wrap
1531 
assign update_pich_wrap_en[0] =
1532 
           update_pich_sel[0] | wsr_pcr_sel[0];
1533 
assign update_pich_wrap_en[1] =
1534 
           update_pich_sel[1] | wsr_pcr_sel[1];
1535 
assign update_pich_wrap_en[2] =
1536 
           update_pich_sel[2] | wsr_pcr_sel[2];
1537 
assign update_pich_wrap_en[3] =
1538 
           update_pich_sel[3] | wsr_pcr_sel[3];
1539 
//
1540 
// selecting the data for pich update
1541 
// thread 0
1542 113 albert.wat 
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_pich0_data (
1543 
       .in0  ({`PIB_PIC_CNT_WIDTH{1'b0}}),
1544 
       .in1  (pich_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
1545 
       .in2  (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
1546 95 fafa1971 
       .sel0 (local_rst),
1547 
       .sel1 (wsr_pic_sel[0] & ~local_rst),
1548 
       .sel2 (~(wsr_pic_sel[0] | local_rst)),
1549 113 albert.wat 
       .dout (update_pich0_data[`PIB_PIC_CNT_WIDTH-1:0])
1550 95 fafa1971 
);
1551 
 
1552 113 albert.wat 
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_pich_cnt0 (
1553 
    .din (update_pich0_data[`PIB_PIC_CNT_WIDTH-1:0]),
1554 
    .q   (pich_cnt0[`PIB_PIC_CNT_WIDTH-1:0]),
1555 95 fafa1971 
    .clk (clk),
1556 
    .en  (update_pich_sel[0]),
1557 
    .se  (se),
1558 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1559 95 fafa1971 
    .so  ()
1560 
);
1561 
//
1562 
// thread 1
1563 113 albert.wat 
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_pich1_data (
1564 
       .in0  ({`PIB_PIC_CNT_WIDTH{1'b0}}),
1565 
       .in1  (pich_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
1566 
       .in2  (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
1567 95 fafa1971 
       .sel0 (local_rst),
1568 
       .sel1 (wsr_pic_sel[1] & ~local_rst),
1569 
       .sel2 (~(wsr_pic_sel[1] | local_rst)),
1570 113 albert.wat 
       .dout (update_pich1_data[`PIB_PIC_CNT_WIDTH-1:0])
1571 95 fafa1971 
);
1572 
 
1573 113 albert.wat 
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_pich_cnt1 (
1574 
    .din (update_pich1_data[`PIB_PIC_CNT_WIDTH-1:0]),
1575 
    .q   (pich_cnt1[`PIB_PIC_CNT_WIDTH-1:0]),
1576 95 fafa1971 
    .clk (clk),
1577 
    .en  (update_pich_sel[1]),
1578 
    .se  (se),
1579 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1580 95 fafa1971 
    .so  ()
1581 
);
1582 
//
1583 
// thread 2
1584 113 albert.wat 
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_pich2_data (
1585 
       .in0  ({`PIB_PIC_CNT_WIDTH{1'b0}}),
1586 
       .in1  (pich_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
1587 
       .in2  (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
1588 95 fafa1971 
       .sel0 (local_rst),
1589 
       .sel1 (wsr_pic_sel[2] & ~local_rst),
1590 
       .sel2 (~(wsr_pic_sel[2] | local_rst)),
1591 113 albert.wat 
       .dout (update_pich2_data[`PIB_PIC_CNT_WIDTH-1:0])
1592 95 fafa1971 
);
1593 
 
1594 113 albert.wat 
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_pich_cnt2 (
1595 
    .din (update_pich2_data[`PIB_PIC_CNT_WIDTH-1:0]),
1596 
    .q   (pich_cnt2[`PIB_PIC_CNT_WIDTH-1:0]),
1597 95 fafa1971 
    .clk (clk),
1598 
    .en  (update_pich_sel[2]),
1599 
    .se  (se),
1600 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1601 95 fafa1971 
    .so  ()
1602 
);
1603 
//
1604 
// thread 3
1605 113 albert.wat 
mux3ds #(`PIB_PIC_CNT_WIDTH) mux_update_pich3_data (
1606 
       .in0  ({`PIB_PIC_CNT_WIDTH{1'b0}}),
1607 
       .in1  (pich_wsr_data[`PIB_PIC_CNT_WIDTH-1:0]),
1608 
       .in2  (pich_cnt_sum[`PIB_PIC_CNT_WIDTH-1:0]),
1609 95 fafa1971 
       .sel0 (local_rst),
1610 
       .sel1 (wsr_pic_sel[3] & ~local_rst),
1611 
       .sel2 (~(wsr_pic_sel[3] | local_rst)),
1612 113 albert.wat 
       .dout (update_pich3_data[`PIB_PIC_CNT_WIDTH-1:0])
1613 95 fafa1971 
);
1614 
 
1615 113 albert.wat 
dffe_s #(`PIB_PIC_CNT_WIDTH) dff_pich_cnt3 (
1616 
    .din (update_pich3_data[`PIB_PIC_CNT_WIDTH-1:0]),
1617 
    .q   (pich_cnt3[`PIB_PIC_CNT_WIDTH-1:0]),
1618 95 fafa1971 
    .clk (clk),
1619 
    .en  (update_pich_sel[3]),
1620 
    .se  (se),
1621 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1622 95 fafa1971 
    .so  ()
1623 
);
1624 
 
1625 
//==========================
1626 
// reading the PCRs and PICs
1627 
//==========================
1628 
// decoding the thread information for rsr instruction from IFU
1629 
// modified due to timing
1630 
/*
1631 
assign thread_rsel_e[0] = ~(|ifu_tlu_thrid_e[1:0]);
1632 
assign thread_rsel_e[1] = ~ifu_tlu_thrid_e[1] &  ifu_tlu_thrid_e[0];
1633 
assign thread_rsel_e[2] =  ifu_tlu_thrid_e[1] & ~ifu_tlu_thrid_e[0];
1634 
assign thread_rsel_e[3] =  (&ifu_tlu_thrid_e[1:0]);
1635 
*/
1636 
assign thread_rsel_d[0] = ~(|ifu_tlu_thrid_d[1:0]);
1637 
assign thread_rsel_d[1] = ~ifu_tlu_thrid_d[1] &  ifu_tlu_thrid_d[0];
1638 
assign thread_rsel_d[2] =  ifu_tlu_thrid_d[1] & ~ifu_tlu_thrid_d[0];
1639 
// assign thread_rsel_d[3] =  (&ifu_tlu_thrid_d[1:0]);
1640 
//
1641 113 albert.wat 
dff_s #(`TLU_THRD_NUM-1) dff_thread_rsel_e (
1642 
    .din (thread_rsel_d[`TLU_THRD_NUM-2:0]),
1643 
    .q   (thread_rsel_e[`TLU_THRD_NUM-2:0]),
1644 95 fafa1971 
    .clk (clk),
1645 
    .se  (se),
1646 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1647 95 fafa1971 
    .so  ()
1648 
);
1649 
// selecting the correct pic for rdpr
1650 
// modified to avoid rte failure
1651 113 albert.wat 
assign pic_rdata_e[`TLU_ASR_DATA_WIDTH-1:0] =
1652 95 fafa1971 
       (thread_rsel_e[0])?
1653 113 albert.wat 
       {pich_cnt0[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt0[`PIB_PIC_CNT_WIDTH-2:0]}:
1654 95 fafa1971 
       (thread_rsel_e[1])?
1655 113 albert.wat 
       {pich_cnt1[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt1[`PIB_PIC_CNT_WIDTH-2:0]}:
1656 95 fafa1971 
       (thread_rsel_e[2])?
1657 113 albert.wat 
       {pich_cnt2[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt2[`PIB_PIC_CNT_WIDTH-2:0]}:
1658 
       {pich_cnt3[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt3[`PIB_PIC_CNT_WIDTH-2:0]};
1659 95 fafa1971 
/*
1660 
mux4ds #(`TLU_ASR_DATA_WIDTH) mux_pic_rdata (
1661 
        .in0    ({pich_cnt0[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt0[`PIB_PIC_CNT_WIDTH-2:0]}),
1662 
        .in1    ({pich_cnt1[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt1[`PIB_PIC_CNT_WIDTH-2:0]}),
1663 
        .in2    ({pich_cnt2[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt2[`PIB_PIC_CNT_WIDTH-2:0]}),
1664 
        .in3    ({pich_cnt3[`PIB_PIC_CNT_WIDTH-2:0], picl_cnt3[`PIB_PIC_CNT_WIDTH-2:0]}),
1665 
        .sel0   (thread_rsel_e[0]),
1666 
        .sel1   (thread_rsel_e[1]),
1667 
        .sel2   (thread_rsel_e[2]),
1668 
        .sel3   (thread_rsel_e[3]),
1669 
        .dout   (pic_rdata_e[`TLU_ASR_DATA_WIDTH-1:0])
1670 
);
1671 
 
1672 
// selecting the correct pcr for rdpr
1673 
// modified for bug 2391
1674 
mux4ds #(`TLU_ASR_DATA_WIDTH) mux_pcr_rdata (
1675 
        .in0    ({58'b0,pcr0[`PIB_PCR_WIDTH-1:0]}),
1676 
        .in1    ({58'b0,pcr1[`PIB_PCR_WIDTH-1:0]}),
1677 
        .in2    ({58'b0,pcr2[`PIB_PCR_WIDTH-1:0]}),
1678 
        .in3    ({58'b0,pcr3[`PIB_PCR_WIDTH-1:0]}),
1679 
        .sel0   (thread_rsel_e[0]),
1680 
        .sel1   (thread_rsel_e[1]),
1681 
        .sel2   (thread_rsel_e[2]),
1682 
        .sel3   (thread_rsel_e[3]),
1683 
        .dout   (pcr_rdata_e[`TLU_ASR_DATA_WIDTH-1:0])
1684 
);
1685 
 
1686 
mux4ds #(`PIB_PCR_WIDTH) mux_pcr_rdata (
1687 
        .in0    (pcr0[`PIB_PCR_WIDTH-1:0]),
1688 
        .in1    (pcr1[`PIB_PCR_WIDTH-1:0]),
1689 
        .in2    (pcr2[`PIB_PCR_WIDTH-1:0]),
1690 
        .in3    (pcr3[`PIB_PCR_WIDTH-1:0]),
1691 
        .sel0   (thread_rsel_e[0]),
1692 
        .sel1   (thread_rsel_e[1]),
1693 
        .sel2   (thread_rsel_e[2]),
1694 
        .sel3   (thread_rsel_e[3]),
1695 
        .dout   (pcr_reg_rdata_e[`PIB_PCR_WIDTH-1:0])
1696 
);
1697 
*/
1698 
 
1699 113 albert.wat 
assign pcr_reg_rdata_e[`PIB_PCR_WIDTH-1:0] =
1700 
       (thread_rsel_e[0])? pcr0[`PIB_PCR_WIDTH-1:0]:
1701 
       (thread_rsel_e[1])? pcr1[`PIB_PCR_WIDTH-1:0]:
1702 
       (thread_rsel_e[2])? pcr2[`PIB_PCR_WIDTH-1:0]:
1703 
       pcr3[`PIB_PCR_WIDTH-1:0];
1704 95 fafa1971 
 
1705 113 albert.wat 
assign pcr_rdata_e[`TLU_ASR_DATA_WIDTH-1:0] =
1706 95 fafa1971 
           {54'b0, // rsvd bits
1707 113 albert.wat 
            pcr_reg_rdata_e[`PIB_PCR_CH_OVF:`PIB_PCR_CL_OVF],
1708 95 fafa1971 
            1'b0,  // rsvd bit
1709 113 albert.wat 
            pcr_reg_rdata_e[`PIB_PCR_SL_HI:`PIB_PCR_SL_LO],
1710 95 fafa1971 
            1'b0,  // rsvd bit
1711 113 albert.wat 
            pcr_reg_rdata_e[`PIB_PCR_UT:`PIB_PCR_PRIV]};
1712 95 fafa1971 
 
1713 
// constructing the mux select for the output mux for rsr inst
1714 
assign rsr_data_sel_e[0] = pcr_rw_e;
1715 
assign rsr_data_sel_e[1] = ~pcr_rw_e;
1716 
 
1717 
// modified due to timing
1718 
// assign rsr_data_sel_e[1] = ~pcr_rw_e & (pic_npriv_rw_e | pic_priv_rw_e);
1719 
// assign rsr_data_sel_e[2] = ~(|rsr_data_sel_e[1:0]);
1720 
/*
1721 
mux3ds #(`TLU_ASR_DATA_WIDTH) mux_exu_rsr_data_e (
1722 
        .in0(pcr_rdata_e[`TLU_ASR_DATA_WIDTH-1:0]),
1723 
        .in1(pic_rdata_e[`TLU_ASR_DATA_WIDTH-1:0]),
1724 
        .in2(tlu_pib_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0]),
1725 
        .sel0(rsr_data_sel_e[0]),
1726 
        .sel1(rsr_data_sel_e[1]),
1727 
        .sel2(rsr_data_sel_e[2]),
1728 
        .dout(tlu_exu_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0])
1729 
);
1730 
*/
1731 113 albert.wat 
mux2ds #(`TLU_ASR_DATA_WIDTH) mux_tlu_pib_rsr_data_e (
1732 
        .in0(pcr_rdata_e[`TLU_ASR_DATA_WIDTH-1:0]),
1733 
        .in1(pic_rdata_e[`TLU_ASR_DATA_WIDTH-1:0]),
1734 95 fafa1971 
        .sel0(rsr_data_sel_e[0]),
1735 
        .sel1(rsr_data_sel_e[1]),
1736 113 albert.wat 
        .dout(tlu_pib_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0])
1737 95 fafa1971 
);
1738 
//==========================
1739 
// over_flow trap
1740 
//==========================
1741 
// staged the wrap bit for comparison
1742 
//
1743 
// thread 0 - modified for bug 3937
1744 
mux2ds mux_picl_cnt_wrap_datain_0 (
1745 113 albert.wat 
        .in0(picl_cnt0[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]),
1746 
        .in1(picl_cnt0[`PIB_PIC_CNT_WIDTH-1]),
1747 95 fafa1971 
        .sel0(wsr_pcr_sel[0]),
1748 
        .sel1(~wsr_pcr_sel[0]),
1749 
        .dout(picl_cnt_wrap_datain[0])
1750 
);
1751 
 
1752 
mux2ds mux_pich_cnt_wrap_datain_0 (
1753 113 albert.wat 
        .in0(pich_cnt0[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]),
1754 
        .in1(pich_cnt0[`PIB_PIC_CNT_WIDTH-1]),
1755 95 fafa1971 
        .sel0(wsr_pcr_sel[0]),
1756 
        .sel1(~wsr_pcr_sel[0]),
1757 
        .dout(pich_cnt_wrap_datain[0])
1758 
);
1759 
/*
1760 
assign picl_cnt_wrap_datain[0] =
1761 
           (picl_cnt0[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]);
1762 
 
1763 
assign pich_cnt_wrap_datain[0] =
1764 
           (pich_cnt0[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]);
1765 
*/
1766 
 
1767 113 albert.wat 
dffre_s dffre_picl0_wrap (
1768 95 fafa1971 
    .din (picl_cnt_wrap_datain[0]),
1769 
    .q   (picl_cnt_wrap[0]),
1770 
    .clk (clk),
1771 
    .en  (update_picl_wrap_en[0]),
1772 
    .rst (local_rst | wsr_pic_sel[0]),
1773 
    .se  (se),
1774 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1775 95 fafa1971 
    .so  ()
1776 
);
1777 
 
1778 113 albert.wat 
dffre_s dffre_pich0_wrap (
1779 95 fafa1971 
    .din (pich_cnt_wrap_datain[0]),
1780 
    .q   (pich_cnt_wrap[0]),
1781 
    .clk (clk),
1782 
    .en  (update_pich_wrap_en[0]),
1783 
    .rst (local_rst | wsr_pic_sel[0]),
1784 
    .se  (se),
1785 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1786 95 fafa1971 
    .so  ()
1787 
);
1788 
//
1789 
// thread 1 - modified for bug 3937
1790 
mux2ds mux_picl_cnt_wrap_datain_1 (
1791 113 albert.wat 
        .in0(picl_cnt1[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]),
1792 
        .in1(picl_cnt1[`PIB_PIC_CNT_WIDTH-1]),
1793 95 fafa1971 
        .sel0(wsr_pcr_sel[1]),
1794 
        .sel1(~wsr_pcr_sel[1]),
1795 
        .dout(picl_cnt_wrap_datain[1])
1796 
);
1797 
 
1798 
mux2ds mux_pich_cnt_wrap_datain_1 (
1799 113 albert.wat 
        .in0(pich_cnt1[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]),
1800 
        .in1(pich_cnt1[`PIB_PIC_CNT_WIDTH-1]),
1801 95 fafa1971 
        .sel0(wsr_pcr_sel[1]),
1802 
        .sel1(~wsr_pcr_sel[1]),
1803 
        .dout(pich_cnt_wrap_datain[1])
1804 
);
1805 
/*
1806 
assign picl_cnt_wrap_datain[1] =
1807 
           (picl_cnt1[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]);
1808 
 
1809 
assign pich_cnt_wrap_datain[1] =
1810 
           (pich_cnt1[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]);
1811 
*/
1812 
 
1813 113 albert.wat 
dffre_s dffre_picl1_wrap (
1814 95 fafa1971 
    .din (picl_cnt_wrap_datain[1]),
1815 
    .q   (picl_cnt_wrap[1]),
1816 
    .clk (clk),
1817 
    .en  (update_picl_wrap_en[1]),
1818 
    .rst (local_rst | wsr_pic_sel[1]),
1819 
    .se  (se),
1820 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1821 95 fafa1971 
    .so  ()
1822 
);
1823 
 
1824 113 albert.wat 
dffre_s dffre_pich1_wrap (
1825 95 fafa1971 
    .din (pich_cnt_wrap_datain[1]),
1826 
    .q   (pich_cnt_wrap[1]),
1827 
    .clk (clk),
1828 
    .en  (update_pich_wrap_en[1]),
1829 
    .rst (local_rst | wsr_pic_sel[1]),
1830 
    .se  (se),
1831 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1832 95 fafa1971 
    .so  ()
1833 
);
1834 
//
1835 
// thread 2 - modified for bug 3937
1836 
mux2ds mux_picl_cnt_wrap_datain_2 (
1837 113 albert.wat 
        .in0(picl_cnt2[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]),
1838 
        .in1(picl_cnt2[`PIB_PIC_CNT_WIDTH-1]),
1839 95 fafa1971 
        .sel0(wsr_pcr_sel[2]),
1840 
        .sel1(~wsr_pcr_sel[2]),
1841 
        .dout(picl_cnt_wrap_datain[2])
1842 
);
1843 
 
1844 
mux2ds mux_pich_cnt_wrap_datain_2 (
1845 113 albert.wat 
        .in0(pich_cnt2[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]),
1846 
        .in1(pich_cnt2[`PIB_PIC_CNT_WIDTH-1]),
1847 95 fafa1971 
        .sel0(wsr_pcr_sel[2]),
1848 
        .sel1(~wsr_pcr_sel[2]),
1849 
        .dout(pich_cnt_wrap_datain[2])
1850 
);
1851 
/*
1852 
assign picl_cnt_wrap_datain[2] =
1853 
           (picl_cnt2[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]);
1854 
 
1855 
assign pich_cnt_wrap_datain[2] =
1856 
           (pich_cnt2[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]);
1857 
*/
1858 
 
1859 113 albert.wat 
dffre_s dffre_picl2_wrap (
1860 95 fafa1971 
    .din (picl_cnt_wrap_datain[2]),
1861 
    .q   (picl_cnt_wrap[2]),
1862 
    .clk (clk),
1863 
    .en  (update_picl_wrap_en[2]),
1864 
    .rst (local_rst | wsr_pic_sel[2]),
1865 
    .se  (se),
1866 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1867 95 fafa1971 
    .so  ()
1868 
);
1869 
 
1870 113 albert.wat 
dffre_s dffre_pich2_wrap (
1871 95 fafa1971 
    .din (pich_cnt_wrap_datain[2]),
1872 
    .q   (pich_cnt_wrap[2]),
1873 
    .clk (clk),
1874 
    .en  (update_pich_wrap_en[2]),
1875 
    .rst (local_rst | wsr_pic_sel[2]),
1876 
    .se  (se),
1877 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1878 95 fafa1971 
    .so  ()
1879 
);
1880 
//
1881 
// thread 3 - modified for bug 3937
1882 
mux2ds mux_picl_cnt_wrap_datain_3 (
1883 113 albert.wat 
        .in0(picl_cnt3[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]),
1884 
        .in1(picl_cnt3[`PIB_PIC_CNT_WIDTH-1]),
1885 95 fafa1971 
        .sel0(wsr_pcr_sel[3]),
1886 
        .sel1(~wsr_pcr_sel[3]),
1887 
        .dout(picl_cnt_wrap_datain[3])
1888 
);
1889 
 
1890 
mux2ds mux_pich_cnt_wrap_datain_3 (
1891 113 albert.wat 
        .in0(pich_cnt3[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]),
1892 
        .in1(pich_cnt3[`PIB_PIC_CNT_WIDTH-1]),
1893 95 fafa1971 
        .sel0(wsr_pcr_sel[3]),
1894 
        .sel1(~wsr_pcr_sel[3]),
1895 
        .dout(pich_cnt_wrap_datain[3])
1896 
);
1897 
/*
1898 
assign picl_cnt_wrap_datain[3] =
1899 
           (picl_cnt3[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CL_OVF]);
1900 
 
1901 
assign pich_cnt_wrap_datain[3] =
1902 
           (pich_cnt3[`PIB_PIC_CNT_WIDTH-1] ^ pcr_wdata_in[`PIB_PCR_CH_OVF]);
1903 
*/
1904 
 
1905 113 albert.wat 
dffre_s dffre_picl3_wrap (
1906 95 fafa1971 
    .din (picl_cnt_wrap_datain[3]),
1907 
    .q   (picl_cnt_wrap[3]),
1908 
    .clk (clk),
1909 
    .en  (update_picl_wrap_en[3]),
1910 
    .rst (local_rst | wsr_pic_sel[3]),
1911 
    .se  (se),
1912 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1913 95 fafa1971 
    .so  ()
1914 
);
1915 
 
1916 113 albert.wat 
dffre_s dffre_pich3_wrap (
1917 95 fafa1971 
    .din (pich_cnt_wrap_datain[3]),
1918 
    .q   (pich_cnt_wrap[3]),
1919 
    .clk (clk),
1920 
    .en  (update_pich_wrap_en[3]),
1921 
    .rst (local_rst | wsr_pic_sel[3]),
1922 
    .se  (se),
1923 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1924 95 fafa1971 
    .so  ()
1925 
);
1926 
//
1927 
// generating the over-flow (0->1) to be set in sftint[15]
1928 
assign pib_picl_wrap[0] =
1929 113 albert.wat 
         ((picl_cnt_wrap[0] ^ picl_cnt0[`PIB_PIC_CNT_WIDTH-1]) & incr_evq[0]);
1930 95 fafa1971 
assign pib_picl_wrap[1] =
1931 113 albert.wat 
         ((picl_cnt_wrap[1] ^ picl_cnt1[`PIB_PIC_CNT_WIDTH-1]) & incr_evq[1]);
1932 95 fafa1971 
assign pib_picl_wrap[2] =
1933 113 albert.wat 
         ((picl_cnt_wrap[2] ^ picl_cnt2[`PIB_PIC_CNT_WIDTH-1]) & incr_evq[2]);
1934 95 fafa1971 
assign pib_picl_wrap[3] =
1935 113 albert.wat 
         ((picl_cnt_wrap[3] ^ picl_cnt3[`PIB_PIC_CNT_WIDTH-1]) & incr_evq[3]);
1936 95 fafa1971 
//
1937 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.