OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [tlu_tcl.v] - Blame information for rev 113

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 95 fafa1971
// ========== Copyright Header Begin ==========================================
2
// 
3
// OpenSPARC T1 Processor File: tlu_tcl.v
4
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6
// 
7
// The above named program is free software; you can redistribute it and/or
8
// modify it under the terms of the GNU General Public
9
// License version 2 as published by the Free Software Foundation.
10
// 
11
// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
// General Public License for more details.
15
// 
16
// You should have received a copy of the GNU General Public
17
// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19
// 
20
// ========== Copyright Header End ============================================
21 113 albert.wat
`ifdef SIMPLY_RISC_TWEAKS
22
`define SIMPLY_RISC_SCANIN .si(0)
23
`else
24
`define SIMPLY_RISC_SCANIN .si()
25
`endif
26 95 fafa1971
////////////////////////////////////////////////////////////////////
27
/*
28
//      Description:    Trap Control Logic
29
*/
30
 
31
////////////////////////////////////////////////////////////////////////
32
// Local header file includes / local defines
33
////////////////////////////////////////////////////////////////////////
34 113 albert.wat
`include "tlu.h"
35 95 fafa1971
 
36
module tlu_tcl (/*AUTOARG*/
37
   // Outputs
38
   tlu_ifu_trappc_vld_w1, tlu_ifu_trapnpc_vld_w1, tlu_ifu_trap_tid_w1,
39
   tlu_trap_hpstate_enb, tsa_wr_tpl, tsa_rd_tid, tsa_rd_tpl, tsa_rd_en,
40
   tsa_wr_tid, tsa_wr_vld, tsa_rd_vld_e, tlu_lsu_tl_zero, tlu_restore_pc_sel_w1,
41
   tlu_early_flush_pipe_w, tlu_early_flush_pipe2_w, tlu_exu_early_flush_pipe_w,
42
   tlu_agp_tid_w2, tsa_tstate_en, tsa_ttype_en, tlu_tl_gt_0_w2,
43
   tlu_exu_agp_tid, tlu_true_pc_sel_w, // tlu_retry_inst_m, tlu_done_inst_m, 
44
   tlu_tick_en_l, tlu_tickcmp_en_l, tlu_stickcmp_en_l, tlu_local_flush_w,
45
   tlu_tba_en_l, tlu_thrd_wsel_w2, tlu_thread_wsel_g, tlu_final_ttype_w2,
46
   tlu_thread_inst_vld_g, tlu_update_pc_l_w, tlu_htickcmp_en_l,
47
   tsa_pc_en, tsa_npc_en, tlu_hyperv_rdpr_sel, tlu_wsr_inst_nq_g,
48
   tlu_exu_priv_trap_m, tlu_ibrkpt_trap_w2, tlu_full_flush_pipe_w2,
49
   tlu_pstate_din_sel0, tlu_pstate_din_sel1, tlu_pstate_din_sel2,
50
   tlu_pstate_din_sel3, tlu_update_pstate_l_w2, tlu_trp_lvl,
51
   tlu_pil, tlu_wr_tsa_inst_w2, tlu_trap_cwp_en, // tlu_lsu_priv_trap_w,
52
   tlu_exu_cwp_retry_m, tlu_exu_cwpccr_update_m, tlu_lsu_priv_trap_m,
53
   tlu_lsu_asi_update_m, tlu_lsu_tid_m, tlu_pc_mxsel_w2, // tlu_lsu_asi_m,
54
   tlu_select_tba_w2, tdp_select_tba_w2, tlu_set_sftint_l_g,
55
   tlu_clr_sftint_l_g, tlu_wr_sftint_l_g, tlu_sftint_mx_sel, tlu_itag_acc_sel_g,
56
   tlu_sftint_en_l_g, tlu_sftint_penc_sel, tlu_sftint_vld, tlu_int_tid_m,
57
   tlu_tickcmp_sel, tlu_incr_tick, immu_sfsr_trp_wr, tlu_select_redmode,
58
   tlu_isfsr_din_g, // tlu_dsfsr_din_g, tlu_tag_access_ctxt_sel_m, 
59
   tlu_tick_npt, tlu_thrd_rsel_e, tlu_inst_vld_nq_m, tlu_pic_cnt_en_m,
60
   tlu_rdpr_mx1_sel, tlu_rdpr_mx2_sel, tlu_rdpr_mx3_sel, tlu_rdpr_mx4_sel,
61
   tlu_rdpr_mx5_sel, tlu_rdpr_mx6_sel, tlu_rdpr_mx7_sel, tlu_lsu_pstate_am,
62
   tlu_lsu_redmode_rst_d1, lsu_tlu_rsr_data_mod_e, tlu_addr_msk_g,
63
   // added for hypervisor support
64
   tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g, tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g,
65
   tlu_thrd_traps_w2, tlu_tick_ctl_din, tsa_htstate_en, tlu_por_rstint_g,
66
   tlu_hintp_vld, tlu_rerr_vld, tlu_final_offset_w1, // tlu_ifu_trapnpc_w2, 
67
   so, tlu_sscan_tcl_data, tlu_rst, // tlu_ifu_trappc_w2, tlu_rst_l, 
68
   // Inputs
69
   ifu_tlu_sraddr_d, ifu_tlu_rsr_inst_d, lsu_tlu_early_flush_w, ifu_tlu_pc_oor_e,
70
   tlu_wsr_data_b63_w, tlu_wsr_data_w, lsu_tlu_ttype_m2, ifu_tlu_flush_fd_w,
71
   lsu_tlu_ttype_vld_m2, ifu_tlu_done_inst_d, ifu_tlu_retry_inst_d, ifu_tlu_ttype_m,
72
   ifu_tlu_ttype_vld_m, exu_tlu_ttype_m, exu_tlu_ttype_vld_m, exu_tlu_spill,
73
   exu_tlu_spill_other, exu_tlu_spill_wtype, exu_tlu_va_oor_m, exu_tlu_spill_tid,
74
   ifu_tlu_sir_inst_m, ifu_tlu_inst_vld_m, ifu_tlu_thrid_d, tlu_tckctr_in,
75
   ifu_tlu_immu_miss_m, exu_tlu_va_oor_jl_ret_m, ifu_tlu_trap_m, lsu_tlu_wsr_inst_e,
76
   exu_tlu_cwp_cmplt, exu_tlu_cwp_retry, exu_tlu_cwp_cmplt_tid, exu_tlu_ue_trap_m,
77
   ifu_tlu_rstint_m, ifu_tlu_hwint_m, ifu_tlu_swint_m, pich_wrap_flg, tlu_pic_wrap_e,
78
   pich_onebelow_flg, pich_twobelow_flg, pib_picl_wrap, pib_pich_wrap, tlu_tcc_inst_w,
79
   int_tlu_rstid_m, tlu_int_pstate_ie, tlu_int_redmode, ifu_npc_w, tlu_pcr_ut,
80
   tlu_sftint_id, lsu_tlu_async_ttype_vld_g, lsu_tlu_defr_trp_taken_g, tlu_pcr_st,
81
   lsu_tlu_misalign_addr_ldst_atm_m, exu_tlu_misalign_addr_jmpl_rtn_m,
82
   lsu_tlu_async_tid_g, lsu_tlu_priv_action_g, lsu_tlu_async_ttype_g, lsu_tlu_wtchpt_trp_g,
83
   ifu_tlu_priv_violtn_m, ifu_lsu_memref_d, tlu_pstate_priv, tlu_isfsr_flt_vld,
84
   tlu_pstate_am, ffu_tlu_trap_ieee754, ffu_tlu_trap_other, ffu_tlu_trap_ue,
85
   ffu_ifu_tid_w2, ffu_tlu_ill_inst_m, ifu_tlu_npc_m,  // ifu_tlu_pc_m, 
86
   lsu_tlu_rsr_data_e, lsu_tlu_squash_va_oor_m, // tlu_restore_npc_w1,
87
   spu_tlu_rsrv_illgl_m, // exu_tlu_cwp0, exu_tlu_cwp1, exu_tlu_cwp2, exu_tlu_cwp3, 
88
   //
89
   // added for hypervisor support
90
   tlu_hpstate_priv, tlu_htstate_rw_d, tlu_htstate_rw_g, tlu_cwp_no_change_m,
91
   tlu_hscpd_dacc_excpt_m, tlu_htickcmp_rw_e, tlu_gl_rw_m, // tlu_gl_rw_g, 
92
   tlu_hpstate_enb, tlu_cpu_mondo_cmp, tlu_dev_mondo_cmp,
93
   tlu_resum_err_cmp, tlu_hintp, tlu_hpstate_tlz, tlu_qtail_dacc_excpt_m,
94
   pib_priv_act_trap_m, rclk, arst_l, grst_l, si, se, rst_tri_en, ctu_sscan_tid
95
   );
96
 
97
/*AUTOINPUT*/
98
// Beginning of automatic inputs (from unused autoinst inputs)
99
// End of automatics
100 113 albert.wat
input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d;      // addr of sr(st/pr)
101 95 fafa1971
input       ifu_tlu_rsr_inst_d;    // valid rd sr(st/pr)
102
// input       ifu_tlu_wsr_inst_d;    // valid wr sr(st/pr)
103
input       lsu_tlu_wsr_inst_e;    // valid wr sr(st/pr)
104
input           tlu_wsr_data_b63_w;    // b63 of wsr data
105
// input        tlu_wsr_data_b16_w;    // b16 of wsr data
106
input [3:0] tlu_wsr_data_w;    // pr/st data to irf.
107
input [8:0]      lsu_tlu_ttype_m2;       // trap type in m2.
108
input           lsu_tlu_ttype_vld_m2;   // trap is signaled.
109
// added asynchronize trap to handle correctable dmmu parity errors
110
input       lsu_tlu_defr_trp_taken_g; // lsu asynchronous trap valid
111
input       lsu_tlu_async_ttype_vld_g; // lsu asynchronous trap valid
112
input [6:0] lsu_tlu_async_ttype_g;  // lsu asynchronous trap type 
113
input [1:0] lsu_tlu_async_tid_g; // asynchronous trap - thread
114
// Removed unused bits 
115
// input        [1:0]   lsu_tlu_ttype_tid_m2;   // trapping thread
116
input           ifu_tlu_done_inst_d;    // done is valid
117
input           ifu_tlu_retry_inst_d;  // retry is valid
118
 
119
input [8:0]      ifu_tlu_ttype_m;        // trap type in m2.
120
input           ifu_tlu_ttype_vld_m;    // trap is signaled.
121
input           ifu_tlu_trap_m;     // trap is signaled.
122
// modified for timing
123
input       ifu_tlu_flush_fd_w;     // instruction flush signal 
124
// input                ifu_tlu_flush_m;            // instruction flush signal 
125
input           lsu_tlu_early_flush_w;  // early flush with tlb from LSU 
126
 
127
input [8:0]      exu_tlu_ttype_m;        // exu src ttype
128
input           exu_tlu_ttype_vld_m;    // exu src ttype vld
129
input           exu_tlu_ue_trap_m;      // exu ue ecc trap indicator 
130
//
131
// added for timing
132
/*
133
input [2:0]  exu_tlu_cwp0;  // cwp - thread0
134
input [2:0]  exu_tlu_cwp1;  // cwp - thread1
135
input [2:0]  exu_tlu_cwp2;  // cwp - thread2
136
input [2:0]  exu_tlu_cwp3;  // cwp - thread3
137
*/
138
//
139
input           exu_tlu_spill;          // spill trap
140
input [1:0]      exu_tlu_spill_tid;      // spill trap - thrid
141
input       exu_tlu_spill_other;    // From exu of sparc_exu.v
142
input [2:0] exu_tlu_spill_wtype;    // From exu of sparc_exu.v
143
input           exu_tlu_va_oor_m;       // ??? - to be used in sfsr
144
input           exu_tlu_va_oor_jl_ret_m; // ??? - to be used in sfsr
145
input           ifu_tlu_sir_inst_m;     // sir instruction executed
146
 
147
input       ifu_tlu_inst_vld_m;    // inst in w-stage of pipe.
148
input       ifu_tlu_pc_oor_e;    // inst in w-stage of pipe.
149
input [1:0] ifu_tlu_thrid_d;     // Thread id.
150
// input       lsu_tlu_dmmu_miss_g;   // ld/st misses in dtlb.
151
//
152
// modified the stage for timing 
153
//input     ifu_tlu_immu_miss_e;   // i-side page fault
154
input       ifu_tlu_immu_miss_m;   // i-side page fault
155
 
156
input       exu_tlu_cwp_cmplt;
157
input       exu_tlu_cwp_retry;
158
input [1:0] exu_tlu_cwp_cmplt_tid;
159
input       tlu_cwp_no_change_m;
160
// input       exu_tlu_cwp_fastcmplt_w;
161
// input moved to tlu_misctl
162
// input [2:0]  tsa_rdata_cwp;
163
// input [`TSA_TTYPE_WIDTH-1:0] tsa_rdata_ttype;
164
// input [7:0]  tsa_rdata_ccr;
165
// input [7:0]  tsa_rdata_asi;
166
 
167
input           ifu_tlu_rstint_m;       // reset interrupt
168
input           ifu_tlu_hwint_m;        // hw interrupt
169
input           ifu_tlu_swint_m;        // sw interrupt
170
input [5:0]      int_tlu_rstid_m;        // reset type
171 113 albert.wat
input [`TLU_THRD_NUM-1:0] tlu_int_pstate_ie;      // interrupt enable
172
input [`TLU_THRD_NUM-1:0] tlu_int_redmode;        // redmode
173 95 fafa1971
// input  [`TLU_THRD_NUM-1:0]   const_cpuid;
174
 
175 113 albert.wat
input [`TLU_THRD_NUM-1:0] tlu_sftint_id;
176
input [`TLU_THRD_NUM-1:0] pich_wrap_flg;
177
input [`TLU_THRD_NUM-1:0] pich_onebelow_flg;
178
input [`TLU_THRD_NUM-1:0] pich_twobelow_flg;
179
input [`TLU_THRD_NUM-1:0] pib_picl_wrap;
180 95 fafa1971
// modified for bug 5436: Niagara 2.0
181 113 albert.wat
input [`TLU_THRD_NUM-1:0] tlu_pcr_ut;
182
input [`TLU_THRD_NUM-1:0] tlu_pcr_st;
183 95 fafa1971
// input tlu_pic_wrap_e, tlu_pcr_ut_e, tlu_pcr_st_e;
184
input tlu_pic_wrap_e;
185
 
186
// input                tlu_tick_match; // match between tick and tick-cmp 
187
// input                tlu_stick_match;        // match between tick and stick-cmp 
188
// input  [`TLU_THRD_NUM-1:0] pib_pic_wrap; // overflow for the pic registers - lvl15 int 
189
// modified for timing support
190
// input  [`TLU_THRD_NUM-1:0] pib_priv_act_trap; // access priv violation of the pics 
191 113 albert.wat
input  [`TLU_THRD_NUM-1:0] pib_priv_act_trap_m; // access priv violation of the pics 
192 95 fafa1971
 
193
input           lsu_tlu_misalign_addr_ldst_atm_m;// misaligned addr - ld,st,atomic 
194
input           exu_tlu_misalign_addr_jmpl_rtn_m;// misaligned addr - jmpl or return addr
195
// input                lsu_tlu_priv_violtn_g;          // privileged violation trap
196
input           lsu_tlu_priv_action_g;          // privileged action trap
197
input           lsu_tlu_wtchpt_trp_g;           // watchpt trap has occurred.
198
 
199
input           ifu_tlu_priv_violtn_m;
200
input           ifu_lsu_memref_d;
201
input [3:0] tlu_pstate_priv;
202
input [3:0] tlu_pstate_am;
203
input [3:0]      tlu_isfsr_flt_vld;
204
input           ffu_tlu_trap_ieee754;
205
input           ffu_tlu_trap_other;
206
input           ffu_tlu_trap_ue;
207
input           ffu_tlu_ill_inst_m; // illegal instruction trap from ffu                
208
input [1:0]      ffu_ifu_tid_w2;
209
input [7:0]      lsu_tlu_rsr_data_e;
210
input       lsu_tlu_squash_va_oor_m;  // squash va_oor for mem-op.
211
input       spu_tlu_rsrv_illgl_m;    // illegal instruction trap from spu 
212
input       tlu_htstate_rw_d;
213
input       tlu_htstate_rw_g;
214
input       tlu_htickcmp_rw_e;
215
// input       tlu_gl_rw_g;
216
input       tlu_gl_rw_m;
217 113 albert.wat
input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;
218
input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb;
219
input [`TLU_THRD_NUM-1:0] tlu_hpstate_tlz;
220
input [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_cmp;
221
input [`TLU_THRD_NUM-1:0] tlu_dev_mondo_cmp;
222
input [`TLU_THRD_NUM-1:0] tlu_resum_err_cmp;
223
input [`TLU_THRD_NUM-1:0] tlu_hintp;
224 95 fafa1971
// input [48:0] ifu_tlu_pc_m;
225
input [48:0] ifu_tlu_npc_m;
226
// input [33:0] tlu_partial_trap_pc_w1;
227
// modified for bug 3017
228
// logic moved to tlu_misctl
229
input tlu_hscpd_dacc_excpt_m;
230
input tlu_qtail_dacc_excpt_m;
231
// added for timing
232
input [4:0] tlu_hyperv_rdpr_sel;
233
input [1:0]      tlu_tckctr_in;
234
input           rclk; // clock
235
// sscan tid
236 113 albert.wat
input [`TLU_THRD_NUM-1:0] ctu_sscan_tid;
237 95 fafa1971
//
238
// modified to abide to the niagara reset methodology
239
input           grst_l;                         // global reset - active log
240
input           arst_l;                         // global reset - active log
241
input           rst_tri_en;                     // global reset - active log
242
input           si;                                 // global scan-in 
243
input           se;                                 // global scan-out 
244
 
245
/*autooutput*/
246
// beginning of automatic outputs (from unused autoinst outputs)
247
// end of automatics
248
output           tlu_ifu_trappc_vld_w1; // trap pc or pc on retry.
249
output           tlu_ifu_trapnpc_vld_w1;// trap pc or pc on retry.
250
output [1:0] tlu_ifu_trap_tid_w1;        // thread id.
251
output       tlu_trap_hpstate_enb;
252
output       tlu_restore_pc_sel_w1;
253 113 albert.wat
output [`TLU_THRD_NUM-1:0] pib_pich_wrap;
254 95 fafa1971
output tlu_tcc_inst_w;
255
 
256
output [2:0] tsa_wr_tpl;         // trap level for wr.
257
output [1:0] tsa_rd_tid;         // thread id for wr.
258
output [2:0] tsa_rd_tpl;         // trap level for rd.
259
output [1:0] tsa_wr_tid;         // thread id for rd.
260
output [1:0] tsa_wr_vld;         // write pointer vld
261
// modified for timing
262
output           tsa_rd_vld_e;          // read pointer
263
output           tsa_rd_en;                 // read pointer
264
output [3:0] tlu_lsu_tl_zero;    // trap level is zero.
265
// output                tlu_ifu_flush_pipe_w;  // exception related flush
266
// output                tlu_flush_pipe_w;      // exception related flush - local copy
267
// added for timing 
268
// output                tlu_flush_all_w2;      // exception related flush - local copy
269
// output                tlu_flush_all_w;       // exception related flush - local copy
270
output           tlu_local_flush_w;     // exception related flush - local copy
271
output           tlu_early_flush_pipe_w;        // exception related flush - local copy
272
output           tlu_early_flush_pipe2_w;       // exception related flush - local copy
273
output           tlu_exu_early_flush_pipe_w;    // exception related flush - to exu
274
output           tlu_full_flush_pipe_w2;            // exception related flush - to exu
275
// output  [2:0]   tlu_exu_agp;            // alternate global pointer
276
// output          tlu_exu_agp_swap;       // switch globals
277
// modified due to timing
278
// output [1:0] tlu_agp_tid_g;        // thread that agp refers to
279
output [1:0] tlu_agp_tid_w2;        // thread that agp refers to
280
output [1:0] tlu_exu_agp_tid;        // thread that agp refers to
281
output           tsa_pc_en;             // enable write of pc in tsa.
282
output       tsa_npc_en;                // enable write of npc in tsa.
283
output       tsa_tstate_en;             // enable write of tstate in tsa.
284
output       tsa_htstate_en;    // enable write of htstate in tsa.
285
output       tsa_ttype_en;              // enable write of ttype in tsa.
286
// modified due to timing
287
// output       tlu_tl_gt_0_g;     // trp lvl gt then 0
288
output       tlu_tl_gt_0_w2;     // trp lvl gt then 0
289
// modified for timing
290
output [2:0] tlu_true_pc_sel_w;
291
// output       tlu_retry_inst_m;  // valid retry inst
292
// output       tlu_done_inst_m;   // valid done inst
293
// output       tlu_dnrtry_inst_m_l; // valid done/retry inst - g
294
output       tlu_tick_en_l;     // tick reg write enable
295 113 albert.wat
output [`TLU_THRD_NUM-1:0]  tlu_tickcmp_en_l;  // tick compare reg write enable
296
output [`TLU_THRD_NUM-1:0]  tlu_stickcmp_en_l; // stick compare reg write enable
297
output [`TLU_THRD_NUM-1:0]  tlu_htickcmp_en_l; // update htickcmp register 
298
output [`TLU_THRD_NUM-1:0]  tlu_tba_en_l;      // tba reg write enable
299
output [`TLU_THRD_NUM-1:0]  tlu_thrd_wsel_w2;   // thread requiring tsa write.
300
output [`TLU_THRD_NUM-1:0]  tlu_thread_wsel_g; // thread for instruction fetched 
301
output [`TSA_TTYPE_WIDTH-1:0] tlu_final_ttype_w2;  // selected ttype - w2
302 95 fafa1971
// output   tlu_async_trap_taken_g; // async trap taken
303 113 albert.wat
output [`TLU_THRD_NUM-1:0]  tlu_thread_inst_vld_g; // valid inst for a thread
304 95 fafa1971
// output [`TLU_THRD_NUM-1:0]  tlu_thread_inst_vld_w2; // valid inst for a thread
305
// output [`TLU_THRD_NUM-1:0]  tlu_update_pc_l_m; // update pc or npc for a thread
306 113 albert.wat
output [`TLU_THRD_NUM-1:0]  tlu_update_pc_l_w; // update pc or npc for a thread
307 95 fafa1971
// output [`TLU_THRD_NUM-1:0]  tlu_thrd_rsel_g; // thread requiring tsa read
308
// modified for bug 1767
309
// output               tlu_select_tle; // tle/cle value on trap 
310
// output [1:0]   tlu_select_mmodel;    // mem. model on trap
311
output          tlu_select_redmode;     // redmode setting on trap
312
// Modified for bug 1575
313
//
314
// output   [2:0]  tlu_pstate_din_sel;    // sel source of tsa wdata
315
output [1:0] tlu_pstate_din_sel0;    // sel source of tsa wdata
316
output [1:0] tlu_pstate_din_sel1;    // sel source of tsa wdata
317
output [1:0] tlu_pstate_din_sel2;    // sel source of tsa wdata
318
output [1:0] tlu_pstate_din_sel3;    // sel source of tsa wdata
319
//
320
// modified due to timing
321
// output [3:0] tlu_update_pstate_l_g; // pstate write enable
322
output [3:0] tlu_update_pstate_l_w2; // pstate write enable
323
output [2:0] tlu_trp_lvl;    // trp lvl - mx'ed
324
output [3:0] tlu_pil;              // pil - mx'ed
325
// output       tlu_wsr_inst_g; // write state inst
326
// 
327
// added for timing
328
output       tlu_wsr_inst_nq_g; // write state inst
329
// output       tlu_wr_tsa_inst_g; // write state inst
330
output       tlu_wr_tsa_inst_w2; // write state inst
331
output       tlu_exu_priv_trap_m; // local traps send to exu 
332
output       tlu_lsu_priv_trap_m; // local traps send to lsu 
333
// output       tlu_lsu_priv_trap_w; // local traps send to lsu 
334
// experiment
335
output       tlu_pic_cnt_en_m; // local traps send to exu 
336
// output       tlu_exu_pic_onebelow_m; // local traps send to exu 
337
// output       tlu_exu_pic_twobelow_m; // local traps send to exu 
338
output       tlu_exu_cwp_retry_m;
339
output       tlu_exu_cwpccr_update_m;
340
// output moved to tlu_misctl
341
// output [2:0] tlu_exu_cwp_m;
342
// output [7:0] tlu_exu_ccr_m;
343
// output [7:0] tlu_lsu_asi_m;          // asi from stack
344
// added for bug3499
345 113 albert.wat
output [`TLU_THRD_NUM-1:0] tlu_trap_cwp_en;
346 95 fafa1971
 
347
output       tlu_lsu_asi_update_m; // update asi
348
output [1:0] tlu_lsu_tid_m;              // thread for asi update
349
 
350
// output        tlu_assist_boot_rst_g; // use rstvaddr all zeroes
351
// modified due to timing
352
// output                tlu_self_boot_rst_g;   // use rstvaddr all ones
353
// output                tlu_select_tba_g;      // use tba
354
// output                tlu_select_htba_g;     // use htba
355
// modified for one-hot mux problem
356
// output                tlu_self_boot_rst_w2;  // use rstvaddr all ones
357
// output                tlu_select_htba_w2;    // use htba
358
output [2:0] tlu_pc_mxsel_w2;
359
output           tlu_select_tba_w2;     // use tba
360
output           tdp_select_tba_w2;     // use tba
361
//
362
output           tlu_set_sftint_l_g;    // set sftint
363
output           tlu_clr_sftint_l_g;    // clr sftint
364
output           tlu_wr_sftint_l_g;     // wr to sftin (asr 16)
365 113 albert.wat
output [`TLU_THRD_NUM-1:0] tlu_sftint_en_l_g; // wr en sftint regs.
366
output [`TLU_THRD_NUM-1:0] tlu_sftint_mx_sel; // mux sel sftint regs.
367 95 fafa1971
//
368
// removed due to sftint recode
369
// output       [3:0]   tlu_sftint_lvl14_int;   // level 14 sft interrupt
370
 
371
output [3:0] tlu_sftint_penc_sel;        // select appr. thread for pr. encd.
372
output [3:0] tlu_sftint_vld;     // a sftint is valid for a thread       
373
output [1:0] tlu_int_tid_m;              // thread id
374
output [1:0] tlu_incr_tick;         // increment tick reg
375
output [3:0] tlu_tickcmp_sel;       // select src for tickcmp
376
 
377
output [3:0]  immu_sfsr_trp_wr;
378
output tlu_itag_acc_sel_g;
379
 
380
output [23:0] tlu_isfsr_din_g;
381
//
382
// removed due to sftint code cleanup
383
output           tlu_tick_npt;          // npt bit of tick
384
output [3:0] tlu_thrd_rsel_e;    // read select for threaded regs
385
 
386
output           tlu_inst_vld_nq_m;     // not qualified inst vld
387
 
388
output [3:0] tlu_lsu_pstate_am;  // ship to lsu
389
 
390
output [2:0] tlu_rdpr_mx1_sel;
391
output [2:0] tlu_rdpr_mx2_sel;
392
output [1:0] tlu_rdpr_mx3_sel;
393
output [1:0] tlu_rdpr_mx4_sel;
394
output [2:0] tlu_rdpr_mx5_sel;
395
output [2:0] tlu_rdpr_mx6_sel;
396
output [3:0] tlu_rdpr_mx7_sel;
397
//
398 113 albert.wat
output [`TSA_TTYPE_WIDTH-1:0] tlu_final_offset_w1;
399 95 fafa1971
// output   [3:0]   tlu_lsu_redmode;            // redmode
400
// output [3:0] tlu_lsu_redmode_rst;
401
// output [`TLU_THRD_NUM-1:0] tlu_lsu_async_ack_w2;
402
output [3:0] tlu_lsu_redmode_rst_d1;
403
output [7:0] lsu_tlu_rsr_data_mod_e;
404
output       tlu_addr_msk_g;        // address masking active for thread in pipe.
405
//
406
// added for hypervisor support
407
// modified for timing
408
// output tlu_thrd0_traps, tlu_thrd1_traps;
409
// output tlu_thrd2_traps, tlu_thrd3_traps;
410 113 albert.wat
output [`TLU_THRD_NUM-1:0] tlu_thrd_traps_w2;
411 95 fafa1971
output tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g;
412
output tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g;
413
// output tlu_ibrkpt_trap_g; 
414
output tlu_ibrkpt_trap_w2;
415
output tlu_tick_ctl_din;
416 113 albert.wat
output [`TLU_THRD_NUM-1:0] tlu_por_rstint_g;
417
output [`TLU_THRD_NUM-1:0] tlu_hintp_vld;  // From tcl of tlu_tcl.v
418
output [`TLU_THRD_NUM-1:0] tlu_rerr_vld;  // From tcl of tlu_tcl.v
419 95 fafa1971
// modified for bug 3017
420
// moved to tlu_misctl
421
output [48:0] ifu_npc_w; //ifu_pc_w, 
422
// 
423
// shadow scan data from tcl tl and ttype
424 113 albert.wat
output [`TCL_SSCAN_WIDTH-1:0] tlu_sscan_tcl_data;
425 95 fafa1971
 
426
//
427
// added to abide to the niagara reset methodology
428
output tlu_rst;     // local unit reset - active high
429
// output tlu_rst_l;    // local unit reset - active low
430
output so;                      // global scan-out 
431
 
432
/*AUTOWIRE*/
433
// Beginning of automatic wires (for undeclared instantiated-module outputs)
434
// End of automatics
435
 
436
// this signal were added to abide to the niagara reset methodology
437
wire local_rst;
438
wire local_rst_l;
439
wire tlu_rst_l; // local unit reset - active low
440
 
441
wire [1:0]  tlu_exu_tid_m;
442
wire [3:0]       pstate_rmode;
443
 
444
// wire select_tba_g;   // use tba
445
wire local_select_tba_w2;       // use tba
446
wire [1:0] select_tba_element_w2;        // use tba
447
// wire select_htba_g;  // use htba
448
//
449
// added for early flush timing fix
450
// wire tlu_early_flush_pipe_m; 
451
wire local_early_flush_pipe_w;
452
wire local_early_flush_pipe2_w;
453
wire local_early_flush_pipe3_w;
454
wire local_early_flush_pipe4_w;
455
wire lsu_ttype_vld_w, lsu_ttype_vld_w2;
456
wire tlu_flush_all_w;
457
wire tlu_ifu_flush_pipe_w;  // exception related flush
458
wire tlu_flush_pipe_w;  // exception related flush
459
wire tlu_flush_all_w2;
460
// wire tlu_wr_tsa_inst_g; // write state inst
461
wire tlu_self_boot_rst_g, tlu_self_boot_rst_w2;
462
wire dnrtry_inst_g;
463
wire dnrtry0_inst_g, dnrtry1_inst_g;
464
wire dnrtry2_inst_g, dnrtry3_inst_g;
465 113 albert.wat
wire [`TLU_THRD_NUM-1:0] dnrtry_inst_w2;
466 95 fafa1971
wire thrd0_traps,thrd1_traps;
467
wire thrd2_traps,thrd3_traps;
468
// wire [`TLU_THRD_NUM-1:0] async_trap_ack_g;
469
// wire [`TLU_THRD_NUM-1:0] async_trap_ack_w2;
470
wire [2:0]       trp_lvl0,trp_lvl0_new;
471
wire [2:0]       trp_lvl1,trp_lvl1_new;
472
wire [2:0]       trp_lvl2,trp_lvl2_new;
473
wire [2:0]       trp_lvl3,trp_lvl3_new;
474
wire tl0_en, tl0_gt_0;
475
wire tl1_en, tl1_gt_0;
476
wire tl2_en, tl2_gt_0;
477
wire tl3_en, tl3_gt_0;
478
wire [1:0] agp_tid_g, agp_tid_w2, agp_tid_w3; // thread that agp refers to
479
// wire tlu_pic_onebelow_e, tlu_pic_twobelow_e; 
480
// experiment
481
wire pich_wrap_flg_m, tlu_pich_wrap_flg_m; // pich_wrap_flg_e, 
482
wire tlu_picl_wrap_flg_m; // pich_wrap_flg_e, 
483
// modified for bug 5436 - Niagara 2.0
484 113 albert.wat
wire [`TLU_THRD_NUM-1:0] pic_cnt_en;
485 95 fafa1971
wire pic_cnt_en_e, pic_cnt_en_m, pic_cnt_en_w, pic_cnt_en_w2;
486
// wire pic_trap_en_e; 
487
//wire pcr_ut_e, pcr_st_e; 
488
// wire [`TLU_THRD_NUM-1:0] pich_exu_wrap_e;
489
// wire pic_hpstate_enb_e, pic_hpstate_priv_e, pic_pstate_priv_e; 
490
//
491 113 albert.wat
wire [`TLU_THRD_NUM-1:0] tlz_thread_set, tlz_thread_data;
492
wire [`TLU_THRD_NUM-1:0] tlz_thread;
493
wire [`TLU_THRD_NUM-1:0] tlz_trap_m, tlz_exu_trap_m;
494
wire [`TLU_THRD_NUM-1:0] tlz_trap_nq_g, tlz_trap_g;
495
wire [`TLU_THRD_NUM-1:0] ifu_thrd_flush_w;
496
wire [`TLU_THRD_NUM-1:0] tlu_none_priv;
497 95 fafa1971
wire cpu_mondo_trap_g, dev_mondo_trap_g;
498
wire cpu_mondo_trap_w2, dev_mondo_trap_w2;
499 113 albert.wat
wire [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_trap;
500
wire [`TLU_THRD_NUM-1:0] tlu_dev_mondo_trap;
501
wire [`TLU_THRD_NUM-1:0] tlu_resum_err_trap;
502
wire [`TLU_THRD_NUM-1:0] tlu_hyper_lite;
503 95 fafa1971
wire [3:0] local_rdpr_mx6_sel;
504
wire [3:0] local_rdpr_mx5_sel;
505
wire [2:0] local_rdpr_mx4_sel;
506
wire [2:0] local_rdpr_mx3_sel;
507
wire [3:0] local_rdpr_mx2_sel;
508
wire [3:0] local_rdpr_mx1_sel;
509
wire tlu_none_priv_m;
510
wire ibrkpt_trap_m, ibrkpt_trap_g, ibrkpt_trap_w2;
511
wire va_oor_jl_ret_g;
512
wire done_inst_m_tmp;
513
wire retry_inst_m_tmp;
514
wire done_inst_w2;
515
wire retry_inst_w2;
516
wire [2:0] true_pc_sel_m, true_pc_sel_w;
517
// wire dsfsr_flt_vld_g;
518
wire done_inst_e, retry_inst_e;
519
wire done_inst_m, retry_inst_m;
520
wire exu_done_inst_m, exu_retry_inst_m;
521
// logic moved to misctl
522
// wire cwp_no_change_m;
523
// wire [2:0] cwp_xor_m, trap_old_cwp_m; 
524
wire done_inst_g, retry_inst_g;
525
wire [1:0] thrid_d, thrid_e, thrid_m, thrid_g;
526
wire [1:0] thrid_w2;
527
//
528
// added for tsa_wr_tid bug
529
//
530
// wire thread0_wtrp_g, thread1_wtrp_g, thread2_wtrp_g, thread3_wtrp_g;
531
wire thread0_wtrp_w2, thread1_wtrp_w2, thread2_wtrp_w2, thread3_wtrp_w2;
532
wire thread0_wsel_g, thread1_wsel_g, thread2_wsel_g, thread3_wsel_g;
533
wire thread0_wsel_w2, thread1_wsel_w2, thread2_wsel_w2, thread3_wsel_w2;
534
wire thread0_rsel_dec_g,thread1_rsel_dec_g;
535
wire thread2_rsel_dec_g,thread3_rsel_dec_g;
536
wire thread0_rsel_d, thread1_rsel_d, thread2_rsel_d, thread3_rsel_d;
537
wire thread0_rsel_m, thread1_rsel_m, thread2_rsel_m, thread3_rsel_m;
538
wire thread0_stg_m, thread1_stg_m, thread2_stg_m, thread3_stg_m;
539
wire thread0_stg_m_buf, thread1_stg_m_buf, thread2_stg_m_buf, thread3_stg_m_buf;
540
wire thread0_rsel_g, thread1_rsel_g, thread2_rsel_g, thread3_rsel_g;
541
wire thread0_rsel_e, thread1_rsel_e, thread2_rsel_e, thread3_rsel_e;
542
wire inst_vld_w2, inst_vld_g, inst_vld_m, inst_vld_nf_g;
543 113 albert.wat
wire [`TLU_THRD_NUM-1:0] thread_inst_vld_g;
544
wire [`TLU_THRD_NUM-1:0] thread_inst_vld_w2;
545 95 fafa1971
// wire tlu_inst_vld_m; // qualified inst vld
546
wire exu_ttype_vld_g, ifu_ttype_vld_g, exu_ue_trap_g;
547
wire [8:0]       exu_ttype_g, ifu_ttype_tmp_g, ifu_ttype_g;
548
wire [8:0]       exu_spill_ttype;
549
// added for timing fix
550
wire    spu_ill_inst_m ;      // illegal instruction trap from spu 
551
wire    spu_ill_inst_uf_g ;      // illegal instruction trap from spu 
552
wire    spu_ill_inst_g ;      // illegal instruction trap from spu 
553
wire    pib_priv_act_trap_g ;   // privilege action trap from pib 
554
wire    pib_priv_act_trap_uf_g ;   // privilege action trap from pib 
555
wire    pib_priv_act_early_trap_m ; // privilege action trap from pib 
556
wire    ffu_ill_inst_uf_g ;   // illegal instruction trap from ffu - unflushed 
557
wire    ffu_ill_inst_g ;      // illegal instruction trap from ffu 
558
wire    ffu_higher_pri_g ;      // illegal instruction trap from ffu 
559
wire    exu_higher_pri_g ;      // UE ECC trap from exu 
560
// wire    lsu_ill_inst_uf_g ;   // illegal instruction trap from lsu - unflushed
561
// wire    lsu_ill_inst_g ;      // illegal instruction trap from lsu 
562
// wire [`TLU_THRD_NUM-1:0] lsu_defr_thrd_g; 
563
wire    lsu_defr_trap_g, lsu_defr_trap_w2 ;     // deferred trap from lsu 
564
wire    local_lsu_async_ttype_vld_w; // deferred trap from lsu 
565
// wire    local_lsu_defr_trp_taken_g; // deferred trap from lsu 
566 113 albert.wat
wire [`TLU_THRD_NUM-1:0] lsu_defr_trp_taken_w2;
567 95 fafa1971
// wire    lsu_tlu_defr_trp_taken_w2 ;  // deferred trap from lsu - signled in g for w2
568
                                     // trap need to sync up with lsu_tlu_async_ttype_vld_g  
569
wire    htrap_ill_inst_m ;      // illegal instruction trap from htrap 
570
wire    htrap_ill_inst_uf_g ;   // illegal instruction trap from htrap - unflushed
571
wire    htrap_ill_inst_g ;      // illegal instruction trap from htrap 
572
 
573 113 albert.wat
wire    [`TLU_ASR_ADDR_WIDTH-1:0] sraddr;
574
wire    [`TLU_ASR_ADDR_WIDTH-1:0] sraddr2;
575 95 fafa1971
// modified due to timing
576
// wire         wsr_inst_d;
577
wire        asr_hyperp, asr_priv;
578
wire            tpc_rw_d, tnpc_rw_d, tstate_rw_d, ttype_rw_d;
579
wire            tick_rw_d, tickcmp_rw_d, tick_npriv_r_d;
580
wire        pcr_rsr_d, pic_rsr_d;
581
wire        pcr_rsr_e, pic_rsr_e;
582
wire        tlu_gl_rw_g;
583
//
584
// added for hypervisor support
585
wire maxtl_wr_sel;
586
wire [3:0] maxstl_wr_sel;
587
wire [2:0] wsr_trp_lvl0_data_w, wsr_trp_lvl1_data_w;
588
wire [2:0] wsr_trp_lvl2_data_w, wsr_trp_lvl3_data_w;
589
wire [2:0] wsr_trp_lvl0_data_w2, wsr_trp_lvl1_data_w2;
590
wire [2:0] wsr_trp_lvl2_data_w2, wsr_trp_lvl3_data_w2;
591
wire       stick_rw_d, stickcmp_rw_d, stickcmp_rw_e;
592
wire       stickcmp_rw_m, stickcmp_rw_g;
593
// wire [3:0] stickcmp_int;       // interrupt caused by stick_ticktmp 
594
// wire [3:0] stick_intclr;  // use to clear the stick_int bit
595
 
596
wire tba_rw_d, pstate_rw_d, pil_rw_d, tl_rw_d;
597
wire tsa_wr_tid_sel_g, tsa_wr_tid_sel_tim_g, tsa_wr_tid_sel_w2;
598
wire immu_miss_g;
599
wire trap_taken_g, trap_taken_w2;
600
wire [1:0] trap_tid_g;
601
// wire [1:0] tsa_wr_tid_g;
602
wire [1:0] pend_trap_tid_g, pend_trap_tid_w2;
603 113 albert.wat
wire [`TSA_TTYPE_WIDTH-1:0] final_ttype_w2;
604
wire [`TSA_TTYPE_WIDTH-1:0] tba_ttype_w1;
605
wire [`TSA_TTYPE_WIDTH-1:0] final_offset_w1;
606 95 fafa1971
wire tsa_rd_vld;
607
// modified for bug 3017
608
// logic moved to tlu_misctl
609
// wire [48:0] normal_trap_pc_w1, normal_trap_npc_w1; 
610
// wire [48:0] trap_pc_w1, trap_npc_w1; 
611
// wire [48:0] trap_pc_w2, trap_npc_w2; 
612
// wire tsa_rd_vld_e, tsa_rd_vld_m;
613 113 albert.wat
wire [`TLU_THRD_NUM-1:0] sscan_tid_sel;
614 95 fafa1971
// logic moved to tlu_misctl
615
/*
616
wire [`TLU_THRD_NUM-1:0] sscan_ttype_en;
617
wire [`TLU_THRD_NUM-1:0] sscan_tt_rd_sel;
618
wire [`TLU_THRD_NUM-1:0] sscan_tt_wr_sel;
619
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt0_data;
620
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt1_data;
621
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt2_data;
622
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt3_data;
623
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt0_din;
624
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt1_din;
625
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt2_din;
626
wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt3_din;
627
wire [`TSA_TTYPE_WIDTH-1:0] tsa_rdata_ttype_m;
628
*/
629 113 albert.wat
wire [`TCL_SSCAN_WIDTH-1:0] tcl_sscan_test_data;
630 95 fafa1971
wire tba_ttype_sel_w2;
631
wire [3:0] final_ttype_sel_g, final_ttype_sel_w2;
632
// modified due to one-hot mux bug
633
wire [1:0] final_offset_en_g, final_offset_en_w1;
634
wire [2:0] final_offset_sel_w1;
635
wire restore_pc_sel_g, restore_pc_sel_w1;
636
// removed for timing
637
// wire [`TSA_TTYPE_WIDTH-1:0] sync_ttype_g;
638
// added to support lsu dferred traps
639
wire            priority_trap_sel0, priority_trap_sel1, priority_trap_sel2;
640
wire            sync_trap_taken_g, sync_trap_taken_w2;
641
// added for timing fix
642
wire            sync_trap_taken_m ;
643
wire            ifu_ttype_early_vld_m ;
644
// wire  [3:0]   tickcmp_int;       // interrupt caused by tick_ticktmp 
645
wire       fp_trap_thrd0,fp_trap_thrd1,fp_trap_thrd2,fp_trap_thrd3;
646 113 albert.wat
wire [`TSA_TTYPE_WIDTH-1:0] ffu_async_ttype;
647 95 fafa1971
wire       spill_thrd0,spill_thrd1,spill_thrd2,spill_thrd3;
648 113 albert.wat
wire [`TLU_THRD_NUM-1:0] trap_cwp_enb;
649
wire [`TLU_THRD_NUM-1:0] lsu_async_vld_en_g, lsu_async_vld_en_w2;
650 95 fafa1971
wire       dmmu_async_thrd0, dmmu_async_thrd1;
651
wire       dmmu_async_thrd2, dmmu_async_thrd3;
652 113 albert.wat
wire [`TSA_TTYPE_WIDTH-1:0] dmmu_async_ttype;
653 95 fafa1971
wire       pend_to_thrd0_en, pend_to_thrd1_en;
654
wire       pend_to_thrd2_en, pend_to_thrd3_en;
655
wire       pend_to_thrd0_reset, pend_to_thrd1_reset;
656
wire       pend_to_thrd2_reset, pend_to_thrd3_reset;
657
wire tlu_pich_cnt_hld;
658 113 albert.wat
wire [`TLU_THRD_NUM-1:0] pich_cnt_hld_rst_g;
659
wire [`TLU_THRD_NUM-1:0] pich_cnt_hld_rst_w2;
660
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_hld;
661
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_hld_q;
662
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_hld_noqual;
663
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_hld_early;
664
wire [`TLU_THRD_NUM-1:0] pend_pich_cnt_adj;
665
wire [`TLU_THRD_NUM-1:0] cwp_en_thrd_reset;
666 95 fafa1971
// wire    pend_to_thrd0_taken, pend_to_thrd1_taken;
667
// wire    pend_to_thrd2_taken, pend_to_thrd3_taken;
668 113 albert.wat
wire [`TSA_TTYPE_WIDTH-1:0] pend_ttype0,pend_ttype1,pend_ttype2,pend_ttype3;
669 95 fafa1971
wire       pending_trap0,pending_trap1,pending_trap2,pending_trap3;
670 113 albert.wat
wire [`TSA_TTYPE_WIDTH-1:0] pending_ttype0,pending_ttype1,pending_ttype2,pending_ttype3;
671
wire [`TSA_TTYPE_WIDTH-1:0] pending_ttype, pending_ttype_w2;
672 95 fafa1971
//
673
// Added for bug 1575
674
wire agp_tid_sel;
675
// modified due to timing
676
// wire update_pstate0_g,update_pstate1_g;
677
// wire update_pstate2_g,update_pstate3_g;
678
// wire [`TLU_THRD_NUM-1:0] update_pstate_g;,
679 113 albert.wat
wire [`TLU_THRD_NUM-1:0] update_pstate_w2;
680 95 fafa1971
wire thrd0_traps_w2, thrd1_traps_w2;
681
wire thrd2_traps_w2, thrd3_traps_w2;
682
wire ifu_ttype_vld_tmp_g;
683
//
684
// added for timing, move qualification from ifu to tlu
685
wire       ifu_ttype_vld_m;
686
wire       cwp_cmplt0,cwp_cmplt1,cwp_cmplt2,cwp_cmplt3;
687
wire       cwp_cmplt_w2, cwp_cmplt_g;
688
wire       cwp_cmplt_rtry_w2, cwp_cmplt_rtry_g;
689
wire       cwp_fastcmplt_w2;
690
wire       cwp_cmplt0_pending, cwp_cmplt1_pending;
691
wire       cwp_cmplt2_pending, cwp_cmplt3_pending;
692
wire       cwp_retry0,cwp_retry1,cwp_retry2,cwp_retry3;
693
wire       pending_thrd0_event_taken, pending_thrd1_event_taken;
694
wire       pending_thrd2_event_taken, pending_thrd3_event_taken;
695
// wire    pending_thrd0_event_taken_w2, pending_thrd1_event_taken_w2;
696
// wire    pending_thrd2_event_taken_w2, pending_thrd3_event_taken_w2;
697
wire       cwp_fastcmplt_m, cwp_fastcmplt_uq_g, cwp_fastcmplt_g;
698
wire       pending_dntry0_taken, pending_dntry1_taken;
699
wire       pending_dntry2_taken, pending_dntry3_taken;
700
wire       rstint_g,hwint_g,swint_g;
701
wire [2:0] early_ttype_sel;
702
// wire [2:0] rst_ttype_sel;
703
wire [1:0] rst_ttype_sel;
704
wire rst_hwint_sel_w2;
705
// modified for timing
706
// wire [3:0] rst_hwdr_ttype_sel;
707
wire rst_hwdr_ttype_sel_w2;
708
wire       onehot_pending_ttype_sel;
709
wire       early_priv_traps_g, exu_hyper_traps_g;
710
wire       exu_pib_priv_act_trap_m;
711 113 albert.wat
wire [`TLU_THRD_NUM-1:0] pib_wrap_m;
712
wire [`TLU_THRD_NUM-1:0] pib_pich_wrap_m;
713 95 fafa1971
wire pib_wrap_trap_nq_g, pib_wrap_trap_g, pib_wrap_trap_m;
714 113 albert.wat
wire [`TLU_THRD_NUM-1:0] pib_trap_en;
715
wire [`TLU_THRD_NUM-1:0] picl_wrap_pend;
716 95 fafa1971
//
717
// added for timing; moved qualification from IFU to TLU
718
wire       ifu_rstint_m,ifu_hwint_m,ifu_swint_m; // swint_nq_g;
719
wire       sftint_penc_update;
720
wire       sftint_user_update_g, sftint_user_update_w2;
721
wire       penc_sel_user_update;
722
wire [5:0] rstid_g;
723
wire       trp_lvl0_incr_w2, trp_lvl1_incr_w2;
724
wire       trp_lvl2_incr_w2, trp_lvl3_incr_w2;
725
wire    rstint_taken,hwint_taken,swint_taken;
726
// wire swint_thrd0_taken, swint_thrd1_taken;
727
// wire swint_thrd2_taken, swint_thrd3_taken;
728
wire    sirint_taken;
729
// wire [`TLU_THRD_NUM-2:0] swint_thrd_g;
730 113 albert.wat
wire [`TLU_THRD_NUM-2:0] sftint_penc_thrd;
731 95 fafa1971
wire    por_rstint_g, xir_rstint_g;
732
wire    por_rstint0_g, por_rstint1_g;
733
wire    por_rstint2_g, por_rstint3_g;
734
wire    por_rstint_w2;
735
wire    por_rstint0_w2, por_rstint1_w2;
736
wire    por_rstint2_w2, por_rstint3_w2;
737
wire    trp_lvl0_at_maxtl,trp_lvl1_at_maxtl;
738
wire    trp_lvl2_at_maxtl,trp_lvl3_at_maxtl;
739
wire    internal_wdr;
740 113 albert.wat
wire [`TLU_THRD_NUM-1:0] internal_wdr_trap;
741 95 fafa1971
// added for hypervispor support
742 113 albert.wat
wire [`TLU_THRD_NUM-1:0] pil_cmp_en;
743
wire [`TLU_THRD_NUM-1:0] sftint_only_vld;
744
wire [`TLU_THRD_NUM-1:0] tlu_int_sftint_pend;
745
wire [`TLU_THRD_NUM-1:0] sftint_pend_wait;
746
wire [`TLU_THRD_NUM-1:0] sftint_wait_rst;
747 95 fafa1971
//
748
wire [3:0] true_pil0, true_pil1;
749
wire [3:0] true_pil2, true_pil3;
750
wire pil0_en,pil1_en,pil2_en,pil3_en;
751
wire set_sftint_d, clr_sftint_d, sftint_rg_rw_d;
752
// modified for timing and bug 5117 
753
wire [6:0] final_swint_id_w2;
754
// wire [6:0] final_swint_id;
755
// wire [6:0] final_swint0_id, final_swint1_id;
756
// wire [6:0] final_swint2_id, final_swint3_id;
757
// modified for bug 3705
758
// wire [6:0] tlz_swint_ttype;
759
// wire [6:0] hwint_swint_ttype;
760
wire [6:0] wrap_tlz_ttype;
761
wire [3:0] sftint0_id,sftint1_id,sftint2_id,sftint3_id;
762
wire [3:0] sftint_id_w2;
763
// wire [6:0] sftint_ttype; 
764
wire done_inst_g_tmp, retry_inst_g_tmp;
765
wire immu_va_oor_brnchetc_m;
766
wire pstate_am;// pstate_priv pstate_priv_g;
767
wire memref_e, memref_m;
768
wire [2:0] isfsr_ftype_sel;
769
wire [6:0] isfsr_ftype_m,isfsr_ftype_g;
770
wire       isfsr_flt_vld_m,isfsr_flt_vld_g;
771
wire       isfsr_trp_wr_m,isfsr_trp_wr_g;
772
wire       itag_acc_sel_g;
773
// wire    flsh_inst_m, flsh_inst_g;
774
// wire    pstate_cle;
775
// wire [2:0] dsfsr_asi_sel_m, dsfsr_asi_sel_g;
776
// wire [1:0] dsfsr_asi_sel_m, // dsfsr_asi_sel_g;
777
wire dmmu_va_oor_m, dmmu_va_oor_g;
778
// wire ldst_xslate_g;
779
// wire [2:0]   dsfsr_ctxt_sel;
780
// wire dsfsr_wr_op_g;
781
// wire dsfsr_flt_vld_m;
782
//
783
// logic moved to lsu_expctl due to timing
784
/*
785
wire dsfsr_ftype_zero;
786
wire [1:0]      dsfsr_ctxt_g,
787
wire [7:0]      dsfsr_asi_g;
788
// wire [6:0]   dsfsr_ftype_g, dsfsr_pe_ftype_g;
789
wire dsfsr_side_effect_g;
790
wire dsfsr_trp_wr_g;
791
*/
792
wire [1:0] isfsr_ctxt_g;
793 113 albert.wat
wire [`TLU_THRD_NUM-1:0] tick_en;
794 95 fafa1971
wire local_sync_trap_m, local_sync_trap_g;
795
wire dside_sync_trap_g, early_dside_trap_g;
796
wire true_hscpd_dacc_excpt_m;
797
wire true_qtail_dacc_excpt_m;
798
// wire lsu_higher_priority;
799
// wire dside_higher_priority;
800 113 albert.wat
wire [`TSA_TTYPE_WIDTH-1:0] local_sync_ttype_g;
801 95 fafa1971
wire local_higher_ttype_flg;
802
// wire [`TSA_TTYPE_WIDTH-1:0]  dside_sync_ttype_pre_g;
803
// wire [`TSA_TTYPE_WIDTH-1:0]  dside_sync_ttype_g;
804 113 albert.wat
wire [`TSA_TTYPE_WIDTH-1:0]      early_sync_ttype_g, early_sync_ttype_w2;
805
wire [`TSA_TTYPE_WIDTH-1:0]      adj_lsu_ttype_w2;
806
wire [`TSA_TTYPE_WIDTH-1:0]      lsu_tlu_ttype_w2;
807 95 fafa1971
// wire [`TSA_TTYPE_WIDTH-3:0]  lsu_tlu_async_ttype_w2;
808
// wire [`TSA_TTYPE_WIDTH-3:0]  rst_ttype_g; 
809 113 albert.wat
wire [`TSA_TTYPE_WIDTH-3:0]      rst_hwint_ttype_g, rst_hwint_ttype_w2;
810
wire [`TSA_TTYPE_WIDTH-3:0]      rst_ttype_w2, rst_hwdr_ttype_w2;
811
wire [`TSA_TTYPE_WIDTH-1:0]      early_ttype_g;
812 95 fafa1971
wire trp_lvl0_at_maxtlless1,trp_lvl1_at_maxtlless1;
813
wire trp_lvl2_at_maxtlless1,trp_lvl3_at_maxtlless1;
814
wire trp_lvl_at_maxtlless1;
815 113 albert.wat
wire [`TLU_THRD_NUM-1:0] tpl_maxless1;
816 95 fafa1971
wire redmode_insertion, redmode_insertion_w2;
817 113 albert.wat
wire [`TLU_THRD_NUM-1:0] tlu_lsu_redmode_rst;
818 95 fafa1971
wire trap_to_redmode;
819
wire pending_thrd_event_taken;
820
// added or modified for timing
821 113 albert.wat
wire [`TLU_THRD_NUM-2:0]  thrd_rsel_g;
822
wire [`TLU_THRD_NUM-2:0]  thrd_rsel_w2;
823 95 fafa1971
wire va_oor_inst_acc_excp_g; // qualified va_oor_jl_ret trap 
824
wire va_oor_data_acc_excp_g, va_oor_data_acc_excp_w2; // qualified exu_tlu_va_oor_m trap 
825
wire sir_inst_g;
826 113 albert.wat
wire [`TLU_THRD_NUM-1:0] pending_trap_sel;
827 95 fafa1971
//
828
// modified to support lsu_deferred traps; modified for timing
829
wire reset_sel_g, reset_sel_w2;
830
wire [2:0] reset_id_g;
831
wire tick_npt0,tick_npt1,tick_npt2,tick_npt3;
832
wire tick_ctl_din;
833
// modified due to early_flush_pipe timing fix
834
// wire tlu_tick_npt_priv_act;
835
wire    tick_npt_priv_act_g;
836
wire    tick_npt_priv_act_m;
837
wire    exu_tick_npt_priv_act_m;
838
//
839
// moved the tick_indis and stick_intdis logic to tlu_tdp
840
// wire tick_intdis0,tick_intdis1,tick_intdis2,tick_intdis3;
841
// wire stick_intdis0,stick_intdis1,stick_intdis2,stick_intdis3;
842
// wire [`TLU_THRD_NUM-1:0]     tick_intrpt;
843
// wire [`TLU_THRD_NUM-1:0]     tick_intclr;  // use to clear the tick_int bit
844
// wire wsr_tick_intclr_g;  // clear the tick_int through asr write
845
// wire wsr_tick_intset_g;  // set the tick_int through asr write 
846
// add and/or modified for hypervisor support
847
// wire [1:0] cwp_cmplt_tid_w2, cwp_cmplt_tid_g;
848
// wire wsr_illeg_globals_g;  // mutual exclusiveness of the pstate globals 
849
// wire wsr_stick_intclr_g;  // clear the stick_int through asr write
850
// wire wsr_stick_intset_g;  // set the stick_int through asr write 
851
// wire [`TLU_THRD_NUM-1:0] stick_intrpt;
852
// wire [`TLU_THRD_NUM-1:0] stick_int_en, stick_int_din;
853
// wire [`TLU_THRD_NUM-1:0] tick_int_en, tick_int_din;
854
// 
855
// wire [1:0] cwp_cmplt_tid_g;
856
wire [1:0] true_trap_tid_g;
857
wire [1:0] early_trap_tid_g;
858
wire [1:0] true_trap_tid_w2;
859
wire trp_lvl_zero;
860
wire misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g;
861
wire tt_init_en;
862 113 albert.wat
wire [`TLU_THRD_NUM-1:0] tt_init_rst;
863
wire [`TLU_THRD_NUM-1:0] tt_unwritten;
864 95 fafa1971
wire ttype_written;
865
wire ttype_unwritten_sel;
866
wire reset_d1;
867
wire thread_tl_zero;
868
// wire iside_trap;
869
wire [7:0] isfsr_asi_g;
870
wire thread_tl_zero_m,thread_tl_zero_g;
871
wire tlu_trap_to_hyper_g, tlu_trap_to_hyper_w2;
872
// wire hyper_wdr_trap;
873
wire hyper_wdr_early_trap_g, hyper_wdr_early_trap_w2, hyper_wdr_trap_w2;
874
wire tlu_priv_traps_w2;
875
wire [2:0] tlu_early_priv_element_g;
876
wire [2:0] tlu_early_priv_element_w2;
877 113 albert.wat
wire [`TLU_THRD_NUM-1:0] trp_lvl_gte_maxstl;
878
wire [`TLU_THRD_NUM-1:0] trp_lvl_at_maxstl;
879 95 fafa1971
 
880
// This section was modified to abide to the Niagara synthesis methodology
881
//
882
//reg   tpc_rw_e, tpc_rw_m, tpc_rw_g;
883
//reg   tnpc_rw_e, tnpc_rw_m, tnpc_rw_g;
884
//reg   tstate_rw_e, tstate_rw_m, tstate_rw_g, tstate_rw_w2;
885
//reg   ttype_rw_e, ttype_rw_m, ttype_rw_g, ttype_rw_w2;
886
//reg   tick_rw_e, tick_rw_m, tick_rw_g;
887
//reg   tick_npriv_r_e, tick_npriv_r_m, tick_npriv_r_g;
888
//reg   tickcmp_rw_e, tickcmp_rw_m, tickcmp_rw_g;
889
//reg   tba_rw_e, tba_rw_m, tba_rw_g;
890
//reg   pstate_rw_e, pstate_rw_m, pstate_rw_g;
891
//reg   pil_rw_e, pil_rw_m, pil_rw_g;
892
//reg   tl_rw_e, tl_rw_m, tl_rw_g;
893
//reg   wsr_inst_e, wsr_inst_m, wsr_inst_g_unflushed; 
894
//reg   set_sftint_e, clr_sftint_e, sftint_rg_rw_e;
895
//reg   set_sftint_m, clr_sftint_m, sftint_rg_rw_m;
896
//reg   set_sftint_g, clr_sftint_g, sftint_rg_rw_g;
897
//
898
wire    tpc_rw_e, tpc_rw_m, tpc_rw_g, tpc_rw_w2;
899
wire    tnpc_rw_e, tnpc_rw_m, tnpc_rw_g, tnpc_rw_w2;
900
wire    tstate_rw_e, tstate_rw_m, tstate_rw_g, tstate_rw_w2;
901
wire    ttype_rw_e, ttype_rw_m, ttype_rw_g, ttype_rw_w2;
902
wire    htstate_rw_w2;
903
wire    tick_rw_e, tick_rw_m, tick_rw_g;
904
wire    tick_npriv_r_e, tick_npriv_r_m, tick_npriv_r_g;
905
wire    tickcmp_rw_e, tickcmp_rw_m, tickcmp_rw_g;
906
wire    tba_rw_e, tba_rw_m, tba_rw_g;
907
wire    pstate_rw_e, pstate_rw_m, pstate_rw_g, pstate_rw_w2;
908
wire    pil_rw_e, pil_rw_m, pil_rw_g;
909
wire    tl_rw_e, tl_rw_m, tl_rw_g, tl_rw_w2;
910
wire    htickcmp_rw_m, htickcmp_rw_g;
911
wire    wsr_inst_e, wsr_inst_m, wsr_inst_g_unflushed;
912
wire    set_sftint_e, clr_sftint_e, sftint_rg_rw_e;
913
wire    set_sftint_m, clr_sftint_m, sftint_rg_rw_m;
914
wire    set_sftint_g, clr_sftint_g, sftint_rg_rw_g;
915
//
916
wire wsr_inst_g, wsr_inst_w2;
917
wire inst_ifu_flush_w;
918
wire inst_ifu_flush2_w;
919
wire clk;
920
 
921
//=========================================================================================
922
//=========================================================================================
923
//=========================================================================================
924
 
925
wire [3:0] tlu_pstate_priv_buf;
926
 
927
assign tlu_pstate_priv_buf[3:0] = tlu_pstate_priv[3:0];
928
 
929
//=========================================================================================
930
//=========================================================================================
931
//=========================================================================================
932
//      reset
933
//=========================================================================================
934
 
935
dffrl_async dffrl_local_rst_l(
936
    .din  (grst_l),
937
    .clk  (clk),
938
    .rst_l(arst_l),
939
    .q    (local_rst_l),
940
    .se   (se),
941 113 albert.wat
    `SIMPLY_RISC_SCANIN,
942 95 fafa1971
    .so   ()
943
);
944
 
945
assign tlu_rst = ~tlu_rst_l;
946
assign local_rst = ~tlu_rst_l;
947
assign tlu_rst_l = local_rst_l;
948
 
949
//=========================================================================================
950
//      Rename
951
//=========================================================================================
952
 
953
// assign       tlu_lsu_redmode[3:0] = tlu_int_redmode[3:0];
954
assign clk = rclk;
955
 
956
//=========================================================================================
957
//      Misc. TDP Control
958
//=========================================================================================
959
//
960
// modified for bug 5436: Niagara 2.0
961
/*
962
assign pcr_ut_e =
963
           (tlu_thrd_rsel_e[0]) ? tlu_pcr_ut[0]:
964
           (tlu_thrd_rsel_e[1]) ? tlu_pcr_ut[1]:
965
           (tlu_thrd_rsel_e[2]) ? tlu_pcr_ut[2]:
966
            tlu_pcr_ut[3];
967
 
968
assign pcr_st_e =
969
           (tlu_thrd_rsel_e[0]) ? tlu_pcr_st[0]:
970
           (tlu_thrd_rsel_e[1]) ? tlu_pcr_st[1]:
971
           (tlu_thrd_rsel_e[2]) ? tlu_pcr_st[2]:
972
            tlu_pcr_st[3];
973
*/
974
 
975
assign  tlu_thread_inst_vld_g[0] =
976
            inst_vld_g & thread0_rsel_g & ~pend_pich_cnt_hld[0];
977
assign  tlu_thread_inst_vld_g[1] =
978
            inst_vld_g & thread1_rsel_g & ~pend_pich_cnt_hld[1];
979
assign  tlu_thread_inst_vld_g[2] =
980
            inst_vld_g & thread2_rsel_g & ~pend_pich_cnt_hld[2];
981
assign  tlu_thread_inst_vld_g[3] =
982
            inst_vld_g & thread3_rsel_g & ~pend_pich_cnt_hld[3];
983
 
984
assign  thread_inst_vld_w2[0] = inst_vld_w2 & thread0_wsel_w2;
985
assign  thread_inst_vld_w2[1] = inst_vld_w2 & thread1_wsel_w2;
986
assign  thread_inst_vld_w2[2] = inst_vld_w2 & thread2_wsel_w2;
987
assign  thread_inst_vld_w2[3] = inst_vld_w2 & thread3_wsel_w2;
988
 
989
assign  thread_inst_vld_g[0] = inst_vld_g & thread0_rsel_g;
990
assign  thread_inst_vld_g[1] = inst_vld_g & thread1_rsel_g;
991
assign  thread_inst_vld_g[2] = inst_vld_g & thread2_rsel_g;
992
assign  thread_inst_vld_g[3] = inst_vld_g & thread3_rsel_g;
993
 
994
// added for timing
995
//
996
assign  tlu_trp_lvl[2:0] =
997
                thread0_rsel_e ? trp_lvl0[2:0] :
998
                        thread1_rsel_e ? trp_lvl1[2:0] :
999
                                thread2_rsel_e ? trp_lvl2[2:0] :
1000
                                        thread3_rsel_e ? trp_lvl3[2:0] : 3'bxxx;
1001
 
1002
assign  tlu_pil[3:0] =
1003
                thread0_rsel_e ? true_pil0[3:0] :
1004
                        thread1_rsel_e ? true_pil1[3:0] :
1005
                                thread2_rsel_e ? true_pil2[3:0] :
1006
                                        thread3_rsel_e ? true_pil3[3:0] : 4'bxxx;
1007
 
1008
assign tlu_tba_en_l[0] = ~(tba_rw_g & wsr_inst_g & thread0_wsel_g);
1009
assign tlu_tba_en_l[1] = ~(tba_rw_g & wsr_inst_g & thread1_wsel_g);
1010
assign tlu_tba_en_l[2] = ~(tba_rw_g & wsr_inst_g & thread2_wsel_g);
1011
assign tlu_tba_en_l[3] = ~(tba_rw_g & wsr_inst_g & thread3_wsel_g);
1012
 
1013
 
1014
assign  tlu_tick_en_l   =       ~(tick_rw_g & wsr_inst_g);
1015
// the logic equations can be made common (grape)
1016
// reset may not have to be factored in !!!
1017
assign  tick_en[0] = (tick_rw_g & wsr_inst_g & thread0_wsel_g) | local_rst | por_rstint0_g;
1018
assign  tick_en[1] = (tick_rw_g & wsr_inst_g & thread1_wsel_g) | local_rst | por_rstint1_g;
1019
assign  tick_en[2] = (tick_rw_g & wsr_inst_g & thread2_wsel_g) | local_rst | por_rstint2_g;
1020
assign  tick_en[3] = (tick_rw_g & wsr_inst_g & thread3_wsel_g) | local_rst | por_rstint3_g;
1021
 
1022
// modified for bug 4763
1023
assign  tlu_tickcmp_en_l[0] =    ~((tickcmp_rw_g & wsr_inst_g & thread0_wsel_g));
1024
assign  tlu_tickcmp_en_l[1] =   ~((tickcmp_rw_g & wsr_inst_g & thread1_wsel_g));
1025
assign  tlu_tickcmp_en_l[2] =   ~((tickcmp_rw_g & wsr_inst_g & thread2_wsel_g));
1026
assign  tlu_tickcmp_en_l[3] =   ~((tickcmp_rw_g & wsr_inst_g & thread3_wsel_g));
1027
//
1028
// modified for bug 4763
1029
assign  tlu_stickcmp_en_l[0] =   ~((stickcmp_rw_g & wsr_inst_g & thread0_wsel_g));
1030
assign  tlu_stickcmp_en_l[1] =  ~((stickcmp_rw_g & wsr_inst_g & thread1_wsel_g));
1031
assign  tlu_stickcmp_en_l[2] =  ~((stickcmp_rw_g & wsr_inst_g & thread2_wsel_g));
1032
assign  tlu_stickcmp_en_l[3] =  ~((stickcmp_rw_g & wsr_inst_g & thread3_wsel_g));
1033
//
1034
// modified for bug 4763
1035
assign  tlu_htickcmp_en_l[0] =   ~((htickcmp_rw_g & wsr_inst_g & thread0_wsel_g));
1036
assign  tlu_htickcmp_en_l[1] =  ~((htickcmp_rw_g & wsr_inst_g & thread1_wsel_g));
1037
assign  tlu_htickcmp_en_l[2] =  ~((htickcmp_rw_g & wsr_inst_g & thread2_wsel_g));
1038
assign  tlu_htickcmp_en_l[3] =  ~((htickcmp_rw_g & wsr_inst_g & thread3_wsel_g));
1039
 
1040
// modified for bug 1266 and 1264
1041 113 albert.wat
dff_s dff_stgg_va_oor_jl_ret_g (
1042 95 fafa1971
    .din (exu_tlu_va_oor_jl_ret_m),
1043
        .q   (va_oor_jl_ret_g),
1044
    .clk (clk),
1045
    .se  (se),
1046 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1047 95 fafa1971
    .so  ()
1048
);
1049
 
1050
// This may have to be changed as all lsu traps may not use mmu globals 
1051
// ffu traps may have to be factored in once round-robin selection in place.
1052
// factor in ldst related mem-address exceptions. 
1053
//
1054
// modified for bug 1264 and 1266
1055
// prioritize the exu_tlu_va_oor_jl_ret_m trap; if no higher traps are happening initiate the trap
1056
//
1057
assign va_oor_inst_acc_excp_g =
1058
      va_oor_jl_ret_g & inst_vld_g &
1059
     ~(exu_ttype_vld_g | ifu_ttype_vld_g | lsu_tlu_priv_action_g | local_sync_trap_g);
1060
//
1061
// added for bug 1316 
1062
// prioritize the exu_tlu_va_oor_jl_ret_m trap; if no higher traps are happening initiate the trap
1063
// modified for bug 3464 and bug 4873 
1064
assign va_oor_data_acc_excp_g =
1065
       (dmmu_va_oor_g & inst_vld_g) & ~(exu_ttype_vld_g | ifu_ttype_vld_g |
1066
        lsu_tlu_priv_action_g | misalign_addr_ldst_atm_g | lsu_tlu_wtchpt_trp_g);
1067
//
1068
// added for timing 
1069 113 albert.wat
dffr_s dffr_va_oor_data_acc_excp_w2 (
1070 95 fafa1971
    .din (va_oor_data_acc_excp_g),
1071
    .q   (va_oor_data_acc_excp_w2),
1072
    .rst (local_rst),
1073
    .clk (clk),
1074
    .se  (se),
1075 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1076 95 fafa1971
    .so  ()
1077
);
1078
//
1079
// exu should qualify with priv bit. Assume ttype vld is asserted.
1080 113 albert.wat
dff_s #(1) dff_stgg_sir_g (
1081 95 fafa1971
    .din (ifu_tlu_sir_inst_m),
1082
        .q   (sir_inst_g),
1083
    .clk (clk),
1084
    .se  (se),
1085 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1086 95 fafa1971
    .so  ()
1087
);
1088
 
1089
assign  pstate_rmode[3:0] = tlu_int_redmode[3:0];
1090
 
1091
wire    intrpt_taken;
1092
// recoded for bug 2644
1093
// assign       intrpt_taken = rstint_taken | hwint_taken | swint_taken;  
1094
assign  intrpt_taken =
1095
            rstint_taken | hwint_taken | sirint_taken;
1096
//
1097
// modified for bug 4906
1098
assign trp_lvl_at_maxtlless1 =
1099
           tpl_maxless1[0] | tpl_maxless1[1] | tpl_maxless1[2] | tpl_maxless1[3];
1100
assign tpl_maxless1[0] =
1101
           (trp_lvl0_at_maxtlless1 | pstate_rmode[0]) & thrd0_traps;
1102
assign tpl_maxless1[1] =
1103
           (trp_lvl1_at_maxtlless1 | pstate_rmode[1]) & thrd1_traps;
1104
assign tpl_maxless1[2] =
1105
           (trp_lvl2_at_maxtlless1 | pstate_rmode[2]) & thrd2_traps;
1106
assign tpl_maxless1[3] =
1107
           (trp_lvl3_at_maxtlless1 | pstate_rmode[3]) & thrd3_traps;
1108
 
1109
// thread enters redstate
1110
// modified for bug 3919
1111
// assign       trap_to_redmode = trp_lvl_at_maxtlless1 & ~intrpt_taken; 
1112
assign  trap_to_redmode = trp_lvl_at_maxtlless1 & ~(rstint_taken | sirint_taken);
1113
 
1114
assign  tlu_lsu_redmode_rst[0]   =
1115
                ((rstint_taken |  sirint_taken) & thread0_rsel_g) |
1116
              tpl_maxless1[0] | internal_wdr_trap[0] | local_rst ;
1117
assign  tlu_lsu_redmode_rst[1]  =
1118
                ((rstint_taken |  sirint_taken) & thread1_rsel_g) |
1119
              tpl_maxless1[1] | internal_wdr_trap[1] | local_rst ;
1120
assign  tlu_lsu_redmode_rst[2]  =
1121
                ((rstint_taken |  sirint_taken) & thread2_rsel_g) |
1122
              tpl_maxless1[2] | internal_wdr_trap[2] | local_rst ;
1123
assign  tlu_lsu_redmode_rst[3]  =
1124
                ((rstint_taken |  sirint_taken) & thread3_rsel_g) |
1125
              tpl_maxless1[3] | internal_wdr_trap[3] | local_rst ;
1126
 
1127 113 albert.wat
dff_s #(`TLU_THRD_NUM) dff_tlu_lsu_redmode_rst_d1 (
1128
    .din (tlu_lsu_redmode_rst[`TLU_THRD_NUM-1:0]),
1129
        .q   (tlu_lsu_redmode_rst_d1[`TLU_THRD_NUM-1:0]),
1130 95 fafa1971
    .clk (clk),
1131
    .se  (se),
1132 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1133 95 fafa1971
    .so  ()
1134
);
1135
 
1136
assign  redmode_insertion =
1137
        local_rst | rstint_taken | trap_to_redmode | internal_wdr | sirint_taken;
1138
//      sir_inst_g;                                     // sigm inst in priv mode
1139
//
1140
// added for timing
1141 113 albert.wat
dff_s dff_redmode_insertion_w2 (
1142 95 fafa1971
    .din (redmode_insertion),
1143
        .q   (redmode_insertion_w2),
1144
    .clk (clk),
1145
    .se  (se),
1146 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1147 95 fafa1971
    .so  ()
1148
);
1149
 
1150
assign  tlu_select_redmode =  redmode_insertion_w2;
1151
 
1152
// added for bug 2808
1153
assign ibrkpt_trap_m =
1154
           (ifu_tlu_ttype_m[8:0]== 9'h076) & ifu_tlu_ttype_vld_m;
1155
 
1156 113 albert.wat
dffr_s dffr_ibrkpt_trap_g (
1157 95 fafa1971
   .din (ibrkpt_trap_m),
1158
   .q   (ibrkpt_trap_g),
1159
   .rst (local_rst),
1160
   .clk (clk),
1161
   .se  (se),
1162 113 albert.wat
   `SIMPLY_RISC_SCANIN,
1163 95 fafa1971
   .so  ()
1164
);
1165
 
1166 113 albert.wat
dffr_s dffr_ibrkpt_trap_w2 (
1167 95 fafa1971
   .din (ibrkpt_trap_g),
1168
   .q   (ibrkpt_trap_w2),
1169
   .rst (local_rst),
1170
   .clk (clk),
1171
   .se  (se),
1172 113 albert.wat
   `SIMPLY_RISC_SCANIN,
1173 95 fafa1971
   .so  ()
1174
);
1175
 
1176
// assign tlu_ibrkpt_trap_g = ibrkpt_trap_g;
1177
assign tlu_ibrkpt_trap_w2 = ibrkpt_trap_w2;
1178
 
1179
// modified for bug 1575
1180
// assign       tlu_pstate_din_sel[2]   = ~(tlu_pstate_din_sel[0] | tlu_pstate_din_sel[1]);
1181
 
1182
// the selection pstate by thread
1183
// modified for the hypervisory support
1184
 
1185
assign  tlu_pstate_din_sel0[0]   = dnrtry_inst_w2[0] & ~rst_tri_en;
1186
assign  tlu_pstate_din_sel0[1]  = (pstate_rw_w2 & wsr_inst_w2) & ~rst_tri_en &
1187
                                 ~tlu_pstate_din_sel0[0] & thread0_wsel_w2;
1188
 
1189
assign  tlu_pstate_din_sel1[0]   = dnrtry_inst_w2[1] & ~rst_tri_en;
1190
assign  tlu_pstate_din_sel1[1]  = (pstate_rw_w2 & wsr_inst_w2) & ~rst_tri_en &
1191
                                 ~tlu_pstate_din_sel1[0] & thread1_wsel_w2;
1192
 
1193
assign  tlu_pstate_din_sel2[0]   = dnrtry_inst_w2[2] & ~rst_tri_en;
1194
assign  tlu_pstate_din_sel2[1]  = (pstate_rw_w2 & wsr_inst_w2) & ~rst_tri_en &
1195
                                 ~tlu_pstate_din_sel2[0] & thread2_wsel_w2;
1196
 
1197
assign  tlu_pstate_din_sel3[0]   = dnrtry_inst_w2[3] & ~rst_tri_en;
1198
assign  tlu_pstate_din_sel3[1]  = (pstate_rw_w2 & wsr_inst_w2) & ~rst_tri_en &
1199
                                 ~tlu_pstate_din_sel3[0] & thread3_wsel_w2;
1200
 
1201
assign  restore_pc_sel_g = (dnrtry_inst_g & cwp_fastcmplt_g) | cwp_cmplt_g;
1202
//
1203 113 albert.wat
dffr_s dffr_restore_pc_sel_w1 (
1204 95 fafa1971
   .din (restore_pc_sel_g),
1205
   .q   (restore_pc_sel_w1),
1206
   .rst (local_rst),
1207
   .clk (clk),
1208
   .se  (se),
1209 113 albert.wat
   `SIMPLY_RISC_SCANIN,
1210 95 fafa1971
   .so  ()
1211
);
1212
 
1213
assign  tlu_restore_pc_sel_w1 = restore_pc_sel_w1;
1214
//
1215
// modified for the hypervisor support and timing
1216
 
1217
assign  update_pstate_w2[0] =
1218
                thrd0_traps_w2 | dnrtry_inst_w2[0] |
1219
                ((pstate_rw_w2 & wsr_inst_w2) & thread0_wsel_w2);
1220
assign  update_pstate_w2[1] =
1221
                thrd1_traps_w2 | dnrtry_inst_w2[1] |
1222
                ((pstate_rw_w2 & wsr_inst_w2) & thread1_wsel_w2);
1223
assign  update_pstate_w2[2] =
1224
                thrd2_traps_w2 | dnrtry_inst_w2[2] |
1225
                ((pstate_rw_w2 & wsr_inst_w2) & thread2_wsel_w2);
1226
assign  update_pstate_w2[3] =
1227
                thrd3_traps_w2 | dnrtry_inst_w2[3] |
1228
                ((pstate_rw_w2 & wsr_inst_w2) & thread3_wsel_w2);
1229
 
1230
// recoded for timing
1231
// modified for bug 4284
1232
assign  tlu_update_pc_l_w[0] =   ~(inst_vld_g & thread0_rsel_g);
1233
assign  tlu_update_pc_l_w[1] =  ~(inst_vld_g & thread1_rsel_g);
1234
assign  tlu_update_pc_l_w[2] =  ~(inst_vld_g & thread2_rsel_g);
1235
assign  tlu_update_pc_l_w[3] =  ~(inst_vld_g & thread3_rsel_g);
1236
//
1237
// modified for timing 
1238 113 albert.wat
assign tlu_thrd_wsel_w2[`TLU_THRD_NUM-1:0] =
1239 95 fafa1971
           {thread3_wtrp_w2, thread2_wtrp_w2, thread1_wtrp_w2, thread0_wtrp_w2};
1240
 
1241
//wire  pending_thrd_event_taken_w2;
1242
assign  pending_thrd_event_taken =
1243
        pending_thrd0_event_taken | pending_thrd1_event_taken |
1244
        pending_thrd2_event_taken | pending_thrd3_event_taken;
1245
//
1246
// modified due to timing
1247
assign  tlu_tl_gt_0_w2 =
1248
                thrd_rsel_w2[0] ? tl0_gt_0 :
1249
                        (thrd_rsel_w2[1] ? tl1_gt_0 :
1250
                                (thrd_rsel_w2[2] ? tl2_gt_0 : tl3_gt_0));
1251
 
1252
assign  thrd_rsel_g[0] =         (thread0_rsel_g & ~pending_thrd_event_taken) | pending_thrd0_event_taken;
1253
assign  thrd_rsel_g[1] =        (thread1_rsel_g & ~pending_thrd_event_taken) | pending_thrd1_event_taken;
1254
assign  thrd_rsel_g[2] =        (thread2_rsel_g & ~pending_thrd_event_taken) | pending_thrd2_event_taken;
1255
 
1256 113 albert.wat
dff_s #(`TLU_THRD_NUM-1) dff_thrd_rsel_w2 (
1257
    .din (thrd_rsel_g[`TLU_THRD_NUM-2:0]),
1258
    .q   (thrd_rsel_w2[`TLU_THRD_NUM-2:0]),
1259 95 fafa1971
    .clk (clk),
1260
    .se  (se),
1261 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1262 95 fafa1971
    .so  ()
1263
);
1264
//
1265
// modified for the tsa_wdata bug (tlu_tdp)
1266
//
1267
// assign tlu_wr_tsa_inst_g = tsa_wr_tid_sel_g;
1268
//
1269
// added for timing
1270
assign tlu_wr_tsa_inst_w2 =
1271
           (wsr_inst_w2 & (tstate_rw_w2 | tpc_rw_w2 | tnpc_rw_w2  |
1272
            ttype_rw_w2 | htstate_rw_w2)) & ~sync_trap_taken_w2;
1273
 
1274
// assign tlu_wsr_inst_g = wsr_inst_g;
1275
// 
1276
// modified for timing
1277
/*
1278
assign tlu_update_pstate_l_g[0] = ~(update_pstate_g[0] | local_rst);
1279
assign tlu_update_pstate_l_g[1] = ~(update_pstate_g[1] | local_rst);
1280
assign tlu_update_pstate_l_g[2] = ~(update_pstate_g[2] | local_rst);
1281
assign tlu_update_pstate_l_g[3] = ~(update_pstate_g[3] | local_rst);
1282
*/
1283
assign tlu_update_pstate_l_w2[0] = ~(update_pstate_w2[0] | local_rst);
1284
assign tlu_update_pstate_l_w2[1] = ~(update_pstate_w2[1] | local_rst);
1285
assign tlu_update_pstate_l_w2[2] = ~(update_pstate_w2[2] | local_rst);
1286
assign tlu_update_pstate_l_w2[3] = ~(update_pstate_w2[3] | local_rst);
1287
 
1288
//=========================================================================================
1289
// rdpr mux selects - recoded due to timing
1290
//=========================================================================================
1291
// modified for bug 1352 - added the non-privedged term in the read select
1292
//
1293
// modified for bug 1859
1294
// assign       tlu_rdpr_mx1_sel[0] = tpc_rw_e; 
1295
// assign       tlu_rdpr_mx1_sel[1] = tnpc_rw_e;
1296
// assign       tlu_rdpr_mx1_sel[2] = tick_rw_e | tick_npriv_r_e;
1297
// assign       tlu_rdpr_mx1_sel[3] = tickcmp_rw_e;
1298
// assign       tlu_rdpr_mx2_sel[0] = tstate_rw_e; 
1299
// assign       tlu_rdpr_mx2_sel[1] = tba_rw_e;
1300
// assign       tlu_rdpr_mx2_sel[2] = sftint_rg_rw_e;
1301
// assign       tlu_rdpr_mx3_sel[0] = ttype_rw_e; 
1302
// assign       tlu_rdpr_mx3_sel[2] = tl_rw_e;
1303
// assign       tlu_rdpr_mx3_sel[3] = pil_rw_e;
1304
// assign       tlu_rdpr_mx4_sel[0] = (|tlu_rdpr_mx2_sel[`RDPR_MX2_SEL_WIDTH-1:0]) | tlu_htba_mx2_sel; 
1305
// assign       tlu_rdpr_mx4_sel[1] = (ttype_rw_e & ttype_written) | pstate_rw_e | tl_rw_e | pil_rw_e;
1306
// assign       tlu_rdpr_mx4_sel[2] =  tlu_rdpr_mx5_active;  
1307
// assign       tlu_rdpr_mx6_sel[0] = (|tlu_rdpr_mx1_sel[3:0]); 
1308
// assign       tlu_rdpr_mx6_sel[1] =  stickcmp_rw_e;  
1309
// assign       tlu_rdpr_mx6_sel[2] =  tlu_htickcmp_rw_e; 
1310
// assign       tlu_rdpr_mx7_sel[0] = |(tlu_rdpr_mx4_sel[2:0]);
1311
// assign       tlu_rdpr_mx7_sel[1] = |(tlu_rdpr_mx6_sel[2:0]); 
1312
// assign       tlu_rdpr_mx7_sel[2] = ttype_unwritten_sel;
1313
 
1314
assign  local_rdpr_mx1_sel[0] = tick_rw_e | tick_npriv_r_e;
1315
assign  local_rdpr_mx1_sel[1] = tickcmp_rw_e;
1316
assign  local_rdpr_mx1_sel[2] = stickcmp_rw_e;
1317
assign  local_rdpr_mx1_sel[3] = tlu_htickcmp_rw_e;
1318
//
1319
assign  tlu_rdpr_mx1_sel[0] = local_rdpr_mx1_sel[1] & ~rst_tri_en;
1320
assign  tlu_rdpr_mx1_sel[1] = local_rdpr_mx1_sel[2] & ~rst_tri_en;
1321
assign  tlu_rdpr_mx1_sel[2] = local_rdpr_mx1_sel[3] & ~rst_tri_en;
1322
//
1323
assign  local_rdpr_mx2_sel[0] = tlu_hyperv_rdpr_sel[0];
1324
assign  local_rdpr_mx2_sel[1] = tlu_hyperv_rdpr_sel[1];
1325
assign  local_rdpr_mx2_sel[2] = tl_rw_e;
1326
assign  local_rdpr_mx2_sel[3] = pil_rw_e;
1327
//
1328
assign  tlu_rdpr_mx2_sel[0] = local_rdpr_mx2_sel[1] & ~rst_tri_en;
1329
assign  tlu_rdpr_mx2_sel[1] = local_rdpr_mx2_sel[2] & ~rst_tri_en;
1330
assign  tlu_rdpr_mx2_sel[2] = local_rdpr_mx2_sel[3] & ~rst_tri_en;
1331
//
1332
assign  local_rdpr_mx3_sel[0] = sftint_rg_rw_e;
1333
assign  local_rdpr_mx3_sel[1] = pstate_rw_e;
1334
assign  local_rdpr_mx3_sel[2] = tlu_hyperv_rdpr_sel[2];
1335
//
1336
assign  tlu_rdpr_mx3_sel[0] = local_rdpr_mx3_sel[1] & ~rst_tri_en;
1337
assign  tlu_rdpr_mx3_sel[1] = local_rdpr_mx3_sel[2] & ~rst_tri_en;
1338
//
1339
assign  local_rdpr_mx4_sel[0] = tpc_rw_e;
1340
assign  local_rdpr_mx4_sel[1] = tnpc_rw_e;
1341
assign  local_rdpr_mx4_sel[2] = tstate_rw_e;
1342
//
1343
assign  tlu_rdpr_mx4_sel[0] = local_rdpr_mx4_sel[1] & ~rst_tri_en;
1344
assign  tlu_rdpr_mx4_sel[1] = local_rdpr_mx4_sel[2] & ~rst_tri_en;
1345
//
1346
// modified for rte failures
1347
assign  local_rdpr_mx5_sel[0] = tba_rw_e;
1348
assign  local_rdpr_mx5_sel[1] = tlu_hyperv_rdpr_sel[4] & ~rst_tri_en;
1349
assign  local_rdpr_mx5_sel[2] = (|local_rdpr_mx1_sel[3:0]) & ~rst_tri_en;
1350
assign  local_rdpr_mx5_sel[3] = (pcr_rsr_e | pic_rsr_e) & ~rst_tri_en;
1351
//
1352
assign  tlu_rdpr_mx5_sel[0] = local_rdpr_mx5_sel[1];
1353
assign  tlu_rdpr_mx5_sel[1] = local_rdpr_mx5_sel[2];
1354
assign  tlu_rdpr_mx5_sel[2] = local_rdpr_mx5_sel[3];
1355
//
1356
assign  tlu_rdpr_mx6_sel[0] = local_rdpr_mx6_sel[1];
1357
assign  tlu_rdpr_mx6_sel[1] = local_rdpr_mx6_sel[2];
1358
assign  tlu_rdpr_mx6_sel[2] = local_rdpr_mx6_sel[3];
1359
// 
1360
assign  local_rdpr_mx6_sel[0] = ttype_rw_e;
1361
assign  local_rdpr_mx6_sel[1] = tlu_hyperv_rdpr_sel[3] & ~rst_tri_en;
1362
assign  local_rdpr_mx6_sel[2] = (|local_rdpr_mx2_sel[3:0]) & ~rst_tri_en;
1363
assign  local_rdpr_mx6_sel[3] = (|local_rdpr_mx3_sel[2:0]) & ~rst_tri_en;
1364
//
1365
assign  tlu_rdpr_mx7_sel[0] = (|local_rdpr_mx4_sel[2:0]) & ~rst_tri_en;
1366
assign  tlu_rdpr_mx7_sel[1] = (|local_rdpr_mx5_sel[3:0]) & ~rst_tri_en;
1367
assign  tlu_rdpr_mx7_sel[2] = (|local_rdpr_mx6_sel[3:0]) & ~rst_tri_en;
1368
assign  tlu_rdpr_mx7_sel[3] = ~(|tlu_rdpr_mx7_sel[2:0]);
1369
 
1370
//=========================================================================================
1371
 
1372
assign  ttype_written = (thread0_rsel_e & ~tt_unwritten[0]) |
1373
                        (thread1_rsel_e & ~tt_unwritten[1]) |
1374
                        (thread2_rsel_e & ~tt_unwritten[2]) |
1375
                        (thread3_rsel_e & ~tt_unwritten[3]);
1376
 
1377
assign  ttype_unwritten_sel = ttype_rw_e & ~ttype_written;
1378
 
1379
//
1380
// constructing the mux select for rdpr 7 in tdp
1381
//
1382
 
1383
//=========================================================================================
1384
 
1385 113 albert.wat
dff_s #(2) dff_stgdntry_m (
1386 95 fafa1971
    .din ({done_inst_e,retry_inst_e}),
1387
        .q   ({done_inst_m_tmp,retry_inst_m_tmp}),
1388
    .clk (clk),
1389
    .se  (se),
1390 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1391 95 fafa1971
    .so  ()
1392
);
1393
 
1394
wire    trap_on_dnrtry_m;
1395
// priv opcode, illegal inst trap on done/retry.
1396
assign  trap_on_dnrtry_m =  ifu_ttype_vld_m ;
1397
 
1398
// qualification done with previous instruction's flush pipe 
1399
// the inst_vld may have to be sent earlier to avoid the critical path.
1400
// modified for bug 4074 and 4561
1401
assign  done_inst_m  =
1402
            done_inst_m_tmp  & ~(((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1403
            tlu_ifu_flush_pipe_w) | trap_on_dnrtry_m);
1404
/*
1405
            done_inst_m_tmp  & ~(((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1406
            tlu_ifu_flush_pipe_w) | ((thrid_w2[1:0] == tlu_exu_tid_m[1:0]) &
1407
            lsu_defr_trap_g) | trap_on_dnrtry_m);
1408
*/
1409
assign  retry_inst_m =
1410
            retry_inst_m_tmp & ~(((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1411
            tlu_ifu_flush_pipe_w) | trap_on_dnrtry_m);
1412
/*
1413
            retry_inst_m_tmp & ~(((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1414
            tlu_ifu_flush_pipe_w) | ((thrid_w2[1:0] == tlu_exu_tid_m[1:0]) &
1415
            lsu_defr_trap_g) | trap_on_dnrtry_m);
1416
*/
1417
/*
1418
// logic moved to tlu_misctl
1419
// modified/added for timing violations
1420
// moved the logic from exu to tlu due to timing violations
1421
 
1422
mux4ds #(3) mux_trap_old_cwp_m(
1423
    .in0(exu_tlu_cwp0[2:0]),
1424
    .in1(exu_tlu_cwp1[2:0]),
1425
    .in2(exu_tlu_cwp2[2:0]),
1426
    .in3(exu_tlu_cwp3[2:0]),
1427
    .sel0(thread0_rsel_m),
1428
    .sel1(thread1_rsel_m),
1429
    .sel2(thread2_rsel_m),
1430
    .sel3(thread3_rsel_m),
1431
    .dout(trap_old_cwp_m[2:0])
1432
);
1433
 
1434
assign cwp_xor_m[2:0] = trap_old_cwp_m[2:0] ^ tlu_exu_cwp_m[2:0];
1435
 
1436
assign cwp_no_change_m = ~|(cwp_xor_m[2:0]);
1437
*/
1438
assign cwp_fastcmplt_m =
1439
           tlu_exu_cwpccr_update_m & tlu_cwp_no_change_m;
1440
 
1441 113 albert.wat
dffr_s dffr_cwp_fastcmplt_uq_g (
1442 95 fafa1971
    .din (cwp_fastcmplt_m),
1443
        .q   (cwp_fastcmplt_uq_g),
1444
    .clk (clk),
1445
    .rst (local_rst),
1446
    .se  (se),
1447 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1448 95 fafa1971
    .so  ()
1449
);
1450
 
1451
// assign       tlu_exu_cwpccr_update_m = done_inst_m | retry_inst_m;
1452
assign  tlu_exu_cwpccr_update_m = exu_done_inst_m | exu_retry_inst_m;
1453
 
1454
assign exu_done_inst_m  =
1455
           done_inst_m_tmp; // & ~(ifu_tlu_ttype_vld_m & ifu_tlu_inst_vld_m); 
1456
assign exu_retry_inst_m =
1457
           retry_inst_m_tmp;// & ~(ifu_tlu_ttype_vld_m & ifu_tlu_inst_vld_m);
1458
 
1459
//
1460
// modified due timing problems 
1461
// assign       tlu_exu_cwp_retry_m = retry_inst_m; 
1462
assign  tlu_exu_cwp_retry_m = exu_retry_inst_m;
1463
 
1464
// qualify with flush ?
1465
// modified for timing and bug4658 
1466
// modified for timing and added the omitted tlz trap qualification
1467
 
1468
assign  true_pc_sel_m[0] =
1469
            retry_inst_m_tmp & ~ifu_tlu_trap_m & ifu_tlu_inst_vld_m &
1470 113 albert.wat
            ~(pib_wrap_trap_m | (|tlz_trap_m[`TLU_THRD_NUM-1:0]));
1471 95 fafa1971
assign  true_pc_sel_m[1]  =
1472
            done_inst_m_tmp  & ~ifu_tlu_trap_m & ifu_tlu_inst_vld_m &
1473 113 albert.wat
            ~(pib_wrap_trap_m | (|tlz_trap_m[`TLU_THRD_NUM-1:0])) ;
1474 95 fafa1971
 
1475
assign  true_pc_sel_m[2]  = ~(|true_pc_sel_m[1:0]);
1476
 
1477 113 albert.wat
dffr_s #(3) dff_true_pc_sel_w (
1478 95 fafa1971
    .din (true_pc_sel_m[2:0]),
1479
    .q   (true_pc_sel_w[2:0]),
1480
    .clk (clk),
1481
    .rst (local_rst),
1482
    .se  (se),
1483 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1484 95 fafa1971
    .so  ()
1485
);
1486
 
1487 113 albert.wat
dff_s #(49) dff_ifu_npc_w (
1488 95 fafa1971
    .din (ifu_tlu_npc_m[48:0]),
1489
    .q   (ifu_npc_w[48:0]),
1490
    .clk (clk),
1491
    .se  (se),
1492 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1493 95 fafa1971
    .so  ()
1494
);
1495
 
1496
assign tlu_true_pc_sel_w[2:0] = true_pc_sel_w[2:0];
1497
 
1498 113 albert.wat
dff_s #(2) dff_stgdntry_g (
1499 95 fafa1971
    .din ({done_inst_m,retry_inst_m}),
1500
        .q   ({done_inst_g_tmp,retry_inst_g_tmp}),
1501
    .clk (clk),
1502
    .se  (se),
1503 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1504 95 fafa1971
    .so  ()
1505
);
1506
 
1507
assign  done_inst_g = done_inst_g_tmp & inst_vld_g;
1508
assign  retry_inst_g = retry_inst_g_tmp & inst_vld_g;
1509
 
1510
//assign        tlu_retry_inst_g = retry_inst_g;
1511
//assign        tlu_done_inst_g  = done_inst_g;
1512
// 
1513
// threaded dnrtry_inst_g signal
1514
// modified for timing 
1515
//
1516
assign  dnrtry0_inst_g = (done_inst_g | retry_inst_g) &
1517
                        ~(inst_ifu_flush2_w | local_early_flush_pipe_w) &
1518
                          thread0_rsel_g;
1519
 
1520
assign  dnrtry1_inst_g = (done_inst_g | retry_inst_g) &
1521
                        ~(inst_ifu_flush2_w | local_early_flush_pipe_w) &
1522
                          thread1_rsel_g;
1523
 
1524
assign  dnrtry2_inst_g = (done_inst_g | retry_inst_g) &
1525
                        ~(inst_ifu_flush2_w | local_early_flush_pipe_w) &
1526
                          thread2_rsel_g;
1527
 
1528
assign  dnrtry3_inst_g = (done_inst_g | retry_inst_g) &
1529
                        ~(inst_ifu_flush2_w | local_early_flush_pipe_w) &
1530
                          thread3_rsel_g;
1531
//
1532
// added for timing
1533 113 albert.wat
dffr_s #(`TLU_THRD_NUM) dffr_dnrtry_inst_w2 (
1534 95 fafa1971
    .din ({dnrtry3_inst_g,dnrtry2_inst_g,dnrtry1_inst_g,dnrtry0_inst_g}),
1535 113 albert.wat
    .q   (dnrtry_inst_w2[`TLU_THRD_NUM-1:0]),
1536 95 fafa1971
    .rst (local_rst),
1537
    .clk (clk),
1538
    .se  (se),
1539 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1540 95 fafa1971
    .so  ()
1541
);
1542
 
1543
assign  tlu_dnrtry0_inst_g = dnrtry0_inst_g;
1544
assign  tlu_dnrtry1_inst_g = dnrtry1_inst_g;
1545
assign  tlu_dnrtry2_inst_g = dnrtry2_inst_g;
1546
assign  tlu_dnrtry3_inst_g = dnrtry3_inst_g;
1547
 
1548
// flush needed for done/retry with tl=0
1549
// modified for timing
1550
// assign       dnrtry_inst_g = (done_inst_g | retry_inst_g) & ~tlu_flush_pipe_w;
1551
// 
1552
assign  dnrtry_inst_g = (done_inst_g | retry_inst_g) &
1553
                       ~(inst_ifu_flush_w | local_early_flush_pipe_w);
1554 113 albert.wat
dff_s #(2) dff_stgdntry_e (
1555 95 fafa1971
    .din ({ifu_tlu_done_inst_d,ifu_tlu_retry_inst_d}),
1556
        .q   ({done_inst_e,retry_inst_e}),
1557
    .clk (clk),
1558
    .se  (se),
1559 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1560 95 fafa1971
    .so  ()
1561
);
1562
 
1563
assign  thrid_d[1:0] = ifu_tlu_thrid_d[1:0];
1564
 
1565
assign  thread0_rsel_d = ~thrid_d[1] & ~thrid_d[0];
1566
assign  thread1_rsel_d = ~thrid_d[1] &  thrid_d[0];
1567
assign  thread2_rsel_d =  thrid_d[1] & ~thrid_d[0];
1568
assign  thread3_rsel_d =  thrid_d[1] &  thrid_d[0];
1569
 
1570
//
1571
// modified due to rte failure 
1572 113 albert.wat
dff_s #(2) dff_thrid_e (
1573 95 fafa1971
    .din (thrid_d[1:0]),
1574
        .q   (thrid_e[1:0]),
1575
    .clk (clk),
1576
    .se  (se),
1577 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1578 95 fafa1971
    .so  ()
1579
);
1580
 
1581 113 albert.wat
dff_s #(2) dff_thrid_m (
1582 95 fafa1971
    .din (thrid_e[1:0]),
1583
    .q   (thrid_m[1:0]),
1584
    .clk (clk),
1585
    .se  (se),
1586 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1587 95 fafa1971
    .so  ()
1588
);
1589
 
1590 113 albert.wat
dff_s #(2) dff_thrid_g (
1591 95 fafa1971
    .din (thrid_m[1:0]),
1592
    .q   (thrid_g[1:0]),
1593
    .clk (clk),
1594
    .se  (se),
1595 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1596 95 fafa1971
    .so  ()
1597
);
1598
 
1599
assign  thread0_rsel_e = ~(|thrid_e[1:0]);
1600
assign  thread1_rsel_e = ~thrid_e[1] &  thrid_e[0];
1601
assign  thread2_rsel_e =  thrid_e[1] & ~thrid_e[0];
1602
assign  thread3_rsel_e =  (&thrid_e[1:0]);
1603
 
1604
assign  tlu_thrd_rsel_e[0] = thread0_rsel_e;
1605
assign  tlu_thrd_rsel_e[1] = thread1_rsel_e;
1606
assign  tlu_thrd_rsel_e[2] = thread2_rsel_e;
1607
assign  tlu_thrd_rsel_e[3] = thread3_rsel_e;
1608
//
1609
// added for timing
1610 113 albert.wat
dff_s #(`TLU_THRD_NUM) dff_thread_stg_m (
1611 95 fafa1971
    .din ({thread3_rsel_e, thread2_rsel_e, thread1_rsel_e, thread0_rsel_e}),
1612
    .q   ({thread3_stg_m, thread2_stg_m, thread1_stg_m, thread0_stg_m}),
1613
    .clk (clk),
1614
    .se  (se),
1615 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1616 95 fafa1971
    .so  ()
1617
);
1618
 
1619
assign thread0_stg_m_buf = thread0_stg_m;
1620
assign thread1_stg_m_buf = thread1_stg_m;
1621
assign thread2_stg_m_buf = thread2_stg_m;
1622
assign thread3_stg_m_buf = thread3_stg_m;
1623
 
1624
assign  thread0_rsel_m = ~(|thrid_m[1:0]);
1625
assign  thread1_rsel_m = ~thrid_m[1] &  thrid_m[0];
1626
assign  thread2_rsel_m =  thrid_m[1] & ~thrid_m[0];
1627
assign  thread3_rsel_m =  (&thrid_m[1:0]);
1628
 
1629
assign  thread0_rsel_dec_g = ~(|thrid_g[1:0]);
1630
assign  thread1_rsel_dec_g = ~thrid_g[1] &  thrid_g[0];
1631
assign  thread2_rsel_dec_g =  thrid_g[1] & ~thrid_g[0];
1632
assign  thread3_rsel_dec_g =  (&thrid_g[1:0]);
1633
 
1634 113 albert.wat
dff_s #(`TLU_THRD_NUM) dff_thread_rsel_g (
1635 95 fafa1971
    .din ({thread3_rsel_m, thread2_rsel_m, thread1_rsel_m, thread0_rsel_m}),
1636
    .q   ({thread3_rsel_g, thread2_rsel_g, thread1_rsel_g, thread0_rsel_g}),
1637
    .clk (clk),
1638
    .se  (se),
1639 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1640 95 fafa1971
    .so  ()
1641
);
1642
 
1643 113 albert.wat
dff_s #(`TLU_THRD_NUM) dff_thread_wsel_g (
1644 95 fafa1971
    .din ({thread3_rsel_m, thread2_rsel_m, thread1_rsel_m, thread0_rsel_m}),
1645
    .q   ({thread3_wsel_g, thread2_wsel_g, thread1_wsel_g, thread0_wsel_g}),
1646
    .clk (clk),
1647
    .se  (se),
1648 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1649 95 fafa1971
    .so  ()
1650
);
1651
// timing -fix: load redistribution
1652
/*
1653
assign  thread0_rsel_g = thread0_rsel_dec_g;
1654
assign  thread1_rsel_g = thread1_rsel_dec_g;
1655
assign  thread2_rsel_g = thread2_rsel_dec_g;
1656
assign  thread3_rsel_g = thread3_rsel_dec_g;
1657
*/
1658
// 
1659
 
1660 113 albert.wat
dff_s #(2) dff_stgdntry_w2 (
1661 95 fafa1971
    .din ({done_inst_g,retry_inst_g}),
1662
        .q   ({done_inst_w2,retry_inst_w2}),
1663
    .clk (clk),
1664
    .se  (se),
1665 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1666 95 fafa1971
    .so  ()
1667
);
1668
//
1669
// modified for bug 4561
1670
assign inst_vld_m =
1671
           ifu_tlu_inst_vld_m & ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1672
           (tlu_flush_pipe_w | inst_ifu_flush_w));
1673
/*
1674
assign inst_vld_m =
1675
           ifu_tlu_inst_vld_m & ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1676
           (tlu_flush_pipe_w | inst_ifu_flush_w)) & ~((thrid_w2[1:0] == tlu_exu_tid_m[1:0]) &
1677
            lsu_defr_trap_g);
1678
*/
1679
//
1680
 
1681
assign tlu_inst_vld_nq_m =
1682
           ifu_tlu_inst_vld_m & ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1683
           tlu_flush_all_w);
1684
 
1685 113 albert.wat
dff_s dff_stgivld_g (
1686 95 fafa1971
    .din (inst_vld_m),
1687
    .q   (inst_vld_nf_g),
1688
    .clk (clk),
1689
    .se  (se),
1690 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1691 95 fafa1971
    .so  ()
1692
);
1693
//
1694
// modified for timing
1695
/*
1696 113 albert.wat
dffr_s dffr_inst_ifu_flush_w (
1697 95 fafa1971
    .din (ifu_tlu_flush_m),
1698
        .q   (inst_ifu_flush_w),
1699
    .clk (clk),
1700
    .rst (local_rst),
1701
    .se  (se),
1702 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1703 95 fafa1971
    .so  ()
1704
);
1705
*/
1706
assign inst_ifu_flush_w  = ifu_tlu_flush_fd_w;
1707
assign inst_ifu_flush2_w = ifu_tlu_flush_fd_w;
1708
 
1709
// added for bug 2133
1710
assign inst_vld_g =
1711
       inst_vld_nf_g & ~(inst_ifu_flush_w | lsu_tlu_defr_trp_taken_g);
1712
       // modified for bug 4561
1713
       // inst_vld_nf_g & ~(inst_ifu_flush_w | lsu_tlu_defr_trp_taken_g | 
1714
       // ((thrid_w2[1:0] == thrid_g[1:0]) & lsu_defr_trap_g));
1715
 
1716 113 albert.wat
dff_s dff_stgivld_w2 (
1717 95 fafa1971
    .din (inst_vld_g),
1718
        .q   (inst_vld_w2),
1719
    .clk (clk),
1720
    .se  (se),
1721 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1722 95 fafa1971
    .so  ()
1723
);
1724
//
1725
// modified due to timing
1726
// assign       cwp_fastcmplt_g = cwp_fastcmplt_w & inst_vld_g;
1727
assign  cwp_fastcmplt_g = cwp_fastcmplt_uq_g & inst_vld_g;
1728
 
1729 113 albert.wat
dff_s dff_stgfcmplt_w2 (
1730 95 fafa1971
    .din (cwp_fastcmplt_g),
1731
        .q   (cwp_fastcmplt_w2),
1732
    .clk (clk),
1733
    .se  (se),
1734 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1735 95 fafa1971
    .so  ()
1736
);
1737
 
1738
// The stage name assignment may have to be changed !!
1739
// done/retry qualified with inst_vld as it could be flushed.
1740
assign  tlu_ifu_trappc_vld_w1   =       ((retry_inst_w2 | done_inst_w2) & inst_vld_w2 & cwp_fastcmplt_w2) |
1741
                                        thrd0_traps_w2 | thrd1_traps_w2 |
1742
                                        thrd2_traps_w2 | thrd3_traps_w2 | cwp_cmplt_w2;
1743
                                        //thrd2_traps_w2 | thrd3_traps_w2) & inst_vld_w2 | cwp_cmplt_w2;           
1744
assign  tlu_ifu_trapnpc_vld_w1  =       (retry_inst_w2 & inst_vld_w2 & cwp_fastcmplt_w2) |
1745
                                        thrd0_traps_w2 | thrd1_traps_w2 |
1746
                                        thrd2_traps_w2 | thrd3_traps_w2 | cwp_cmplt_rtry_w2;
1747
                                        //) & inst_vld_w2 | cwp_cmplt_w2;          
1748
//
1749
// modified for hypervisor support
1750
// assign       tlu_ifu_trap_tid_w1[1:0]=       cwp_cmplt_w2 ? cwp_cmplt_tid_w2[1:0] : trap_tid_w2[1:0];
1751
//
1752
// recoded for timing
1753
// assign       true_trap_tid_g[1:0] = cwp_cmplt_g ? cwp_cmplt_tid_g[1:0] : trap_tid_g[1:0];
1754
// modified for bug 4091 and 4491
1755
/*
1756
assign early_trap_tid_g[1:0] =
1757
               (((hwint_g | pib_wrap_trap_g| local_early_flush_pipe_w) &
1758
              ~(ifu_tlu_flush_fd_w | local_lsu_defr_trp_taken_g)) |
1759
           (dnrtry_inst_g & cwp_fastcmplt_g) | rstint_g) ? thrid_g[1:0] : pend_trap_tid_g[1:0];
1760
*/
1761
assign early_trap_tid_g[1:0] =
1762
               (((hwint_g | pib_wrap_trap_g| local_early_flush_pipe_w) & ~ifu_tlu_flush_fd_w) |
1763
           (dnrtry_inst_g & cwp_fastcmplt_g) | rstint_g) ? thrid_g[1:0] : pend_trap_tid_g[1:0];
1764
//
1765
// modified for bug 4561
1766
assign  true_trap_tid_g[1:0] =
1767
             // (lsu_defr_trap_g) ? thrid_w2[1:0]  : 
1768
             (dside_sync_trap_g | lsu_defr_trap_g) ? thrid_g[1:0] :
1769
              early_trap_tid_g[1:0];
1770
 
1771 113 albert.wat
dff_s #(2) dff_true_trap_tid_w2 (
1772 95 fafa1971
    .din (true_trap_tid_g[1:0]),
1773
    .q   (true_trap_tid_w2[1:0]),
1774
    .clk (clk),
1775
    .se  (se),
1776 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1777 95 fafa1971
    .so  ()
1778
);
1779
assign tlu_ifu_trap_tid_w1[1:0] = true_trap_tid_w2[1:0];
1780
 
1781
// determine the mode of operation for the trapped thread
1782
// modified for timing 
1783
/*
1784
assign tlu_trap_hpstate_enb =
1785
           (~(|true_trap_tid_g[1:0]))? tlu_hpstate_enb[0]:
1786
               ((~true_trap_tid_g[1] & true_trap_tid_g[0])? tlu_hpstate_enb[1]:
1787
                   ((true_trap_tid_g[1] & ~true_trap_tid_g[0])? tlu_hpstate_enb[2]:
1788
                       tlu_hpstate_enb[3]));
1789
*/
1790
assign tlu_trap_hpstate_enb =
1791
           (~(|true_trap_tid_w2[1:0]))? tlu_hpstate_enb[0]:
1792
               ((~true_trap_tid_w2[1] & true_trap_tid_w2[0])? tlu_hpstate_enb[1]:
1793
                   ((true_trap_tid_w2[1] & ~true_trap_tid_w2[0])? tlu_hpstate_enb[2]:
1794
                       tlu_hpstate_enb[3]));
1795
 
1796
//=========================================================================================
1797
//      Local Exceptions within TLU/MMU
1798
//=========================================================================================
1799
 
1800
// These are to be merged with lsu reported exceptions.
1801
// 
1802
// modified due to early_flush timing fix
1803
// assign       local_sync_trap_g = tlu_mmu_sync_data_excp_g;
1804
// 
1805
// modified for hypervisor support
1806
// modified for timing 
1807
assign  local_sync_trap_m =
1808
               (true_hscpd_dacc_excpt_m | true_qtail_dacc_excpt_m) & inst_vld_m;
1809
// 
1810
// added for dsfsr bug
1811
assign  tlu_lsu_priv_trap_m =
1812
               (true_hscpd_dacc_excpt_m | true_qtail_dacc_excpt_m);
1813
//
1814
/*
1815
// added for timing
1816 113 albert.wat
dffr_s dffr_tlu_lsu_priv_trap_w  (
1817 95 fafa1971
    .din (tlu_lsu_priv_trap_m),
1818
    .q   (tlu_lsu_priv_trap_w),
1819
    .rst (local_rst),
1820
    .clk (clk),
1821
    .se  (se),
1822 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1823 95 fafa1971
    .so  ()
1824
);
1825
//
1826
*/
1827
// added for timing 
1828
// modified for bug 3618
1829
assign true_hscpd_dacc_excpt_m =
1830
           tlu_hscpd_dacc_excpt_m &
1831
           ((thread0_stg_m_buf & ~tlu_hyper_lite[0]) |
1832
            (thread1_stg_m_buf & ~tlu_hyper_lite[1]) |
1833
            (thread2_stg_m_buf & ~tlu_hyper_lite[2]) |
1834
            (thread3_stg_m_buf & ~tlu_hyper_lite[3]));
1835
 
1836
assign true_qtail_dacc_excpt_m =
1837
           ((thread0_stg_m_buf & tlu_hpstate_enb[0] &  ~tlu_hpstate_priv[0] &
1838
             tlu_pstate_priv_buf[0])  |
1839
            (thread1_stg_m_buf & tlu_hpstate_enb[1] &  ~tlu_hpstate_priv[1] &
1840
             tlu_pstate_priv_buf[1])  |
1841
            (thread2_stg_m_buf & tlu_hpstate_enb[2] &  ~tlu_hpstate_priv[2] &
1842
             tlu_pstate_priv_buf[2])  |
1843
            (thread3_stg_m_buf & tlu_hpstate_enb[3] &  ~tlu_hpstate_priv[3] &
1844
             tlu_pstate_priv_buf[3])) & tlu_qtail_dacc_excpt_m;
1845
 
1846 113 albert.wat
dffr_s dffr_local_sync_trap_g  (
1847 95 fafa1971
    .din (local_sync_trap_m),
1848
    .q   (local_sync_trap_g),
1849
    .rst (local_rst),
1850
    .clk (clk),
1851
    .se  (se),
1852 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1853 95 fafa1971
    .so  ()
1854
);
1855
 
1856
//=========================================================================================
1857
//      Queuing traps
1858
//=========================================================================================
1859
 
1860
// For current instr, prioritize traps across pipe. There are 3 synchronous sources :
1861
// ifu,exu,lsu. Assume ifu traps have highest priority so compare has to be done
1862
// only between exu and lsu traps.
1863
 
1864
// added for timing; moved qualification from IFU to TLU
1865
assign  ifu_rstint_m =
1866
        ifu_tlu_rstint_m & ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1867
        tlu_flush_all_w) & inst_vld_m;
1868
assign  ifu_hwint_m =
1869
        ifu_tlu_hwint_m & ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1870
        tlu_flush_all_w) & inst_vld_m;
1871
assign  ifu_swint_m =
1872
        ifu_tlu_swint_m & ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) &
1873
        tlu_flush_all_w) & inst_vld_m;
1874
 
1875
// generate the thread specific ifu flush signal - added for bug 2133
1876
assign ifu_thrd_flush_w[0] = inst_ifu_flush2_w & thread0_rsel_dec_g;
1877
assign ifu_thrd_flush_w[1] = inst_ifu_flush2_w & thread1_rsel_dec_g;
1878
assign ifu_thrd_flush_w[2] = inst_ifu_flush2_w & thread2_rsel_dec_g;
1879
assign ifu_thrd_flush_w[3] = inst_ifu_flush2_w & thread3_rsel_dec_g;
1880
 
1881
 
1882
// INTERRUPT
1883 113 albert.wat
dff_s #(9) dff_stgint_g (
1884 95 fafa1971
   .din ({ifu_rstint_m,ifu_hwint_m,ifu_swint_m,int_tlu_rstid_m[5:0]}),
1885
   .q   ({rstint_g,hwint_g,swint_g,rstid_g[5:0]}),
1886
   .clk (clk),
1887
   .se  (se),
1888 113 albert.wat
   `SIMPLY_RISC_SCANIN,
1889 95 fafa1971
   .so  ()
1890
);
1891
 
1892
// Determine type of reset. Type of reset determines what state gets updated.
1893
// This is the same as wrm reset !!! Can we then turn off writes to TNPC, TPC ???
1894
assign  por_rstint_g = ((rstid_g[5:0] == 6'h01) & rstint_g);
1895
assign  por_rstint0_g = por_rstint_g & thread0_rsel_g;
1896
assign  por_rstint1_g = por_rstint_g & thread1_rsel_g;
1897
assign  por_rstint2_g = por_rstint_g & thread2_rsel_g;
1898
assign  por_rstint3_g = por_rstint_g & thread3_rsel_g;
1899
// 
1900
// added for bug 4749 
1901
assign  xir_rstint_g = ((rstid_g[5:0] == 6'h03) & rstint_g);
1902
 
1903 113 albert.wat
dff_s dff_por_rstint_w2 (
1904 95 fafa1971
    .din (por_rstint_g),
1905
        .q   (por_rstint_w2),
1906
    .clk (clk),
1907
    .se  (se),
1908 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1909 95 fafa1971
    .so  ()
1910
);
1911
 
1912
assign  por_rstint0_w2 = por_rstint_w2 & thread0_wsel_w2;
1913
assign  por_rstint1_w2 = por_rstint_w2 & thread1_wsel_w2;
1914
assign  por_rstint2_w2 = por_rstint_w2 & thread2_wsel_w2;
1915
assign  por_rstint3_w2 = por_rstint_w2 & thread3_wsel_w2;
1916
 
1917
assign  tlu_por_rstint_g[0]  = por_rstint0_g;
1918
assign  tlu_por_rstint_g[1]  = por_rstint1_g;
1919
assign  tlu_por_rstint_g[2]  = por_rstint2_g;
1920
assign  tlu_por_rstint_g[3]  = por_rstint3_g;
1921
 
1922
assign  rstint_taken = rstint_g & inst_vld_g;
1923
 
1924
// hwint needs to be requalified with pstate.ie. IFU will replay hwint in
1925
// case dropped. IFU needs to source thread id in the form of ifu_tlu_thrid_d.
1926
assign  hwint_taken = hwint_g & inst_vld_g;
1927
//
1928
// modified for bug 5127
1929
// assign       sirint_taken = sir_inst_g & inst_vld_g; 
1930
assign  sirint_taken =
1931
            sir_inst_g & inst_vld_g  & ~(pib_wrap_trap_nq_g |
1932 113 albert.wat
            lsu_tlu_defr_trp_taken_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0]));
1933 95 fafa1971
 
1934
assign  swint_taken = swint_g & inst_vld_g;
1935
 
1936
/*
1937
assign  swint_thrd0_taken = swint_taken & thread0_rsel_g & tlu_int_pstate_ie[0];
1938
assign  swint_thrd1_taken = swint_taken & thread1_rsel_g & tlu_int_pstate_ie[1];
1939
assign  swint_thrd2_taken = swint_taken & thread2_rsel_g & tlu_int_pstate_ie[2];
1940
assign  swint_thrd3_taken = swint_taken & thread3_rsel_g & tlu_int_pstate_ie[3];
1941
//
1942
//modified for hypervisor support
1943
assign  swint_id[3:0]   =
1944
        swint_thrd0_taken ? sftint0_id[3:0] :
1945
                swint_thrd1_taken ? sftint1_id[3:0] :
1946
                        swint_thrd2_taken ? sftint2_id[3:0] :
1947
                                swint_thrd3_taken ? sftint3_id[3:0] :
1948
                                        4'bxxxx;
1949
*/
1950
//
1951
//added for timing 
1952 113 albert.wat
dffr_s #(`TLU_THRD_NUM) dffr_tlu_cpu_mondo_trap (
1953
    .din (tlu_cpu_mondo_cmp[`TLU_THRD_NUM-1:0]),
1954
    .q   (tlu_cpu_mondo_trap[`TLU_THRD_NUM-1:0]),
1955 95 fafa1971
    .rst (local_rst),
1956
    .clk (clk),
1957
    .se  (se),
1958 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1959 95 fafa1971
    .so  ()
1960
);
1961
//
1962 113 albert.wat
dffr_s #(`TLU_THRD_NUM) dffr_tlu_dev_mondo_trap (
1963
    .din (tlu_dev_mondo_cmp[`TLU_THRD_NUM-1:0]),
1964
    .q   (tlu_dev_mondo_trap[`TLU_THRD_NUM-1:0]),
1965 95 fafa1971
    .rst (local_rst),
1966
    .clk (clk),
1967
    .se  (se),
1968 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1969 95 fafa1971
    .so  ()
1970
);
1971
 
1972 113 albert.wat
dffr_s #(`TLU_THRD_NUM) dffr_tlu_resum_err_trap (
1973
    .din (tlu_resum_err_cmp[`TLU_THRD_NUM-1:0]),
1974
    .q   (tlu_resum_err_trap[`TLU_THRD_NUM-1:0]),
1975 95 fafa1971
    .rst (local_rst),
1976
    .clk (clk),
1977
    .se  (se),
1978 113 albert.wat
    `SIMPLY_RISC_SCANIN,
1979 95 fafa1971
    .so  ()
1980
);
1981
//
1982
assign cpu_mondo_trap_g =
1983
       (thread0_wsel_g)? tlu_cpu_mondo_trap[0]:
1984
       (thread1_wsel_g)? tlu_cpu_mondo_trap[1]:
1985
       (thread2_wsel_g)? tlu_cpu_mondo_trap[2]:
1986
       tlu_cpu_mondo_trap[3];
1987
 
1988
assign dev_mondo_trap_g =
1989
       (thread0_wsel_g)? tlu_dev_mondo_trap[0]:
1990
       (thread1_wsel_g)? tlu_dev_mondo_trap[1]:
1991
       (thread2_wsel_g)? tlu_dev_mondo_trap[2]:
1992
       tlu_dev_mondo_trap[3];
1993
 
1994
assign sftint_id_w2[3:0] =
1995
       (thread0_wsel_w2)? sftint0_id[3:0]:
1996
       (thread1_wsel_w2)? sftint1_id[3:0]:
1997
       (thread2_wsel_w2)? sftint2_id[3:0]:
1998
        sftint3_id[3:0];
1999
 
2000 113 albert.wat
dffr_s dffr_cpu_mondo_trap_w2 (
2001 95 fafa1971
    .din (cpu_mondo_trap_g),
2002
    .q   (cpu_mondo_trap_w2),
2003
    .rst (local_rst),
2004
    .clk (clk),
2005
    .se  (se),
2006 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2007 95 fafa1971
    .so  ()
2008
);
2009
 
2010 113 albert.wat
dffr_s dffr_dev_mondo_trap_w2 (
2011 95 fafa1971
    .din (dev_mondo_trap_g),
2012
    .q   (dev_mondo_trap_w2),
2013
    .rst (local_rst),
2014
    .clk (clk),
2015
    .se  (se),
2016 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2017 95 fafa1971
    .so  ()
2018
);
2019
 
2020
assign final_swint_id_w2[6:0] =
2021 113 albert.wat
       (cpu_mondo_trap_w2)? `CPU_MONDO_TRAP :
2022
       (dev_mondo_trap_w2)? `DEV_MONDO_TRAP :
2023 95 fafa1971
        {3'b100, sftint_id_w2[3:0]};
2024
 
2025
// recoded for timing for bug 5117
2026
/*
2027
assign final_swint0_id[6:0] =
2028
        tlu_cpu_mondo_trap[0] ? `CPU_MONDO_TRAP :
2029
                ((tlu_dev_mondo_trap[0] & ~tlu_cpu_mondo_trap[0]) ? `DEV_MONDO_TRAP :
2030
                      {3'b100, sftint0_id[3:0]});
2031
 
2032
assign final_swint1_id[6:0] =
2033
        tlu_cpu_mondo_trap[1] ? `CPU_MONDO_TRAP :
2034
                ((tlu_dev_mondo_trap[1] & ~tlu_cpu_mondo_trap[1]) ? `DEV_MONDO_TRAP :
2035
                      {3'b100, sftint1_id[3:0]});
2036
 
2037
assign final_swint2_id[6:0] =
2038
        tlu_cpu_mondo_trap[2] ? `CPU_MONDO_TRAP :
2039
                ((tlu_dev_mondo_trap[2] & ~tlu_cpu_mondo_trap[2]) ? `DEV_MONDO_TRAP :
2040
                      {3'b100, sftint2_id[3:0]});
2041
 
2042
assign final_swint3_id[6:0] =
2043
        tlu_cpu_mondo_trap[3] ? `CPU_MONDO_TRAP :
2044
                ((tlu_dev_mondo_trap[3] & ~tlu_cpu_mondo_trap[3]) ? `DEV_MONDO_TRAP :
2045
                      {3'b100, sftint3_id[3:0]});
2046
 
2047
assign final_swint_id[6:0]      =
2048
        swint_thrd0_taken ? final_swint0_id[6:0] :
2049
                swint_thrd1_taken ? final_swint1_id[6:0] :
2050
                        swint_thrd2_taken ? final_swint2_id[6:0] :
2051
                                swint_thrd3_taken ? final_swint3_id[6:0] :
2052
                                        7'bxxxxxxx;
2053
*/
2054
 
2055
// Assume rstid(interrupt/reset vector) is the same as trap type.
2056
// Need to confirm !!!!
2057
// sftware sir is generated by ifu decode.
2058
// ttype for internal wdr is tt of trap itself.
2059
 
2060
// sir inst at maxtl can result entry to error state and thus wdr
2061
// modified for bug 4749 and 4906
2062
assign internal_wdr_trap[0] =
2063
           (thrd0_traps & trp_lvl0_at_maxtl) &
2064
          ~((por_rstint_g | xir_rstint_g) & thread0_rsel_g);
2065
assign internal_wdr_trap[1] =
2066
           (thrd1_traps & trp_lvl1_at_maxtl) &
2067
          ~((por_rstint_g | xir_rstint_g) & thread1_rsel_g);
2068
assign internal_wdr_trap[2] =
2069
           (thrd2_traps & trp_lvl2_at_maxtl) &
2070
          ~((por_rstint_g | xir_rstint_g) & thread2_rsel_g);
2071
assign internal_wdr_trap[3] =
2072
           (thrd3_traps & trp_lvl3_at_maxtl) &
2073
          ~((por_rstint_g | xir_rstint_g) & thread3_rsel_g);
2074
 
2075
assign internal_wdr =
2076
           internal_wdr_trap[0] | internal_wdr_trap[1] |
2077
           internal_wdr_trap[2] | internal_wdr_trap[3];
2078
/*
2079
assign  internal_wdr =
2080
                ((thrd0_traps & trp_lvl0_at_maxtl) |
2081
                (thrd1_traps & trp_lvl1_at_maxtl) |
2082
                (thrd2_traps & trp_lvl2_at_maxtl) |
2083
                (thrd3_traps & trp_lvl3_at_maxtl)) &
2084
       ~(por_rstint_g | xir_rstint_g);
2085
*/
2086
//
2087
// modified for bug 4640 and bug5127 
2088
assign  tlu_self_boot_rst_g =
2089
              rstint_g | internal_wdr | (sir_inst_g &
2090
              ~(lsu_defr_trap_g | pib_wrap_trap_g |
2091 113 albert.wat
               (|tlz_trap_g[`TLU_THRD_NUM-1:0]))) | trap_to_redmode;
2092 95 fafa1971
              // (rstint_g | internal_wdr | (sir_inst_g & ~lsu_defr_trap_g) |
2093
 
2094
//
2095
// added for timing; moved qualification from IFU to TLU
2096
// modified for bug 4561
2097
assign  ifu_ttype_vld_m =
2098
            ifu_tlu_ttype_vld_m &
2099
            ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) & tlu_flush_pipe_w);
2100
/*
2101
assign  ifu_ttype_vld_m =
2102
            ifu_tlu_ttype_vld_m &
2103
            ~((thrid_g[1:0] == tlu_exu_tid_m[1:0]) & tlu_flush_pipe_w) &
2104
            ~((thrid_w2[1:0] == tlu_exu_tid_m[1:0]) & lsu_defr_trap_g);
2105
*/
2106
 
2107
// REGULAR TRAP
2108 113 albert.wat
dff_s #(20) dff_stgeftt_g (
2109 95 fafa1971
    .din ({exu_tlu_ttype_m[8:0],exu_tlu_ttype_vld_m,ifu_tlu_ttype_m[8:0],ifu_ttype_vld_m}),
2110
    .q   ({exu_ttype_g[8:0],exu_ttype_vld_g,ifu_ttype_tmp_g[8:0],ifu_ttype_vld_tmp_g}),
2111
    .clk (clk),
2112
    .se  (se),
2113 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2114 95 fafa1971
    .so  ()
2115
);
2116
 
2117
// added for bug 1293
2118
// added spu_tlu_rsrv_illgl_m2 to account for the new illeg_instr from spu
2119
//
2120
// modified for the hypervisor support - wsr_illeg_globals_g is no longer necessary
2121
// modified for pib support and timing fixes 
2122
/*
2123
assign ifu_ttype_g[8:0] = //((wsr_illeg_globals_g | spu_tlu_rsrv_illgl_m2) &
2124
                          (spu_tlu_rsrv_illgl_m2 &
2125
                         ~(ifu_ttype_tmp_g & (ifu_ttype_tmp_g < 9'h012)) &
2126
                         ~immu_miss_g) ?
2127
                           9'h010 :
2128
                          ((tlu_tick_npt_priv_act) ? 9'h037 :
2129
                          ifu_ttype_tmp_g);
2130
*/
2131
//
2132
// determine whether the processor is in user mode
2133
assign tlu_none_priv[0] = ~(tlu_hpstate_priv[0] | tlu_pstate_priv_buf[0]);
2134
assign tlu_none_priv[1] = ~(tlu_hpstate_priv[1] | tlu_pstate_priv_buf[1]);
2135
assign tlu_none_priv[2] = ~(tlu_hpstate_priv[2] | tlu_pstate_priv_buf[2]);
2136
assign tlu_none_priv[3] = ~(tlu_hpstate_priv[3] | tlu_pstate_priv_buf[3]);
2137
 
2138
assign tlu_hyper_lite[0] =
2139
           tlu_hpstate_priv[0]| (~tlu_hpstate_enb[0] & tlu_pstate_priv_buf[0]);
2140
assign tlu_hyper_lite[1] =
2141
           tlu_hpstate_priv[1]| (~tlu_hpstate_enb[1] & tlu_pstate_priv_buf[1]);
2142
assign tlu_hyper_lite[2] =
2143
           tlu_hpstate_priv[2]| (~tlu_hpstate_enb[2] & tlu_pstate_priv_buf[2]);
2144
assign tlu_hyper_lite[3] =
2145
           tlu_hpstate_priv[3]| (~tlu_hpstate_enb[3] & tlu_pstate_priv_buf[3]);
2146
//
2147
// htrap instruction illegal instruction trap  
2148
// this trap is taken only in hypervisor mode and not in hyper-lite
2149
// mode
2150
assign tlu_none_priv_m =
2151
          (tlu_none_priv[0] & tlu_hpstate_enb[0] & thread0_rsel_m) |
2152
          (tlu_none_priv[1] & tlu_hpstate_enb[1] & thread1_rsel_m) |
2153
          (tlu_none_priv[2] & tlu_hpstate_enb[2] & thread2_rsel_m) |
2154
          (tlu_none_priv[3] & tlu_hpstate_enb[3] & thread3_rsel_m);
2155
 
2156
assign htrap_ill_inst_m =
2157
    (exu_tlu_ttype_vld_m &  exu_tlu_ttype_m[8] &
2158
     exu_tlu_ttype_m[7]) &  tlu_none_priv_m;
2159
 
2160 113 albert.wat
dffr_s dffr_htrap_ill_inst_uf_g (
2161 95 fafa1971
   .din (htrap_ill_inst_m),
2162
   .q   (htrap_ill_inst_uf_g),
2163
   .rst (local_rst),
2164
   .clk (clk),
2165
   .se  (se),
2166 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2167 95 fafa1971
   .so  ()
2168
);
2169
 
2170
assign htrap_ill_inst_g = htrap_ill_inst_uf_g & ~inst_ifu_flush_w;
2171
// 
2172
// added for timing fix
2173
assign spu_ill_inst_m = spu_tlu_rsrv_illgl_m & inst_vld_m;
2174
 
2175 113 albert.wat
dffr_s dffr_spu_ill_inst_uf_g (
2176 95 fafa1971
   .din (spu_ill_inst_m),
2177
   // modified for bug 2133
2178
   // .q   (spu_ill_inst_g),
2179
   .q   (spu_ill_inst_uf_g),
2180
   .rst (local_rst),
2181
   .clk (clk),
2182
   .se  (se),
2183 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2184 95 fafa1971
   .so  ()
2185
);
2186
 
2187
 
2188
// 
2189
// added for bug 2133
2190
// modified at Farnad's request for bug 3599
2191
// modified back to the old behavior (pre bug 3599) due to bug 4698
2192
assign spu_ill_inst_g =
2193
//             spu_ill_inst_uf_g & ~(inst_ifu_flush_w); 
2194
// fix for bug 5863. Only a stxa to asi=40 with opcode-rsvd should cause an illgl_va
2195
           spu_ill_inst_uf_g & ~(inst_ifu_flush_w | lsu_tlu_early_flush_w);
2196
 
2197
assign ffu_higher_pri_g =
2198
           ffu_ill_inst_g & (ifu_ttype_vld_tmp_g & (ifu_ttype_tmp_g == 9'h020));
2199
 
2200
//
2201
assign ifu_ttype_g[8:0] = (((spu_ill_inst_g  | ffu_ill_inst_g | htrap_ill_inst_g) &
2202
                         ~(ifu_ttype_vld_tmp_g   & (ifu_ttype_tmp_g < 9'h012)) &
2203
                         ~immu_miss_g) | ffu_higher_pri_g) ?
2204
                           9'h010 :
2205
                          ((tick_npt_priv_act_g |
2206
                           (pib_priv_act_trap_g & ~ifu_ttype_vld_tmp_g)) ? 9'h037 :
2207
                           ifu_ttype_tmp_g);
2208
//
2209
// added for timing fix
2210
assign pib_priv_act_early_trap_m =
2211
           ((pib_priv_act_trap_m[0] & inst_vld_m & thread0_rsel_m) &
2212
             ~(tlu_pstate_priv_buf[0] | tlu_hpstate_priv[0])) |
2213
           ((pib_priv_act_trap_m[1] & inst_vld_m & thread1_rsel_m) &
2214
             ~(tlu_pstate_priv_buf[1] | tlu_hpstate_priv[1])) |
2215
           ((pib_priv_act_trap_m[2] & inst_vld_m & thread2_rsel_m) &
2216
             ~(tlu_pstate_priv_buf[2] | tlu_hpstate_priv[2])) |
2217
           ((pib_priv_act_trap_m[3] & inst_vld_m & thread3_rsel_m) &
2218
             ~(tlu_pstate_priv_buf[3] | tlu_hpstate_priv[3]));
2219
//
2220
 
2221
 
2222
// recoded the following for timing:
2223
/*
2224
assign exu_pib_priv_act_trap_m =
2225
           ((pib_priv_act_trap_m[0] & thread0_rsel_m) &
2226
             ~(tlu_pstate_priv[0] | tlu_hpstate_priv[0])) |
2227
           ((pib_priv_act_trap_m[1] & thread1_rsel_m) &
2228
             ~(tlu_pstate_priv[1] | tlu_hpstate_priv[1])) |
2229
           ((pib_priv_act_trap_m[2] & thread2_rsel_m) &
2230
             ~(tlu_pstate_priv[2] | tlu_hpstate_priv[2])) |
2231
           ((pib_priv_act_trap_m[3] & thread3_rsel_m) &
2232
             ~(tlu_pstate_priv[3] | tlu_hpstate_priv[3]));
2233
*/
2234
 
2235
wire [3:0] pib_priv_act_trap_thrd_qual_m;
2236
wire [3:0] pib_priv_act_trap_thrd_hpstatepriv_qual_m;
2237
wire [3:0] pib_priv_act_trap_thrd_hpstatepriv_pstatepriv_m;
2238
 
2239
assign  pib_priv_act_trap_thrd_qual_m[0] = pib_priv_act_trap_m[0] & thread0_rsel_m ;
2240
assign  pib_priv_act_trap_thrd_qual_m[1] = pib_priv_act_trap_m[1] & thread1_rsel_m ;
2241
assign  pib_priv_act_trap_thrd_qual_m[2] = pib_priv_act_trap_m[2] & thread2_rsel_m ;
2242
assign  pib_priv_act_trap_thrd_qual_m[3] = pib_priv_act_trap_m[3] & thread3_rsel_m ;
2243
 
2244
assign pib_priv_act_trap_thrd_hpstatepriv_qual_m[0] = pib_priv_act_trap_thrd_qual_m[0] & ~tlu_hpstate_priv[0];
2245
assign pib_priv_act_trap_thrd_hpstatepriv_qual_m[1] = pib_priv_act_trap_thrd_qual_m[1] & ~tlu_hpstate_priv[1];
2246
assign pib_priv_act_trap_thrd_hpstatepriv_qual_m[2] = pib_priv_act_trap_thrd_qual_m[2] & ~tlu_hpstate_priv[2];
2247
assign pib_priv_act_trap_thrd_hpstatepriv_qual_m[3] = pib_priv_act_trap_thrd_qual_m[3] & ~tlu_hpstate_priv[3];
2248
 
2249
assign pib_priv_act_trap_thrd_hpstatepriv_pstatepriv_m[0] = pib_priv_act_trap_thrd_hpstatepriv_qual_m[0] &
2250
                                                                ~tlu_pstate_priv[0];
2251
assign pib_priv_act_trap_thrd_hpstatepriv_pstatepriv_m[1] = pib_priv_act_trap_thrd_hpstatepriv_qual_m[1] &
2252
                                                                ~tlu_pstate_priv[1];
2253
assign pib_priv_act_trap_thrd_hpstatepriv_pstatepriv_m[2] = pib_priv_act_trap_thrd_hpstatepriv_qual_m[2] &
2254
                                                                ~tlu_pstate_priv[2];
2255
assign pib_priv_act_trap_thrd_hpstatepriv_pstatepriv_m[3] = pib_priv_act_trap_thrd_hpstatepriv_qual_m[3] &
2256
                                                                ~tlu_pstate_priv[3];
2257
 
2258
assign exu_pib_priv_act_trap_m = (|pib_priv_act_trap_thrd_hpstatepriv_pstatepriv_m[3:0]);
2259
 
2260
 
2261
// 
2262
// added for make pib overflow trap precise
2263
assign pib_trap_en[0] = tlu_int_pstate_ie[0] & (true_pil0[3:0] < 4'hf);
2264
assign pib_trap_en[1] = tlu_int_pstate_ie[1] & (true_pil1[3:0] < 4'hf);
2265
assign pib_trap_en[2] = tlu_int_pstate_ie[2] & (true_pil2[3:0] < 4'hf);
2266
assign pib_trap_en[3] = tlu_int_pstate_ie[3] & (true_pil3[3:0] < 4'hf);
2267
//
2268
// added for bug 5017
2269 113 albert.wat
dffr_s dffr_picl_wrap_pend_0 (
2270 95 fafa1971
    .din (pib_picl_wrap[0]),
2271
    .q   (picl_wrap_pend[0]),
2272
    .rst (local_rst | (thread_inst_vld_w2[0] & ~pib_picl_wrap[0] & ~tlu_full_flush_pipe_w2)),
2273
    .clk (clk),
2274
    .se  (se),
2275 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2276 95 fafa1971
    .so  ()
2277
);
2278 113 albert.wat
dffr_s dffr_picl_wrap_pend_1 (
2279 95 fafa1971
    .din (pib_picl_wrap[1]),
2280
    .q   (picl_wrap_pend[1]),
2281
    .rst (local_rst | (thread_inst_vld_w2[1] & ~pib_picl_wrap[1] & ~tlu_full_flush_pipe_w2)),
2282
    .clk (clk),
2283
    .se  (se),
2284 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2285 95 fafa1971
    .so  ()
2286
);
2287 113 albert.wat
dffr_s dffr_picl_wrap_pend_2 (
2288 95 fafa1971
    .din (pib_picl_wrap[2]),
2289
    .q   (picl_wrap_pend[2]),
2290
    .rst (local_rst | (thread_inst_vld_w2[2] & ~pib_picl_wrap[2] & ~tlu_full_flush_pipe_w2)),
2291
    .clk (clk),
2292
    .se  (se),
2293 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2294 95 fafa1971
    .so  ()
2295
);
2296 113 albert.wat
dffr_s dffr_picl_wrap_pend_3 (
2297 95 fafa1971
    .din (pib_picl_wrap[3]),
2298
    .q   (picl_wrap_pend[3]),
2299
    .rst (local_rst | (thread_inst_vld_w2[3] & ~pib_picl_wrap[3] & ~tlu_full_flush_pipe_w2)),
2300
    .clk (clk),
2301
    .se  (se),
2302 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2303 95 fafa1971
    .so  ()
2304
);
2305
 
2306
assign tlu_picl_wrap_flg_m =
2307
       (picl_wrap_pend[0] & thread0_stg_m_buf) |
2308
       (picl_wrap_pend[1] & thread1_stg_m_buf) |
2309
       (picl_wrap_pend[2] & thread2_stg_m_buf) |
2310
       (picl_wrap_pend[3] & thread3_stg_m_buf);
2311
 
2312
// modified for bug 4086, 4206, 4246 and 4314
2313
// modified for bug 5033, 5083 and 5017
2314
// modified for bug 5436 - Niagara 2.0
2315
 
2316
// changed pend_pich_cnt_hld to pend_pich_cnt_hld_noqual as per bug5436(reopened 9/17/04).
2317
assign pib_wrap_m[0] =
2318
           // (pib_picl_wrap[0] |
2319
           ((picl_wrap_pend[0] & thread0_rsel_m) |
2320
           (pich_wrap_flg[0] & inst_vld_m & thread0_rsel_m) |
2321
           (pich_onebelow_flg[0] & (inst_vld_m & thread0_rsel_m) &
2322
           ((inst_vld_g & thread0_rsel_g) | (inst_vld_w2 & thread0_wsel_w2))) |
2323
           (pich_twobelow_flg[0] & (inst_vld_m & thread0_rsel_m) &
2324
           (inst_vld_g & thread0_rsel_g) & (inst_vld_w2 & thread0_wsel_w2))) &
2325
            pib_trap_en[0] & ~(tlu_flush_pipe_w & thread0_rsel_g) & ~pend_pich_cnt_hld_noqual[0];
2326
assign pib_wrap_m[1] =
2327
           // (pib_picl_wrap[1] |
2328
           ((picl_wrap_pend[1] & thread1_rsel_m) |
2329
           (pich_wrap_flg[1] & inst_vld_m & thread1_rsel_m) |
2330
           (pich_onebelow_flg[1] & (inst_vld_m & thread1_rsel_m) &
2331
           ((inst_vld_g & thread1_rsel_g) | (inst_vld_w2 & thread1_wsel_w2))) |
2332
           (pich_twobelow_flg[1] & (inst_vld_m & thread1_rsel_m) &
2333
           (inst_vld_g & thread1_rsel_g) & (inst_vld_w2 & thread1_wsel_w2))) &
2334
            pib_trap_en[1] & ~(tlu_flush_pipe_w & thread1_rsel_g) & ~pend_pich_cnt_hld_noqual[1];
2335
assign pib_wrap_m[2] =
2336
           // (pib_picl_wrap[2] |
2337
           ((picl_wrap_pend[2] & thread2_rsel_m) |
2338
           (pich_wrap_flg[2] & inst_vld_m & thread2_rsel_m) |
2339
           (pich_onebelow_flg[2] & (inst_vld_m & thread2_rsel_m) &
2340
           ((inst_vld_g & thread2_rsel_g) | (inst_vld_w2 & thread2_wsel_w2))) |
2341
           (pich_twobelow_flg[2] & (inst_vld_m & thread2_rsel_m) &
2342
           (inst_vld_g & thread2_rsel_g) & (inst_vld_w2 & thread2_wsel_w2))) &
2343
            pib_trap_en[2] & ~(tlu_flush_pipe_w & thread2_rsel_g) & ~pend_pich_cnt_hld_noqual[2];
2344
assign pib_wrap_m[3] =
2345
           // (pib_picl_wrap[3] |
2346
           ((picl_wrap_pend[3] & thread3_rsel_m) |
2347
           (pich_wrap_flg[3] & inst_vld_m & thread3_rsel_m) |
2348
           (pich_onebelow_flg[3] & (inst_vld_m & thread3_rsel_m) &
2349
           ((inst_vld_g & thread3_rsel_g) | (inst_vld_w2 & thread3_wsel_w2))) |
2350
           (pich_twobelow_flg[3] & (inst_vld_m & thread3_rsel_m) &
2351
           (inst_vld_g & thread3_rsel_g) & (inst_vld_w2 & thread3_wsel_w2))) &
2352
            pib_trap_en[3] & ~(tlu_flush_pipe_w & thread3_rsel_g) & ~pend_pich_cnt_hld_noqual[3];
2353
 
2354
// modified for timing and bug 4314 and 5017
2355
// added for bug 5436 - Niagara 2.0
2356
 
2357
// removed qualification with ~pend_pich_cnt_hld from the following logics and pushed
2358
// the qulaification to G stage only for software interupt bit15 setting. The above 
2359
// logic stay the same and no precise trap will be taken in the case of b2b valid
2360
// instruction as indicated in bug5436(reopened 9/16/04) 
2361
assign pib_pich_wrap_m[0] =
2362
           // (pib_picl_wrap[0] |
2363
           ((picl_wrap_pend[0] & thread0_rsel_m) |
2364
           (pich_wrap_flg[0] & inst_vld_m & thread0_rsel_m) |
2365
           (pich_onebelow_flg[0] & (inst_vld_m & thread0_rsel_m) &
2366
           ((inst_vld_g & thread0_rsel_g) | (inst_vld_w2 & thread0_wsel_w2))) |
2367
           (pich_twobelow_flg[0] & (inst_vld_m & thread0_rsel_m) &
2368
           (inst_vld_g & thread0_rsel_g) & (inst_vld_w2 & thread0_wsel_w2))) &
2369
           ~(tlu_flush_pipe_w & thread0_rsel_g) ;
2370
assign pib_pich_wrap_m[1] =
2371
           // (pib_picl_wrap[1] |
2372
           ((picl_wrap_pend[1] & thread1_rsel_m) |
2373
           (pich_wrap_flg[1] & inst_vld_m & thread1_rsel_m) |
2374
           (pich_onebelow_flg[1] & (inst_vld_m & thread1_rsel_m) &
2375
           ((inst_vld_g & thread1_rsel_g) | (inst_vld_w2 & thread1_wsel_w2))) |
2376
           (pich_twobelow_flg[1] & (inst_vld_m & thread1_rsel_m) &
2377
           (inst_vld_g & thread1_rsel_g) & (inst_vld_w2 & thread1_wsel_w2))) &
2378
           ~(tlu_flush_pipe_w & thread1_rsel_g) ;
2379
assign pib_pich_wrap_m[2] =
2380
           // (pib_picl_wrap[2] |
2381
           ((picl_wrap_pend[2] & thread2_rsel_m) |
2382
           (pich_wrap_flg[2] & inst_vld_m & thread2_rsel_m) |
2383
           (pich_onebelow_flg[2] & (inst_vld_m & thread2_rsel_m) &
2384
           ((inst_vld_g & thread2_rsel_g) | (inst_vld_w2 & thread2_wsel_w2))) |
2385
           (pich_twobelow_flg[2] & (inst_vld_m & thread2_rsel_m) &
2386
           (inst_vld_g & thread2_rsel_g) & (inst_vld_w2 & thread2_wsel_w2))) &
2387
           ~(tlu_flush_pipe_w & thread2_rsel_g) ;
2388
assign pib_pich_wrap_m[3] =
2389
           // (pib_picl_wrap[3] |
2390
           ((picl_wrap_pend[3] & thread3_rsel_m) |
2391
           (pich_wrap_flg[3] & inst_vld_m & thread3_rsel_m) |
2392
           (pich_onebelow_flg[3] & (inst_vld_m & thread3_rsel_m) &
2393
           ((inst_vld_g & thread3_rsel_g) | (inst_vld_w2 & thread3_wsel_w2))) |
2394
           (pich_twobelow_flg[3] & (inst_vld_m & thread3_rsel_m) &
2395
           (inst_vld_g & thread3_rsel_g) & (inst_vld_w2 & thread3_wsel_w2))) &
2396
           ~(tlu_flush_pipe_w & thread3_rsel_g) ;
2397
/*
2398
assign pib_wrap_m[0] =
2399
           (pib_picl_wrap[0] |
2400
           (pich_wrap_flg[0] & inst_vld_m & thread0_rsel_m) |
2401
           (pich_onebelow_flg[0] & inst_vld_m & (inst_vld_g | inst_vld_w2) &
2402
           thread0_rsel_m & (thread0_wsel_w2 | thread0_rsel_g)) |
2403
           (pich_twobelow_flg[0] & inst_vld_m & inst_vld_g  & inst_vld_w2 &
2404
            thread0_rsel_g & thread0_rsel_m & thread0_wsel_w2)) & pib_trap_en[0] &
2405
            ~(tlu_flush_pipe_w & thread0_rsel_g);
2406
assign pib_wrap_m[1] =
2407
           (pib_picl_wrap[1] |
2408
           (pich_wrap_flg[1] & inst_vld_m & thread1_rsel_m) |
2409
           (pich_onebelow_flg[1] & inst_vld_m & (inst_vld_g | inst_vld_w2) &
2410
           thread1_rsel_m & (thread1_wsel_w2 | thread1_rsel_g)) |
2411
           (pich_twobelow_flg[1] & inst_vld_m & inst_vld_g  & inst_vld_w2 &
2412
            thread1_rsel_g & thread1_rsel_m & thread1_wsel_w2)) & pib_trap_en[1] &
2413
            ~(tlu_flush_pipe_w & thread1_rsel_g);
2414
assign pib_wrap_m[2] =
2415
           (pib_picl_wrap[2] |
2416
           (pich_wrap_flg[2] & inst_vld_m & thread2_rsel_m) |
2417
           (pich_onebelow_flg[2] & inst_vld_m & (inst_vld_g | inst_vld_w2) &
2418
           thread2_rsel_m & (thread2_wsel_w2 | thread2_rsel_g)) |
2419
           (pich_twobelow_flg[2] & inst_vld_m & inst_vld_g  & inst_vld_w2 &
2420
            thread2_rsel_g & thread2_rsel_m & thread2_wsel_w2)) & pib_trap_en[2] &
2421
            ~(tlu_flush_pipe_w & thread2_rsel_g);
2422
assign pib_wrap_m[3] =
2423
           (pib_picl_wrap[3] |
2424
           (pich_wrap_flg[3] & inst_vld_m & thread3_rsel_m) |
2425
           (pich_onebelow_flg[3] & inst_vld_m & (inst_vld_g | inst_vld_w2) &
2426
           thread3_rsel_m & (thread3_wsel_w2 | thread3_rsel_g)) |
2427
           (pich_twobelow_flg[3] & inst_vld_m & inst_vld_g  & inst_vld_w2 &
2428
            thread3_rsel_g & thread3_rsel_m & thread3_wsel_w2)) & pib_trap_en[3] &
2429
            ~(tlu_flush_pipe_w & thread3_rsel_g);
2430
 
2431
// modified for timing and bug 4314
2432
assign pib_pich_wrap_m[0] =
2433
           (pib_picl_wrap[0] |
2434
           (pich_wrap_flg[0] & inst_vld_m & thread0_rsel_m) |
2435
           (pich_onebelow_flg[0] & inst_vld_m & (inst_vld_g | inst_vld_w2) &
2436
           thread0_rsel_m & (thread0_wsel_w2 | thread0_rsel_g)) |
2437
           (pich_twobelow_flg[0] & inst_vld_m & inst_vld_g  & inst_vld_w2 &
2438
            thread0_rsel_g & thread0_rsel_m & thread0_wsel_w2)) &
2439
            ~(tlu_flush_pipe_w & thread0_rsel_g);
2440
assign pib_pich_wrap_m[1] =
2441
           (pib_picl_wrap[1] |
2442
           (pich_wrap_flg[1] & inst_vld_m & thread1_rsel_m) |
2443
           (pich_onebelow_flg[1] & inst_vld_m & (inst_vld_g | inst_vld_w2) &
2444
           thread1_rsel_m & (thread1_wsel_w2 | thread1_rsel_g)) |
2445
           (pich_twobelow_flg[1] & inst_vld_m & inst_vld_g  & inst_vld_w2 &
2446
            thread1_rsel_g & thread1_rsel_m & thread1_wsel_w2)) &
2447
            ~(tlu_flush_pipe_w & thread1_rsel_g);
2448
assign pib_pich_wrap_m[2] =
2449
           (pib_picl_wrap[2] |
2450
           (pich_wrap_flg[2] & inst_vld_m & thread2_rsel_m) |
2451
           (pich_onebelow_flg[2] & inst_vld_m & (inst_vld_g | inst_vld_w2) &
2452
           thread2_rsel_m & (thread2_wsel_w2 | thread2_rsel_g)) |
2453
           (pich_twobelow_flg[2] & inst_vld_m & inst_vld_g  & inst_vld_w2 &
2454
            thread2_rsel_g & thread2_rsel_m & thread2_wsel_w2)) &
2455
            ~(tlu_flush_pipe_w & thread2_rsel_g);
2456
assign pib_pich_wrap_m[3] =
2457
           (pib_picl_wrap[3] |
2458
           (pich_wrap_flg[3] & inst_vld_m & thread3_rsel_m) |
2459
           (pich_onebelow_flg[3] & inst_vld_m & (inst_vld_g | inst_vld_w2) &
2460
           thread3_rsel_m & (thread3_wsel_w2 | thread3_rsel_g)) |
2461
           (pich_twobelow_flg[3] & inst_vld_m & inst_vld_g  & inst_vld_w2 &
2462
            thread3_rsel_g & thread3_rsel_m & thread3_wsel_w2)) &
2463
            ~(tlu_flush_pipe_w & thread3_rsel_g);
2464
//
2465
*/
2466
 
2467
 
2468
wire [3:0] pib_pich_wrap_q;
2469
 
2470 113 albert.wat
dffr_s #(`TLU_THRD_NUM) dffr_pib_pich_wrap (
2471
   .din (pib_pich_wrap_m[`TLU_THRD_NUM-1:0]),
2472
   .q   (pib_pich_wrap_q[`TLU_THRD_NUM-1:0]),
2473 95 fafa1971
   .rst (local_rst),
2474
   .clk (clk),
2475
   .se  (se),
2476 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2477 95 fafa1971
   .so  ()
2478
);
2479
 
2480
// added for the bug 5436 reopened on 9/16/2004 by Samy. The following pushes
2481
// the qualification by hold signal to G stage.So sofint bit15 is set for signaling
2482
// software a overflow has occurred. But the preciese trap will not be taken.
2483
assign pib_pich_wrap[3:0] = pib_pich_wrap_q[3:0] & {4{~pend_pich_cnt_hld}};
2484
 
2485
 
2486
// 
2487
// experiment
2488
/*
2489
assign pich_exu_wrap_e[0] =
2490
       tlu_thread_inst_vld_w2[0]? pich_onebelow_flg[0]: pich_wrap_flg[0];
2491
assign pich_exu_wrap_e[1] =
2492
       tlu_thread_inst_vld_w2[1]? pich_onebelow_flg[1]: pich_wrap_flg[1];
2493
assign pich_exu_wrap_e[2] =
2494
       tlu_thread_inst_vld_w2[2]? pich_onebelow_flg[2]: pich_wrap_flg[2];
2495
assign pich_exu_wrap_e[3] =
2496
       tlu_thread_inst_vld_w2[3]? pich_onebelow_flg[3]: pich_wrap_flg[3];
2497
 
2498
assign pich_wrap_flg_e =
2499
           (tlu_thrd_rsel_e[0]) ? pich_exu_wrap_e[0]:
2500
           (tlu_thrd_rsel_e[1]) ? pich_exu_wrap_e[1]:
2501
           (tlu_thrd_rsel_e[2]) ? pich_exu_wrap_e[2]:
2502
            pich_exu_wrap_e[3];
2503
*/
2504
 
2505 113 albert.wat
dffr_s dffr_pich_wrap_flg_m (
2506 95 fafa1971
   .din (tlu_pic_wrap_e),
2507
   .q   (pich_wrap_flg_m),
2508
   .rst (local_rst),
2509
   .clk (clk),
2510
   .se  (se),
2511 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2512 95 fafa1971
   .so  ()
2513
);
2514
//
2515
// modified for bug 5436 - Niagara 2.0
2516
assign tlu_pich_wrap_flg_m =
2517
           pich_wrap_flg_m & tlu_pic_cnt_en_m;
2518
/*
2519
assign pic_hpstate_priv_e =
2520
           (tlu_thrd_rsel_e[0]) ? tlu_hpstate_priv[0]:
2521
           (tlu_thrd_rsel_e[1]) ? tlu_hpstate_priv[1]:
2522
           (tlu_thrd_rsel_e[2]) ? tlu_hpstate_priv[2]:
2523
            tlu_hpstate_priv[3];
2524
 
2525
assign pic_pstate_priv_e =
2526
           (tlu_thrd_rsel_e[0]) ? tlu_pstate_priv_buf[0]:
2527
           (tlu_thrd_rsel_e[1]) ? tlu_pstate_priv_buf[1]:
2528
           (tlu_thrd_rsel_e[2]) ? tlu_pstate_priv_buf[2]:
2529
            tlu_pstate_priv_buf[3];
2530
 
2531
assign pic_hpstate_enb_e =
2532
           (tlu_thrd_rsel_e[0]) ? tlu_hpstate_enb[0]:
2533
           (tlu_thrd_rsel_e[1]) ? tlu_hpstate_enb[1]:
2534
           (tlu_thrd_rsel_e[2]) ? tlu_hpstate_enb[2]:
2535
            tlu_hpstate_enb[3];
2536
 
2537
assign pic_trap_en_e =
2538
           (tlu_thrd_rsel_e[0]) ? pib_trap_en[0]:
2539
           (tlu_thrd_rsel_e[1]) ? pib_trap_en[1]:
2540
           (tlu_thrd_rsel_e[2]) ? pib_trap_en[2]:
2541
            pib_trap_en[3];
2542
*/
2543
 
2544
// modified for bug 5436 - Niagara 2.0
2545
 
2546
assign pic_cnt_en[0] =
2547
            ((~tlu_hpstate_priv[0] & ~tlu_pstate_priv_buf[0] & tlu_pcr_ut[0]) |
2548
             (~tlu_hpstate_enb[0]  & tlu_hpstate_priv[0] & tlu_pcr_st[0]) |
2549
             (tlu_hpstate_enb[0]   & tlu_pstate_priv_buf[0]  & ~tlu_hpstate_priv[0] &
2550
 //tlu_pcr_st[0])) & pib_trap_en[0]; 
2551
              tlu_pcr_st[0])) ;
2552
assign pic_cnt_en[1] =
2553
            ((~tlu_hpstate_priv[1] & ~tlu_pstate_priv_buf[1] & tlu_pcr_ut[1]) |
2554
             (~tlu_hpstate_enb[1]  & tlu_hpstate_priv[1] & tlu_pcr_st[1]) |
2555
             (tlu_hpstate_enb[1]   & tlu_pstate_priv_buf[1]  & ~tlu_hpstate_priv[1] &
2556
 //tlu_pcr_st[1])) & pib_trap_en[1]; 
2557
              tlu_pcr_st[1])) ;
2558
assign pic_cnt_en[2] =
2559
            ((~tlu_hpstate_priv[2] & ~tlu_pstate_priv_buf[2] & tlu_pcr_ut[2]) |
2560
             (~tlu_hpstate_enb[2]  & tlu_hpstate_priv[2] & tlu_pcr_st[2]) |
2561
             (tlu_hpstate_enb[2]   & tlu_pstate_priv_buf[2]  & ~tlu_hpstate_priv[2] &
2562
 //tlu_pcr_st[2])) & pib_trap_en[2]; 
2563
              tlu_pcr_st[2])) ;
2564
assign pic_cnt_en[3] =
2565
            ((~tlu_hpstate_priv[3] & ~tlu_pstate_priv_buf[3] & tlu_pcr_ut[3]) |
2566
             (~tlu_hpstate_enb[3]  & tlu_hpstate_priv[3] & tlu_pcr_st[3]) |
2567
             (tlu_hpstate_enb[3]   & tlu_pstate_priv_buf[3]  & ~tlu_hpstate_priv[3] &
2568
 //tlu_pcr_st[3])) & pib_trap_en[3]; 
2569
              tlu_pcr_st[3])) ;
2570
 
2571
assign pic_cnt_en_e =
2572
           (tlu_thrd_rsel_e[0]) ? pic_cnt_en[0]:
2573
           (tlu_thrd_rsel_e[1]) ? pic_cnt_en[1]:
2574
           (tlu_thrd_rsel_e[2]) ? pic_cnt_en[2]:
2575
            pic_cnt_en[3];
2576
 
2577
 
2578
/*
2579
assign pic_cnt_en_e =
2580
            ((~pic_hpstate_priv_e & ~pic_pstate_priv_e & pcr_ut_e) |
2581
             (~pic_hpstate_enb_e  & pic_hpstate_priv_e & pcr_st_e) |
2582
             (pic_hpstate_enb_e   & pic_pstate_priv_e  & ~pic_hpstate_priv_e &
2583
              pcr_st_e)) & pic_trap_en_e;
2584
*/
2585
 
2586 113 albert.wat
dffr_s dffr_tlu_pic_cnt_en_m (
2587 95 fafa1971
   .din (pic_cnt_en_e),
2588
   .q   (pic_cnt_en_m),
2589
   .rst (local_rst),
2590
   .clk (clk),
2591
   .se  (se),
2592 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2593 95 fafa1971
   .so  ()
2594
);
2595
 
2596
/**** replaced the following with and-or for better synthesis interms of timing
2597
assign tlu_pich_cnt_hld =
2598
       (thread0_rsel_m) ? pend_pich_cnt_hld[0]:
2599
       (thread1_rsel_m) ? pend_pich_cnt_hld[1]:
2600
       (thread2_rsel_m) ? pend_pich_cnt_hld[2]:
2601
        pend_pich_cnt_hld[3];
2602
************/
2603
 
2604
 
2605
assign tlu_pich_cnt_hld = (thread0_stg_m & pend_pich_cnt_hld_early[0]) |
2606
                          (thread1_stg_m & pend_pich_cnt_hld_early[1]) |
2607
                          (thread2_stg_m & pend_pich_cnt_hld_early[2]) |
2608
                          (thread3_stg_m & pend_pich_cnt_hld_early[3]) ;
2609
 
2610
 
2611
// added the follwoing since we still want to qualify with pib_trap_en for the trap signal going
2612
// to exu, i.e. tlu_pic_cnt_en_m is used to generate tlu_exu_pic_onebelow_m in tlu_misctl.v 
2613
wire pic_trap_en_e =
2614
           (tlu_thrd_rsel_e[0]) ? pib_trap_en[0]:
2615
           (tlu_thrd_rsel_e[1]) ? pib_trap_en[1]:
2616
           (tlu_thrd_rsel_e[2]) ? pib_trap_en[2]:
2617
            pib_trap_en[3];
2618
 
2619
wire pic_trap_en_m;
2620
 
2621 113 albert.wat
dffr_s dffr_pic_trap_en_m (
2622 95 fafa1971
   .din (pic_trap_en_e),
2623
   .q   (pic_trap_en_m),
2624 113 albert.wat
   .rst (local_rst), .clk (clk), .se  (se), `SIMPLY_RISC_SCANIN, .so  ());
2625 95 fafa1971
 
2626
wire tlu_pic_cnt_en_m_prequal = pic_cnt_en_m & pic_trap_en_m;
2627
 
2628
assign tlu_pic_cnt_en_m = tlu_pic_cnt_en_m_prequal & ~tlu_pich_cnt_hld;
2629
 
2630
//
2631
// added for bug 5436 - Niagara 2.0
2632 113 albert.wat
dffr_s dffr_pic_cnt_en_w (
2633 95 fafa1971
   .din (pic_cnt_en_m),
2634
   .q   (pic_cnt_en_w),
2635
   .rst (local_rst),
2636
   .clk (clk),
2637
   .se  (se),
2638 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2639 95 fafa1971
   .so  ()
2640
);
2641
 
2642 113 albert.wat
dffr_s dffr_pic_cnt_en_w2 (
2643 95 fafa1971
   .din (pic_cnt_en_w),
2644
   .q   (pic_cnt_en_w2),
2645
   .rst (local_rst),
2646
   .clk (clk),
2647
   .se  (se),
2648 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2649 95 fafa1971
   .so  ()
2650
);
2651
 
2652
/*
2653
// added for bug 4785
2654
assign tlu_pic_onebelow_e =
2655
           (thread0_rsel_e) ? pich_onebelow_flg[0] :
2656
           (thread1_rsel_e) ? pich_onebelow_flg[1] :
2657
           (thread2_rsel_e) ? pich_onebelow_flg[2] :
2658
           pich_onebelow_flg[3];
2659
 
2660 113 albert.wat
dffr_s dffr_tlu_exu_pic_onebelow_m (
2661 95 fafa1971
   .din (tlu_pic_onebelow_e),
2662
   .q   (tlu_exu_pic_onebelow_m),
2663
   .rst (local_rst),
2664
   .clk (clk),
2665
   .se  (se),
2666 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2667 95 fafa1971
   .so  ()
2668
);
2669
 
2670
assign tlu_pic_twobelow_e =
2671
           (thread0_rsel_e) ? pich_twobelow_flg[0] :
2672
           (thread1_rsel_e) ? pich_twobelow_flg[1] :
2673
           (thread2_rsel_e) ? pich_twobelow_flg[2] :
2674
           pich_twobelow_flg[3];
2675
 
2676 113 albert.wat
dffr_s dffr_tlu_exu_pic_twobelow_m (
2677 95 fafa1971
   .din (tlu_pic_twobelow_e),
2678
   .q   (tlu_exu_pic_twobelow_m),
2679
   .rst (local_rst),
2680
   .clk (clk),
2681
   .se  (se),
2682 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2683 95 fafa1971
   .so  ()
2684
);
2685
*/
2686
//
2687
// added for bug 4395
2688 113 albert.wat
dffr_s dffr_tlu_tcc_inst_w (
2689 95 fafa1971
    .din (exu_tlu_ttype_m[8]),
2690
    .q   (tlu_tcc_inst_w),
2691
    .clk (clk),
2692
    .rst (local_rst),
2693
    .se  (se),
2694 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2695 95 fafa1971
    .so  ()
2696
);
2697
//
2698 113 albert.wat
assign pib_wrap_trap_m = (|pib_wrap_m[`TLU_THRD_NUM-1:0]);
2699 95 fafa1971
//
2700
// modified for bug 4342
2701
// pib wrap precise trap 
2702 113 albert.wat
dffr_s dffr_pib_wrap_trap_nq_g (
2703 95 fafa1971
   .din (pib_wrap_trap_m),
2704
   .q   (pib_wrap_trap_nq_g),
2705
   .rst (local_rst),
2706
   .clk (clk),
2707
   .se  (se),
2708 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2709 95 fafa1971
   .so  ()
2710
);
2711
 
2712
// modified for bug 4916
2713
assign pib_wrap_trap_g =
2714
           pib_wrap_trap_nq_g & ~lsu_tlu_defr_trp_taken_g;
2715
//
2716
// modified for bug 2955
2717
assign tlu_exu_priv_trap_m =
2718
           exu_pib_priv_act_trap_m | exu_tick_npt_priv_act_m |
2719 113 albert.wat
           (|tlz_exu_trap_m[`TLU_THRD_NUM-1:0]) | tlu_pich_wrap_flg_m |
2720 95 fafa1971
           tlu_picl_wrap_flg_m;
2721
// 
2722
// illegal instruction from ffu
2723 113 albert.wat
dffr_s dffr_ffu_ill_inst_uf_g (
2724 95 fafa1971
   .din (ffu_tlu_ill_inst_m),
2725
   .q   (ffu_ill_inst_uf_g),
2726
   .rst (local_rst),
2727
   .clk (clk),
2728
   .se  (se),
2729 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2730 95 fafa1971
   .so  ()
2731
);
2732
 
2733
assign ffu_ill_inst_g = ffu_ill_inst_uf_g & ~inst_ifu_flush_w;
2734
/*
2735 113 albert.wat
dffr_s dffr_lsu_ill_inst_uf_g (
2736 95 fafa1971
   .din (lsu_tlu_ill_inst_m),
2737
   .q   (lsu_ill_inst_uf_g),
2738
   .rst (local_rst),
2739
   .clk (clk),
2740
   .se  (se),
2741 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2742 95 fafa1971
   .so  ()
2743
);
2744
 
2745
assign lsu_ill_inst_g = lsu_ill_inst_uf_g & ~inst_ifu_flush_w;
2746
//
2747
*/
2748
// added for bug 4074 and modified for bug 4715
2749
/*
2750 113 albert.wat
dffr_s dffr_lsu_tlu_defr_trp_taken_w2 (
2751 95 fafa1971
   .din (lsu_tlu_defr_trp_taken_g),
2752
   .q   (lsu_tlu_defr_trp_taken_w2),
2753
   .rst (local_rst),
2754
   .clk (clk),
2755
   .se  (se),
2756 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2757 95 fafa1971
   .so  ()
2758
);
2759
*/
2760
 
2761
assign lsu_defr_trp_taken_w2[0] = lsu_defr_trap_w2 & thread0_wsel_w2;
2762
assign lsu_defr_trp_taken_w2[1] = lsu_defr_trap_w2 & thread1_wsel_w2;
2763
assign lsu_defr_trp_taken_w2[2] = lsu_defr_trap_w2 & thread2_wsel_w2;
2764
assign lsu_defr_trp_taken_w2[3] = lsu_defr_trap_w2 & thread3_wsel_w2;
2765
 
2766
 
2767
// added for the lsu deferred trap - bug 3060
2768
// modified for bug 4074, 4561 and 4916
2769
assign lsu_defr_trap_g = lsu_tlu_defr_trp_taken_g & ~ifu_tlu_flush_fd_w;
2770
// assign lsu_defr_trap_g = lsu_tlu_defr_trp_taken_g; 
2771
 
2772
assign local_lsu_async_ttype_vld_w = lsu_tlu_async_ttype_vld_g;
2773
//
2774
// modified for bug 4443 and 4561
2775
// added for timing
2776 113 albert.wat
dffr_s dffr_lsu_defr_trap_w2 (
2777 95 fafa1971
   .din (lsu_defr_trap_g),
2778
   .q   (lsu_defr_trap_w2),
2779
   .rst (local_rst),
2780
   .clk (clk),
2781
   .se  (se),
2782 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2783 95 fafa1971
   .so  ()
2784
);
2785
//
2786
// privilege action trap of the PIB registers
2787 113 albert.wat
dffr_s dffr_pib_priv_act_trap_g (
2788 95 fafa1971
   .din (pib_priv_act_early_trap_m),
2789
   .q   (pib_priv_act_trap_uf_g),
2790
   .rst (local_rst),
2791
   .clk (clk),
2792
   .se  (se),
2793 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2794 95 fafa1971
   .so  ()
2795
);
2796
//
2797
// added for bug 2133
2798
assign pib_priv_act_trap_g = pib_priv_act_trap_uf_g & ~inst_ifu_flush_w;
2799
//
2800
assign  ifu_ttype_vld_g = ifu_ttype_vld_tmp_g | spu_ill_inst_g | immu_miss_g    |
2801
                          tick_npt_priv_act_g | ffu_ill_inst_g | pib_priv_act_trap_g |
2802
                          htrap_ill_inst_g;
2803
// 
2804
// added and modified for timing fix
2805
assign ifu_ttype_early_vld_m =
2806
             (ifu_ttype_vld_m  | pib_priv_act_early_trap_m |
2807
              spu_ill_inst_m   | tick_npt_priv_act_m | ffu_tlu_ill_inst_m |
2808
              htrap_ill_inst_m);
2809
 
2810
assign  early_dside_trap_g =
2811
            (local_sync_trap_g & ~inst_ifu_flush2_w) |
2812
             va_oor_inst_acc_excp_g | va_oor_data_acc_excp_g;
2813
//
2814
assign  dside_sync_trap_g =
2815
            lsu_ttype_vld_w | early_dside_trap_g;
2816
//
2817
// The sync ttype is being recoded for timing
2818
// Merge with lsu traps.
2819
//
2820 113 albert.wat
mux2ds #(`TSA_TTYPE_WIDTH) mx_local_sync_ttype (
2821
    .in0  (`INST_ACC_EXC),
2822
        .in1  (`DATA_ACC_EXC),
2823 95 fafa1971
    .sel0 (va_oor_inst_acc_excp_g),
2824
    .sel1 (~va_oor_inst_acc_excp_g),
2825 113 albert.wat
    .dout (local_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0])
2826 95 fafa1971
);
2827
 
2828
// Need 9b comparator.
2829
// assign dside_higher_priority = (dside_sync_ttype_g[8:0] > exu_ttype_g[8:0]);
2830
assign local_higher_ttype_flg =
2831 113 albert.wat
           (local_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0] >
2832
            exu_ttype_g[`TSA_TTYPE_WIDTH-1:0]);
2833 95 fafa1971
 
2834
// added for bug 3977
2835 113 albert.wat
dffr_s dffr_exu_ue_trap_g (
2836 95 fafa1971
   .din (exu_tlu_ue_trap_m),
2837
   .q   (exu_ue_trap_g),
2838
   .rst (local_rst),
2839
   .clk (clk),
2840
   .se  (se),
2841 113 albert.wat
   `SIMPLY_RISC_SCANIN,
2842 95 fafa1971
   .so  ()
2843
);
2844
assign exu_higher_pri_g =
2845
           exu_ue_trap_g & exu_ttype_vld_g & ~immu_miss_g;
2846
 
2847
// Is the prioritization needed or is this handled among the units themselves ?
2848
// modified for bug 3977
2849
assign  priority_trap_sel0 =
2850 113 albert.wat
            ifu_ttype_vld_g & ~((|tlz_trap_g[`TLU_THRD_NUM-1:0]) |
2851 95 fafa1971
            lsu_defr_trap_g | exu_higher_pri_g);
2852
//
2853
// modified for support to lsu deferred traps
2854
// modified for bug 3977
2855
assign  priority_trap_sel1 =
2856 113 albert.wat
            ~((|tlz_trap_g[`TLU_THRD_NUM-1:0]) | lsu_defr_trap_g) &
2857 95 fafa1971
            ~(ifu_ttype_vld_g & ~exu_higher_pri_g) &
2858
             ((exu_ttype_vld_g & ~early_dside_trap_g) |
2859
                         ((exu_ttype_vld_g &  early_dside_trap_g) & ~local_higher_ttype_flg));
2860
// 
2861
// modified for bug 3634
2862
assign  priority_trap_sel2 = ~(priority_trap_sel0 | priority_trap_sel1);
2863
//
2864
// recoded for timing
2865
// Prioritized ttype for thread available.
2866
/*
2867
mux4ds #(9) finaltt_sel (
2868
    .in0    ({2'b00,`TLZ_TRAP}),
2869
    .in1    (ifu_ttype_g[8:0]),
2870
        .in2    (exu_ttype_g[8:0]),
2871
        .in3    (dside_sync_ttype_g[8:0]),
2872
    .sel0   (|tlz_trap_g[`TLU_THRD_NUM-1:0]),
2873
    .sel1   (priority_trap_sel0),
2874
        .sel2   (priority_trap_sel1),
2875
        .sel3   (priority_trap_sel2),
2876
    .dout   (sync_ttype_g[8:0])
2877
);
2878
*/
2879
//
2880
// modified for bug 3634
2881
// modified for bug 3977
2882 113 albert.wat
mux3ds #(`TSA_TTYPE_WIDTH) mx_early_sync_ttype (
2883 95 fafa1971
//     .in0    ({2'b00,`TLZ_TRAP}),
2884
    .in0    (ifu_ttype_g[8:0]),
2885
        .in1    (exu_ttype_g[8:0]),
2886
        .in2    (local_sync_ttype_g[8:0]),
2887
    .sel0   (priority_trap_sel0),
2888
        .sel1   (priority_trap_sel1),
2889
        .sel2   (priority_trap_sel2),
2890 113 albert.wat
    .dout   (early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0])
2891 95 fafa1971
);
2892
//
2893
// added for timing 
2894 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH) dff_early_sync_ttype_w2 (
2895
    .din (early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
2896
    .q   (early_sync_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
2897 95 fafa1971
    .clk (clk),
2898
    .se  (se),
2899 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2900 95 fafa1971
    .so  ()
2901
);
2902
//
2903
// Now pend Div and Spill/Fill traps if necessary. These traps are always pended
2904
// even if there is no concurrent synchronous trap. They are pended by thread.
2905
// Include fp traps
2906
// modified for bug 4857
2907
assign  sync_trap_taken_g =
2908
        ((ifu_ttype_vld_g | exu_ttype_vld_g | lsu_tlu_ttype_vld_m2 | early_dside_trap_g |
2909 113 albert.wat
     (|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & inst_vld_g) |
2910 95 fafa1971
      intrpt_taken | swint_taken | lsu_defr_trap_g;
2911
     // (|tlz_trap_g[`TLU_THRD_NUM-1:0])) & inst_vld_g) | intrpt_taken | swint_taken |
2912
     //  lsu_defr_trap_g | pib_wrap_trap_g; 
2913
// 
2914
// added for timing
2915 113 albert.wat
dff_s dff_sync_trap_taken_w2 (
2916 95 fafa1971
    .din (sync_trap_taken_g),
2917
        .q   (sync_trap_taken_w2),
2918
    .clk (clk),
2919
    .se  (se),
2920 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2921 95 fafa1971
    .so  ()
2922
);
2923
//
2924
// added for timing fix 
2925
// modified for bug 3653, bug 4758 and bug 5169
2926
assign  sync_trap_taken_m =
2927
         (exu_tlu_va_oor_jl_ret_m | exu_tlu_ttype_vld_m |
2928 113 albert.wat
      ifu_ttype_early_vld_m | (|tlz_trap_m[`TLU_THRD_NUM-1:0]) | true_hscpd_dacc_excpt_m |
2929 95 fafa1971
      true_qtail_dacc_excpt_m | dmmu_va_oor_m | exu_tlu_va_oor_jl_ret_m |
2930
      pib_wrap_trap_m | ifu_swint_m | ifu_hwint_m | ifu_rstint_m) & inst_vld_m;
2931
/*
2932
assign  sync_trap_taken_m =
2933
        ((exu_tlu_va_oor_jl_ret_m | exu_tlu_ttype_vld_m |
2934
      ifu_ttype_early_vld_m | (|tlz_trap_m[`TLU_THRD_NUM-1:0]) | true_hscpd_dacc_excpt_m |
2935
      true_qtail_dacc_excpt_m | dmmu_va_oor_m | exu_tlu_va_oor_jl_ret_m) &
2936
      inst_vld_m) | pib_wrap_trap_m | ifu_swint_m | ifu_hwint_m | ifu_rstint_m;
2937
*/
2938
 
2939
assign fp_trap_thrd0 = ~ffu_ifu_tid_w2[1] & ~ffu_ifu_tid_w2[0];
2940
assign fp_trap_thrd1 = ~ffu_ifu_tid_w2[1] &  ffu_ifu_tid_w2[0];
2941
assign fp_trap_thrd2 =  ffu_ifu_tid_w2[1] & ~ffu_ifu_tid_w2[0];
2942
assign fp_trap_thrd3 =  ffu_ifu_tid_w2[1] &  ffu_ifu_tid_w2[0];
2943
 
2944
// assign div_zero_thrd0 = ~exu_tlu_div_tid[1] & ~exu_tlu_div_tid[0];
2945
// assign div_zero_thrd1 = ~exu_tlu_div_tid[1] &  exu_tlu_div_tid[0];
2946
// assign div_zero_thrd2 =  exu_tlu_div_tid[1] & ~exu_tlu_div_tid[0];
2947
// assign div_zero_thrd3 =  exu_tlu_div_tid[1] &  exu_tlu_div_tid[0];
2948
 
2949
assign spill_thrd0 = ~exu_tlu_spill_tid[1] & ~exu_tlu_spill_tid[0];
2950
assign spill_thrd1 = ~exu_tlu_spill_tid[1] &  exu_tlu_spill_tid[0];
2951
assign spill_thrd2 =  exu_tlu_spill_tid[1] & ~exu_tlu_spill_tid[0];
2952
assign spill_thrd3 =  exu_tlu_spill_tid[1] &  exu_tlu_spill_tid[0];
2953
// 
2954
// added for bug 3499
2955 113 albert.wat
dff_s #(`TLU_THRD_NUM) dff_cwp_en_thrd_reset (
2956 95 fafa1971
    .din ({pend_to_thrd3_reset, pend_to_thrd2_reset,
2957
           pend_to_thrd1_reset, pend_to_thrd0_reset}),
2958 113 albert.wat
    .q   (cwp_en_thrd_reset[`TLU_THRD_NUM-1:0]),
2959 95 fafa1971
    .clk (clk),
2960
    .se  (se),
2961 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2962 95 fafa1971
    .so  ()
2963
);
2964
 
2965 113 albert.wat
dffre_s dffre_trap_cwp0_enb (
2966 95 fafa1971
    .din (spill_thrd0),
2967
    .q   (trap_cwp_enb[0]),
2968
    .rst (cwp_en_thrd_reset[0]),
2969
    .en  (exu_tlu_spill & spill_thrd0),
2970
    .clk (clk),
2971
    .se  (se),
2972 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2973 95 fafa1971
    .so  ()
2974
);
2975
 
2976 113 albert.wat
dffre_s dffre_trap_cwp1_enb (
2977 95 fafa1971
    .din (spill_thrd1),
2978
    .q   (trap_cwp_enb[1]),
2979
    .rst (cwp_en_thrd_reset[1]),
2980
    .en  (exu_tlu_spill & spill_thrd1),
2981
    .clk (clk),
2982
    .se  (se),
2983 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2984 95 fafa1971
    .so  ()
2985
);
2986
 
2987 113 albert.wat
dffre_s dffre_trap_cwp2_enb (
2988 95 fafa1971
    .din (spill_thrd2),
2989
    .q   (trap_cwp_enb[2]),
2990
    .rst (cwp_en_thrd_reset[2]),
2991
    .en  (exu_tlu_spill & spill_thrd2),
2992
    .clk (clk),
2993
    .se  (se),
2994 113 albert.wat
    `SIMPLY_RISC_SCANIN,
2995 95 fafa1971
    .so  ()
2996
);
2997
 
2998 113 albert.wat
dffre_s dffre_trap_cwp3_enb (
2999 95 fafa1971
    .din (spill_thrd3),
3000
    .q   (trap_cwp_enb[3]),
3001
    .rst (cwp_en_thrd_reset[3]),
3002
    .en  (exu_tlu_spill & spill_thrd3),
3003
    .clk (clk),
3004
    .se  (se),
3005 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3006 95 fafa1971
    .so  ()
3007
);
3008
 
3009 113 albert.wat
assign tlu_trap_cwp_en[`TLU_THRD_NUM-1:0] = ~(trap_cwp_enb[`TLU_THRD_NUM-1:0]);
3010 95 fafa1971
 
3011
//
3012
// added for asynchronize dmmu traps (correctable parity error)
3013
assign dmmu_async_thrd0 = ~lsu_tlu_async_tid_g[1] & ~lsu_tlu_async_tid_g[0];
3014
assign dmmu_async_thrd1 = ~lsu_tlu_async_tid_g[1] &  lsu_tlu_async_tid_g[0];
3015
assign dmmu_async_thrd2 =  lsu_tlu_async_tid_g[1] & ~lsu_tlu_async_tid_g[0];
3016
assign dmmu_async_thrd3 =  lsu_tlu_async_tid_g[1] &  lsu_tlu_async_tid_g[0];
3017
//
3018
// modified for bug 4074
3019
assign lsu_async_vld_en_g[0] =
3020
//            local_lsu_async_ttype_vld_w & dmmu_async_thrd0 & ~lsu_tlu_defr_trp_taken_g;
3021
            local_lsu_async_ttype_vld_w & dmmu_async_thrd0 & ~lsu_defr_trp_taken_w2[0];
3022
assign lsu_async_vld_en_g[1] =
3023
//            local_lsu_async_ttype_vld_w & dmmu_async_thrd1 & ~lsu_tlu_defr_trp_taken_g;
3024
           local_lsu_async_ttype_vld_w & dmmu_async_thrd1 & ~lsu_defr_trp_taken_w2[1];
3025
assign lsu_async_vld_en_g[2] =
3026
//            local_lsu_async_ttype_vld_w & dmmu_async_thrd2 & ~lsu_tlu_defr_trp_taken_g;
3027
           local_lsu_async_ttype_vld_w & dmmu_async_thrd2 & ~lsu_defr_trp_taken_w2[2];
3028
assign lsu_async_vld_en_g[3] =
3029
//           local_lsu_async_ttype_vld_w & dmmu_async_thrd3 & ~lsu_tlu_defr_trp_taken_g;
3030
           local_lsu_async_ttype_vld_w & dmmu_async_thrd3 & ~lsu_defr_trp_taken_w2[3];
3031
//
3032 113 albert.wat
dffre_s dffre_lsu_async_vld_en_w2_0 (
3033 95 fafa1971
    .din (lsu_async_vld_en_g[0]),
3034
    .q   (lsu_async_vld_en_w2[0]),
3035
    .rst (pend_to_thrd0_reset),
3036
    .en  (lsu_async_vld_en_g[0]),
3037
    .clk (clk),
3038
    .se  (se),
3039 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3040 95 fafa1971
    .so  ()
3041
);
3042 113 albert.wat
dffre_s dffre_lsu_async_vld_en_w2_1 (
3043 95 fafa1971
    .din (lsu_async_vld_en_g[1]),
3044
    .q   (lsu_async_vld_en_w2[1]),
3045
    .rst (pend_to_thrd1_reset),
3046
    .en  (lsu_async_vld_en_g[1]),
3047
    .clk (clk),
3048
    .se  (se),
3049 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3050 95 fafa1971
    .so  ()
3051
);
3052 113 albert.wat
dffre_s dffre_lsu_async_vld_en_w2_2 (
3053 95 fafa1971
    .din (lsu_async_vld_en_g[2]),
3054
    .q   (lsu_async_vld_en_w2[2]),
3055
    .rst (pend_to_thrd2_reset),
3056
    .en  (lsu_async_vld_en_g[2]),
3057
    .clk (clk),
3058
    .se  (se),
3059 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3060 95 fafa1971
    .so  ()
3061
);
3062 113 albert.wat
dffre_s dffre_lsu_async_vld_en_w2_3 (
3063 95 fafa1971
    .din (lsu_async_vld_en_g[3]),
3064
    .q   (lsu_async_vld_en_w2[3]),
3065
    .rst (pend_to_thrd3_reset),
3066
    .en  (lsu_async_vld_en_g[3]),
3067
    .clk (clk),
3068
    .se  (se),
3069 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3070 95 fafa1971
    .so  ()
3071
);
3072
//
3073
// assign trap type base on information send
3074 113 albert.wat
assign dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0] =
3075 95 fafa1971
           {2'b0, lsu_tlu_async_ttype_g[6:0]};
3076
// 
3077
// derived the spill ttype
3078 113 albert.wat
assign exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] =
3079 95 fafa1971
           {3'b010,exu_tlu_spill_other,exu_tlu_spill_wtype[2:0], 2'b00};
3080
//
3081
// derived ffu_asynchronous ttype
3082
// modified for bug 4084 - new ffu asynchronous trap type: 0x29
3083 113 albert.wat
assign ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] =
3084 95 fafa1971
           (ffu_tlu_trap_ue) ? 9'h029:
3085
               ({7'b0001000, ffu_tlu_trap_other, ffu_tlu_trap_ieee754});
3086
//
3087
//
3088
// modified for bug 4084 - new ffu_tlu_trap_ue 
3089 113 albert.wat
assign pend_ttype0[`TSA_TTYPE_WIDTH-1:0] =
3090 95 fafa1971
                (exu_tlu_spill & spill_thrd0) ?
3091 113 albert.wat
         exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] :
3092 95 fafa1971
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd0) ?
3093 113 albert.wat
           ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] :
3094
           dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0]);
3095 95 fafa1971
 
3096
// always flop if selected for thread.
3097
// THREAD0
3098
// added support for dmmu_async_traps
3099
// modified for bug 4084 - new ffu_tlu_trap_ue 
3100
assign pend_to_thrd0_en =
3101
               (exu_tlu_spill & spill_thrd0) |
3102
                  ((ffu_tlu_trap_ieee754 | ffu_tlu_trap_other | ffu_tlu_trap_ue) & fp_trap_thrd0) |
3103
           (lsu_async_vld_en_g[0] & ~lsu_async_vld_en_w2[0]) |
3104
                        cwp_cmplt0;                             // cwp completion always pended.
3105
//
3106
// added for bug 5436 - Niagara 2.0
3107
assign pend_pich_cnt_adj[0] =
3108
              ((exu_tlu_spill & spill_thrd0) |
3109
                  ((ffu_tlu_trap_ieee754 | ffu_tlu_trap_other | ffu_tlu_trap_ue) & fp_trap_thrd0) |
3110
           (lsu_async_vld_en_g[0] & ~lsu_async_vld_en_w2[0])) & pic_cnt_en[0];
3111
 
3112
// If there is no sync trap in a cycle, then the pending trap is taken.
3113
assign  pend_to_thrd0_reset =
3114
        local_rst | pending_thrd0_event_taken;
3115
 
3116
// Choose pending traps in round-robin order.
3117
tlu_rrobin_picker       ptrap_rrobin      (
3118
                .events         ({pending_trap3,pending_trap2,pending_trap1,pending_trap0}),
3119
                .pick_one_hot   (pending_trap_sel[3:0]),
3120
        // 
3121
        // this siganl was modified to abide to the Niagara reset methodology
3122
                        .tlu_rst_l              (tlu_rst_l),
3123
                .clk            (clk)
3124
        );
3125
 
3126
// modified to arbitrate between wsr instruction and asynchronous events
3127
// due to there is only one write port to tsa
3128
// also modified for bug 1672
3129
// modified for bug 3827
3130
assign pending_thrd0_event_taken =
3131
            pending_trap_sel[0] & ~(sync_trap_taken_g | dnrtry_inst_g |
3132
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[0] | (tlu_gl_rw_g & wsr_inst_g));
3133
 
3134 113 albert.wat
dffre_s #(12) dffre_pendthrd0 (
3135 95 fafa1971
    .din ({pend_to_thrd0_en,pend_ttype0[8:0],cwp_cmplt0,exu_tlu_cwp_retry}),
3136
        .q   ({pending_trap0,pending_ttype0[8:0],cwp_cmplt0_pending,cwp_retry0}),
3137
    .rst (pend_to_thrd0_reset),
3138
    .en  (pend_to_thrd0_en),
3139
    .clk (clk),
3140
    .se  (se),
3141 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3142 95 fafa1971
    .so  ()
3143
);
3144
// THREAD1
3145
// added support for dmmu_async_traps
3146
// modified for bug 4084 - new ffu_tlu_trap_ue 
3147
assign pend_to_thrd1_en =
3148
               (exu_tlu_spill & spill_thrd1) |
3149
                  ((ffu_tlu_trap_ieee754 | ffu_tlu_trap_other | ffu_tlu_trap_ue) & fp_trap_thrd1) |
3150
           (lsu_async_vld_en_g[1] & ~lsu_async_vld_en_w2[1]) |
3151
                        cwp_cmplt1;                             // cwp completion always pended.
3152
//
3153
// added for bug 5436 - Niagara 2.0
3154
assign pend_pich_cnt_adj[1] =
3155
              ((exu_tlu_spill & spill_thrd1) |
3156
                  ((ffu_tlu_trap_ieee754 | ffu_tlu_trap_other | ffu_tlu_trap_ue) & fp_trap_thrd1) |
3157
           (lsu_async_vld_en_g[1] & ~lsu_async_vld_en_w2[1])) & pic_cnt_en[1];
3158
 
3159
assign  pend_to_thrd1_reset =
3160
        local_rst | pending_thrd1_event_taken;
3161
 
3162
// modified to arbitrate between wsr instruction and asynchronous events
3163
// due to there is only one write port to tsa
3164
//
3165
// modified for bug 3827
3166
assign pending_thrd1_event_taken =
3167
            pending_trap_sel[1] & ~(sync_trap_taken_g | dnrtry_inst_g |
3168
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[1] | (tlu_gl_rw_g & wsr_inst_g));
3169
 
3170
//
3171
// modified for bug 4084 - new ffu_tlu_trap_ue 
3172 113 albert.wat
assign pend_ttype1[`TSA_TTYPE_WIDTH-1:0] =
3173 95 fafa1971
                (exu_tlu_spill & spill_thrd1) ?
3174 113 albert.wat
         exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] :
3175 95 fafa1971
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd1) ?
3176 113 albert.wat
           ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] :
3177
           dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0]);
3178 95 fafa1971
 
3179 113 albert.wat
dffre_s #(12) dffre_pendthrd1 (
3180 95 fafa1971
    .din ({pend_to_thrd1_en,pend_ttype1[8:0],cwp_cmplt1,exu_tlu_cwp_retry}),
3181
        .q   ({pending_trap1,pending_ttype1[8:0],cwp_cmplt1_pending,cwp_retry1}),
3182
    .rst (pend_to_thrd1_reset),
3183
    .en  (pend_to_thrd1_en),
3184
    .clk (clk),
3185
    .se  (se),
3186 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3187 95 fafa1971
    .so  ()
3188
);
3189
 
3190
// THREAD2
3191
// added support for dmmu_async_traps
3192
// modified for bug 4084 - new ffu_tlu_trap_ue 
3193
assign pend_to_thrd2_en =
3194
               (exu_tlu_spill & spill_thrd2) |
3195
                  ((ffu_tlu_trap_ieee754 | ffu_tlu_trap_other | ffu_tlu_trap_ue) & fp_trap_thrd2) |
3196
           (lsu_async_vld_en_g[2] & ~lsu_async_vld_en_w2[2]) |
3197
                        cwp_cmplt2;                             // cwp completion always pended.
3198
//
3199
// added for bug 5436 - Niagara 2.0
3200
assign pend_pich_cnt_adj[2] =
3201
              ((exu_tlu_spill & spill_thrd2) |
3202
                  ((ffu_tlu_trap_ieee754 | ffu_tlu_trap_other | ffu_tlu_trap_ue) & fp_trap_thrd2) |
3203
           (lsu_async_vld_en_g[2] & ~lsu_async_vld_en_w2[2])) & pic_cnt_en[2];
3204
 
3205
assign  pend_to_thrd2_reset =
3206
        local_rst | pending_thrd2_event_taken;
3207
 
3208
// modified to arbitrate between wsr instruction and asynchronous events
3209
// due to there is only one write port to tsa
3210
//
3211
// modified for bug 3827
3212
assign pending_thrd2_event_taken =
3213
            pending_trap_sel[2] & ~(sync_trap_taken_g | dnrtry_inst_g |
3214
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[2] | (tlu_gl_rw_g & wsr_inst_g));
3215
 
3216
//
3217
// modified for bug 4084 - new ffu_tlu_trap_ue
3218 113 albert.wat
assign pend_ttype2[`TSA_TTYPE_WIDTH-1:0] =
3219 95 fafa1971
                (exu_tlu_spill & spill_thrd2) ?
3220 113 albert.wat
         exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] :
3221 95 fafa1971
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd2) ?
3222 113 albert.wat
           ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] :
3223
           dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0]);
3224 95 fafa1971
 
3225 113 albert.wat
dffre_s #(12) dffre_pendthrd2 (
3226 95 fafa1971
    .din ({pend_to_thrd2_en,pend_ttype2[8:0],cwp_cmplt2,exu_tlu_cwp_retry}),
3227
        .q   ({pending_trap2,pending_ttype2[8:0],cwp_cmplt2_pending,cwp_retry2}),
3228
    .rst (pend_to_thrd2_reset),
3229
    .en  (pend_to_thrd2_en),
3230
    .clk (clk),
3231
    .se  (se),
3232 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3233 95 fafa1971
    .so  ()
3234
);
3235
 
3236
// THREAD3
3237
// added support for dmmu_async_traps
3238
// modified for bug 4084 - new ffu_tlu_trap_ue 
3239
assign pend_to_thrd3_en =
3240
                   (exu_tlu_spill & spill_thrd3) |
3241
                  ((ffu_tlu_trap_ieee754 | ffu_tlu_trap_other | ffu_tlu_trap_ue) & fp_trap_thrd3) |
3242
           (lsu_async_vld_en_g[3] & ~lsu_async_vld_en_w2[3]) |
3243
                        cwp_cmplt3;                             // cwp completion always pended.
3244
//
3245
// added for bug 5436 - Niagara 2.0
3246
assign pend_pich_cnt_adj[3] =
3247
              ((exu_tlu_spill & spill_thrd3) |
3248
                  ((ffu_tlu_trap_ieee754 | ffu_tlu_trap_other | ffu_tlu_trap_ue) & fp_trap_thrd3) |
3249
           (lsu_async_vld_en_g[3] & ~lsu_async_vld_en_w2[3])) & pic_cnt_en[3];
3250
 
3251
assign  pend_to_thrd3_reset =
3252
        local_rst |     pending_thrd3_event_taken;
3253
 
3254
// modified to arbitrate between wsr instruction and asynchronous events
3255
// due to there is only one write port to tsa
3256
// modified for bug 3827
3257
assign pending_thrd3_event_taken =
3258
            pending_trap_sel[3] & ~(sync_trap_taken_g | dnrtry_inst_g |
3259
            tsa_wr_tid_sel_g | ifu_thrd_flush_w[3] | (tlu_gl_rw_g & wsr_inst_g));
3260
 
3261
//
3262 113 albert.wat
assign pend_ttype3[`TSA_TTYPE_WIDTH-1:0] =
3263 95 fafa1971
                (exu_tlu_spill & spill_thrd3) ?
3264 113 albert.wat
         exu_spill_ttype[`TSA_TTYPE_WIDTH-1:0] :
3265 95 fafa1971
                (((ffu_tlu_trap_other | ffu_tlu_trap_ieee754 | ffu_tlu_trap_ue) & fp_trap_thrd3) ?
3266 113 albert.wat
           ffu_async_ttype[`TSA_TTYPE_WIDTH-1:0] :
3267
           dmmu_async_ttype[`TSA_TTYPE_WIDTH-1:0]);
3268 95 fafa1971
//
3269 113 albert.wat
dffre_s #(12) dffre_pendthrd3 (
3270 95 fafa1971
    .din ({pend_to_thrd3_en,pend_ttype3[8:0],cwp_cmplt3,exu_tlu_cwp_retry}),
3271
        .q   ({pending_trap3,pending_ttype3[8:0],cwp_cmplt3_pending,cwp_retry3}),
3272
    .rst (pend_to_thrd3_reset),
3273
    .en  (pend_to_thrd3_en),
3274
    .clk (clk),
3275
    .se  (se),
3276 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3277 95 fafa1971
    .so  ()
3278
);
3279
//
3280
// added for bug 5436 - Niagara 2.0
3281
//assign pich_cnt_hld_rst[`TLU_THRD_NUM-1:0] = 
3282
//           (thread_inst_vld_w2[`TLU_THRD_NUM-1:0] & {4{pic_cnt_en_w2}} |
3283
//           {4{local_rst}});  
3284
 
3285
// fix for 5436 for reopend bugs(9/8/2004) related to flushed inst reseting the hold
3286
// and b2b valid instruction; the 1st one reseting the hold, but the 2nd not incrementing
3287
// since the hold was not reset early to allow the 2nd inst to incr_pich.
3288
 
3289
assign pich_cnt_hld_rst_g[3:0] =
3290
                        (thread_inst_vld_g[3:0] & {4{pic_cnt_en_w}}) &
3291
                        {4{~(lsu_ttype_vld_w | tlu_flush_all_w)}};
3292
 
3293
 
3294 113 albert.wat
dff_s #(4) dff_pich_cnt_hld_rst_g (
3295 95 fafa1971
    .din (pich_cnt_hld_rst_g[3:0]),
3296
    .q   (pich_cnt_hld_rst_w2[3:0]),
3297
    .clk (clk),
3298
    .se  (se),
3299 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3300 95 fafa1971
    .so  ()
3301
);
3302
 
3303
 
3304
assign pend_pich_cnt_hld_early[3:0] = pend_pich_cnt_hld_q[3:0] & ~pich_cnt_hld_rst_w2[3:0];
3305
 
3306
assign pend_pich_cnt_hld[3:0] = pend_pich_cnt_hld_early[3:0];
3307
 
3308
// following is used in pib_wrap_m logic as per bug5436(reopened 9/17/04).
3309
assign pend_pich_cnt_hld_noqual[3:0] = pend_pich_cnt_hld_q[3:0];
3310
 
3311 113 albert.wat
dffre_s dffre_pend_pich_cnt_adj_0 (
3312 95 fafa1971
    .din (pend_pich_cnt_adj[0]),
3313
        .q   (pend_pich_cnt_hld_q[0]),
3314
    .rst (local_rst | pich_cnt_hld_rst_w2[0]),
3315
    .en  (pend_pich_cnt_adj[0]),
3316
    .clk (clk),
3317
    .se  (se),
3318 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3319 95 fafa1971
    .so  ()
3320
);
3321
 
3322 113 albert.wat
dffre_s dffre_pend_pich_cnt_adj_1 (
3323 95 fafa1971
    .din (pend_pich_cnt_adj[1]),
3324
        .q   (pend_pich_cnt_hld_q[1]),
3325
    .rst (local_rst | pich_cnt_hld_rst_w2[1]),
3326
    .en  (pend_pich_cnt_adj[1]),
3327
    .clk (clk),
3328
    .se  (se),
3329 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3330 95 fafa1971
    .so  ()
3331
);
3332
 
3333 113 albert.wat
dffre_s dffre_pend_pich_cnt_adj_2 (
3334 95 fafa1971
    .din (pend_pich_cnt_adj[2]),
3335
        .q   (pend_pich_cnt_hld_q[2]),
3336
    .rst (local_rst | pich_cnt_hld_rst_w2[2]),
3337
    .en  (pend_pich_cnt_adj[2]),
3338
    .clk (clk),
3339
    .se  (se),
3340 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3341 95 fafa1971
    .so  ()
3342
);
3343
 
3344 113 albert.wat
dffre_s dffre_pend_pich_cnt_adj_3 (
3345 95 fafa1971
    .din (pend_pich_cnt_adj[3]),
3346
        .q   (pend_pich_cnt_hld_q[3]),
3347
    .rst (local_rst | pich_cnt_hld_rst_w2[3]),
3348
    .en  (pend_pich_cnt_adj[3]),
3349
    .clk (clk),
3350
    .se  (se),
3351 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3352 95 fafa1971
    .so  ()
3353
);
3354
 
3355
 
3356
assign  trap_taken_g =  thrd0_traps | thrd1_traps | thrd2_traps | thrd3_traps;
3357
// 
3358
// added for timing 
3359 113 albert.wat
dff_s dff_trap_taken_w2 (
3360 95 fafa1971
    .din (trap_taken_g),
3361
    .q   (trap_taken_w2),
3362
    .clk (clk),
3363
    .se  (se),
3364 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3365 95 fafa1971
    .so  ()
3366
);
3367
// Selection of traps should be round-robin.
3368
assign  trap_tid_g[1:0] =
3369
    // lsu_defr_trap_g ? thrid_w2[1:0] :
3370
        ((sync_trap_taken_g) | (dnrtry_inst_g & cwp_fastcmplt_g))  ? thrid_g[1:0] :
3371
                        (pending_trap_sel[0] ? 2'b00 :
3372
                                (pending_trap_sel[1] ? 2'b01 :
3373
                                        (pending_trap_sel[2] ? 2'b10 : 2'b11)));
3374
 
3375
assign pend_trap_tid_g[1:0] =
3376
               pending_trap_sel[0] ? 2'b00 :
3377
                       (pending_trap_sel[1] ? 2'b01 :
3378
                               (pending_trap_sel[2] ? 2'b10 :
3379
                        2'b11));
3380
 
3381 113 albert.wat
dff_s #(2) dff_pend_trap_tid_w2 (
3382 95 fafa1971
    .din (pend_trap_tid_g[1:0]),
3383
    .q   (pend_trap_tid_w2[1:0]),
3384
    .clk (clk),
3385
    .se  (se),
3386 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3387 95 fafa1971
    .so  ()
3388
);
3389
 
3390
 
3391
// Assume fixed priority for now. Should change to round-robin selection !!!
3392
 
3393
// modified for bug 1806
3394
// modified to support lsu deferred traps - modified for timing
3395
// modified for bug 4640 and 5127
3396
//
3397
assign  reset_sel_g =
3398
            rstint_g | (sir_inst_g & ~(lsu_defr_trap_g | pib_wrap_trap_g |
3399 113 albert.wat
            (|tlz_trap_g[`TLU_THRD_NUM-1:0]))) | rst_tri_en;
3400 95 fafa1971
            // rstint_g | (sir_inst_g & ~lsu_defr_trap_g) | rst_tri_en;
3401
//
3402
// added for timing
3403 113 albert.wat
dffr_s dffr_reset_sel_w2 (
3404 95 fafa1971
   .din (reset_sel_g),
3405
   .q   (reset_sel_w2),
3406
   .rst (local_rst),
3407
   .clk (clk),
3408
   .se  (se),
3409 113 albert.wat
   `SIMPLY_RISC_SCANIN,
3410 95 fafa1971
   .so  ()
3411
);
3412
// 
3413
// modified for timing
3414
// assign       reset_defr_id_g[6:0] =
3415
assign  reset_id_g[2:0] =
3416
local_rst ? 3'b001 :
3417
        rstint_g ? rstid_g[2:0] :
3418
                sir_inst_g ? 3'b100 :
3419
                3'bxxx;
3420
 
3421
// recoded for timing
3422
//
3423
// construct the tba_ttype to determine the tba 
3424
// the trap is hypervisor or supervisor traps
3425
// modified for bug 3634 and timing
3426
 
3427
assign tba_ttype_sel_w2 =
3428
           final_ttype_sel_w2[0] | (hyper_wdr_trap_w2 & ~lsu_defr_trap_w2);
3429
 
3430 113 albert.wat
mux2ds #(`TSA_TTYPE_WIDTH) mx_tba_ttype_w2 (
3431 95 fafa1971
    .sel0 (tba_ttype_sel_w2),
3432
    .sel1 (~tba_ttype_sel_w2),
3433 113 albert.wat
    .in0  ({2'b0,rst_hwdr_ttype_w2[`TSA_TTYPE_WIDTH-3:0]}),
3434
    .in1  (final_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3435
    .dout (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0])
3436 95 fafa1971
);
3437
/*
3438
assign tba_ttype_sel_g[0] =
3439
               (rstint_g | rst_tri_en | ((hwint_g | swint_g | hyper_wdr_trap |
3440
               (|tlz_trap_g[`TLU_THRD_NUM-1:0] | sir_inst_g) | pib_wrap_trap_g) &
3441
                inst_vld_g & ~lsu_defr_trap_g);
3442
assign tba_ttype_sel_g[1] =
3443
           (((ifu_ttype_vld_g |  exu_ttype_vld_g | va_oor_inst_acc_excp_g) |
3444
            (local_sync_trap_g & ~(lsu_tlu_priv_action_g | misalign_addr_ldst_atm_g))) &
3445
           ~(reset_sel_g | hwint_g | swint_g | hyper_wdr_trap | (|tlz_trap_g[`TLU_THRD_NUM-1:0])) &
3446
             inst_vld_g) & ~lsu_defr_trap_g & ~pib_wrap_trap_g;
3447
assign tba_ttype_sel_g[2] =
3448
           (((lsu_tlu_ttype_vld_m2 & inst_vld_g) | va_oor_data_acc_excp_g) &
3449
           ~(|tba_ttype_sel_g[1:0])) | (lsu_defr_trap_g & ~(rstint_g | rst_tri_en));
3450
assign tba_ttype_sel_g[3] =
3451
           ~(|tba_ttype_sel_g[2:0]);
3452
 
3453
// added for timing
3454 113 albert.wat
dffr_s #(4) dffr_tba_ttype_sel_w2 (
3455 95 fafa1971
    .din (tba_ttype_sel_g[3:0]),
3456
    .q   (tba_ttype_sel_w2[3:0]),
3457
    .rst (local_rst),
3458
    .clk (clk),
3459
    .se  (se),
3460 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3461 95 fafa1971
    .so  ()
3462
);
3463
//
3464
mux4ds #(`TSA_TTYPE_WIDTH) mx_tba_ttype_w2 (
3465
    .sel0 (tba_ttype_sel_w2[0]),
3466
    .sel1 (tba_ttype_sel_w2[1]),
3467
    .sel2 (tba_ttype_sel_w2[2]),
3468
    .sel3 (tba_ttype_sel_w2[3]),
3469
    .in0  ({2'b0,rst_hwdr_ttype_w2[`TSA_TTYPE_WIDTH-3:0]}),
3470
    .in1  (early_sync_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3471
    .in2  (adj_lsu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3472
    .in3  (pending_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3473
    .dout (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0])
3474
);
3475
 
3476 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH) dff_tba_ttype_w1 (
3477 95 fafa1971
    .din (tba_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
3478
    .q   (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0]),
3479
    .clk (clk),
3480
    .se  (se),
3481 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3482 95 fafa1971
    .so  ()
3483
);
3484
*/
3485
//
3486
// construct the final_ttype to be written into the trap stack 
3487
// modified for bug 3634, 4640 and timing  
3488
assign final_ttype_sel_g[0] =
3489
            (rstint_g | rst_tri_en) | ((hwint_g | swint_g | sir_inst_g |
3490 113 albert.wat
            (|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & inst_vld_g &
3491 95 fafa1971
            ~lsu_defr_trap_g);
3492
//             reset_sel_g | ((hwint_g | swint_g |
3493
//             (|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & inst_vld_g &
3494
//             ~lsu_defr_trap_g);
3495
 
3496
assign final_ttype_sel_g[1] =
3497
           (((ifu_ttype_vld_g | exu_ttype_vld_g | va_oor_inst_acc_excp_g) |
3498
            (local_sync_trap_g & ~(lsu_tlu_priv_action_g | misalign_addr_ldst_atm_g))) &
3499 113 albert.wat
           ~(rstint_g | sir_inst_g  | hwint_g | swint_g | rst_tri_en | (|tlz_trap_g[`TLU_THRD_NUM-1:0])) &
3500 95 fafa1971
             inst_vld_g) & ~lsu_defr_trap_g & ~pib_wrap_trap_g;
3501
assign final_ttype_sel_g[2] =
3502
           ((lsu_tlu_ttype_vld_m2 & inst_vld_g) | va_oor_data_acc_excp_g)  &
3503
           ~(|final_ttype_sel_g[1:0]) | (lsu_defr_trap_g & ~(rst_tri_en | rstint_g));
3504
assign final_ttype_sel_g[3] =
3505
           ~(|final_ttype_sel_g[2:0]);
3506
//
3507
// added for timing
3508 113 albert.wat
dffr_s #(4) dffr_final_ttype_sel_w2 (
3509 95 fafa1971
    .din (final_ttype_sel_g[3:0]),
3510
    .q   (final_ttype_sel_w2[3:0]),
3511
    .rst (local_rst),
3512
    .clk (clk),
3513
    .se  (se),
3514 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3515 95 fafa1971
    .so  ()
3516
);
3517
// 
3518
// modified for timing
3519
/*
3520
mux3ds #(`TSA_TTYPE_WIDTH) mx_adj_lsu_ttype_m2 (
3521
    .sel0 (lsu_defr_trap_g),
3522
    .sel1 (va_oor_data_acc_excp_g & ~lsu_defr_trap_g),
3523
    .sel2 (~(va_oor_data_acc_excp_g | lsu_defr_trap_g)),
3524
    .in0  ({2'b0, lsu_tlu_async_ttype_g[6:0]}),
3525
    .in1  (9'h030),
3526
    .in2  (lsu_tlu_ttype_m2),
3527
    .dout (adj_lsu_ttype_m2[`TSA_TTYPE_WIDTH-1:0])
3528
);
3529
*/
3530
// added for timing 
3531 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH) dff_lsu_tlu_ttype_w2 (
3532
    .din (lsu_tlu_ttype_m2[`TSA_TTYPE_WIDTH-1:0]),
3533
    .q   (lsu_tlu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3534 95 fafa1971
    .clk (clk),
3535
    .se  (se),
3536 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3537 95 fafa1971
    .so  ()
3538
);
3539
//
3540
/*
3541 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH-2) dff_lsu_tlu_async_ttype_w2 (
3542 95 fafa1971
    .din (lsu_tlu_async_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
3543
    .q   (lsu_tlu_async_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
3544
    .clk (clk),
3545
    .se  (se),
3546 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3547 95 fafa1971
    .so  ()
3548
);
3549
*/
3550 113 albert.wat
mux3ds #(`TSA_TTYPE_WIDTH) mx_adj_lsu_ttype_w2 (
3551 95 fafa1971
    .sel0 (lsu_defr_trap_w2),
3552
    .sel1 (va_oor_data_acc_excp_w2 & ~lsu_defr_trap_w2),
3553
    .sel2 (~(va_oor_data_acc_excp_w2 | lsu_defr_trap_w2)),
3554
    // modified for bug 4561
3555
    // .in0  ({2'b0, lsu_tlu_async_ttype_w2[6:0]}),
3556
    .in0  (9'h032),
3557
    .in1  (9'h030),
3558 113 albert.wat
    .in2  (lsu_tlu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3559
    .dout (adj_lsu_ttype_w2[`TSA_TTYPE_WIDTH-1:0])
3560 95 fafa1971
);
3561
//
3562
// modified for timing 
3563 113 albert.wat
mux4ds #(`TSA_TTYPE_WIDTH) mx_final_ttype_w2 (
3564 95 fafa1971
    .sel0 (final_ttype_sel_w2[0]),
3565
    .sel1 (final_ttype_sel_w2[1]),
3566
    .sel2 (final_ttype_sel_w2[2]),
3567
    .sel3 (final_ttype_sel_w2[3]),
3568 113 albert.wat
    .in0  ({2'b0,rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0]}),
3569
    .in1  (early_sync_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3570
    .in2  (adj_lsu_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3571
    .in3  (pending_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3572
    .dout (final_ttype_w2[`TSA_TTYPE_WIDTH-1:0])
3573 95 fafa1971
);
3574
//
3575
// modified for timing
3576
/*
3577 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH) dff_tlu_final_ttype_w2 (
3578 95 fafa1971
    .din (final_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
3579
    .q   (final_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3580
    .clk (clk),
3581
    .se  (se),
3582 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3583 95 fafa1971
    .so  ()
3584
);
3585
*/
3586
 
3587 113 albert.wat
assign tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] =
3588
           final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
3589 95 fafa1971
//
3590
// added for timing
3591
// pending trap type 
3592
assign onehot_pending_ttype_sel = ~(|pending_trap_sel[2:0]);
3593
//
3594 113 albert.wat
mux4ds #(`TSA_TTYPE_WIDTH) mx_pending_ttype (
3595 95 fafa1971
    .sel0 (pending_trap_sel[0]),
3596
    .sel1 (pending_trap_sel[1]),
3597
        .sel2 (pending_trap_sel[2]),
3598
        .sel3 (onehot_pending_ttype_sel),
3599 113 albert.wat
    .in0  (pending_ttype0[`TSA_TTYPE_WIDTH-1:0]),
3600
    .in1  (pending_ttype1[`TSA_TTYPE_WIDTH-1:0]),
3601
    .in2  (pending_ttype2[`TSA_TTYPE_WIDTH-1:0]),
3602
    .in3  (pending_ttype3[`TSA_TTYPE_WIDTH-1:0]),
3603
    .dout (pending_ttype[`TSA_TTYPE_WIDTH-1:0])
3604 95 fafa1971
);
3605
//
3606
// added for timing 
3607 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH) dff_pending_ttype_w2 (
3608
    .din (pending_ttype[`TSA_TTYPE_WIDTH-1:0]),
3609
    .q   (pending_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
3610 95 fafa1971
    .clk (clk),
3611
    .se  (se),
3612 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3613 95 fafa1971
    .so  ()
3614
);
3615
//
3616
// modified for timing and bug 5117
3617
assign rst_ttype_sel[0] = reset_sel_g;
3618
// modified for bug 5127
3619
assign rst_ttype_sel[1] =
3620 113 albert.wat
           ((|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g);
3621 95 fafa1971
           // ~(rstint_g | rst_tri_en); 
3622
           // ((|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) & ~reset_sel_g; 
3623
// assign rst_ttype_sel[2] = ~(|rst_ttype_sel[1:0]); 
3624
 
3625
// reset ttype  
3626
// modified for bug 3634 and bug 3705
3627
// modified for timing and bug 5117
3628 113 albert.wat
assign rst_hwint_ttype_g[`TSA_TTYPE_WIDTH-3:0] =
3629 95 fafa1971
           (rst_ttype_sel[0])? {4'b00,reset_id_g[2:0]}:
3630
          ((rst_ttype_sel[1])? wrap_tlz_ttype[6:0]:
3631 113 albert.wat
            `HWINT_INT);
3632 95 fafa1971
 
3633 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH-2) dff_rst_hwint_ttype_w2 (
3634
    .din (rst_hwint_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
3635
    .q   (rst_hwint_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
3636 95 fafa1971
    .clk (clk),
3637
    .se  (se),
3638 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3639 95 fafa1971
    .so  ()
3640
);
3641
 
3642 113 albert.wat
dffr_s dffr_rst_hwint_sel_w2 (
3643 95 fafa1971
    .din ((|rst_ttype_sel[1:0]) | hwint_g),
3644
    .q   (rst_hwint_sel_w2),
3645
    .clk (clk),
3646
    .se  (se),
3647
    .rst (local_rst),
3648 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3649 95 fafa1971
    .so  ()
3650
);
3651
 
3652 113 albert.wat
assign rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0] =
3653
       (rst_hwint_sel_w2)? rst_hwint_ttype_w2[`TSA_TTYPE_WIDTH-3:0]:
3654
        final_swint_id_w2[`TSA_TTYPE_WIDTH-3:0];
3655 95 fafa1971
 
3656
/*
3657
mux3ds #(`TSA_TTYPE_WIDTH-2) mx_rst_ttype_g (
3658
    .sel0  (rst_ttype_sel[0]),
3659
    .sel1  (rst_ttype_sel[1]),
3660
        .sel2  (rst_ttype_sel[2]),
3661
    .in0 ({4'b00,reset_id_g[2:0]}),
3662
    .in1 (wrap_tlz_ttype[6:0]),
3663
    .in2 (hwint_swint_ttype[6:0]),
3664
    .dout (rst_ttype_g[`TSA_TTYPE_WIDTH-3:0])
3665
);
3666
//
3667
// added for timing
3668 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH-2) dff_rst_ttype_w2 (
3669 95 fafa1971
    .din (rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
3670
    .q   (rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
3671
    .clk (clk),
3672
    .se  (se),
3673 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3674 95 fafa1971
    .so  ()
3675
);
3676
// modified for timing
3677
 
3678
assign rst_hwdr_ttype_sel[0] = reset_sel_g;
3679
assign rst_hwdr_ttype_sel[1] = hyper_wdr_trap & ~reset_sel_g;
3680
assign rst_hwdr_ttype_sel[2] =
3681
           ((|tlz_trap_g[`TLU_THRD_NUM-1:0]) | pib_wrap_trap_g) &
3682
           ~(|rst_hwdr_ttype_sel[1:0]);
3683
assign rst_hwdr_ttype_sel[3] = ~(|rst_hwdr_ttype_sel[2:0]);
3684
 
3685
mux2ds #(`TSA_TTYPE_WIDTH-2) mx_hwint_swint_ttype (
3686
    .sel0 (hwint_g),
3687
    .sel1 (~hwint_g),
3688
    .in0  (`HWINT_INT),
3689
    .in1  (final_swint_id[6:0]),
3690
    .dout (hwint_swint_ttype[6:0])
3691
);
3692
*/
3693
 
3694 113 albert.wat
mux2ds #(`TSA_TTYPE_WIDTH-2) mx_wrap_tlz_ttype (
3695
    .sel0 (|tlz_trap_g[`TLU_THRD_NUM-1:0]),
3696
    .sel1 (~(|tlz_trap_g[`TLU_THRD_NUM-1:0])),
3697
    .in0  (`TLZ_TRAP),
3698
    .in1  (`PIB_OVERFLOW_TTYPE),
3699 95 fafa1971
    .dout (wrap_tlz_ttype[6:0])
3700
);
3701
//
3702
// modified for timing
3703
assign rst_hwdr_ttype_sel_w2 = hyper_wdr_trap_w2 & ~reset_sel_w2;
3704
 
3705 113 albert.wat
mux2ds #(`TSA_TTYPE_WIDTH-2) mx_rst_hwdr_ttype_w2 (
3706 95 fafa1971
    .sel0  (rst_hwdr_ttype_sel_w2),
3707
    .sel1  (~rst_hwdr_ttype_sel_w2),
3708
    .in0 ({7'b0000010}),
3709 113 albert.wat
    .in1 (rst_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
3710
    .dout (rst_hwdr_ttype_w2[`TSA_TTYPE_WIDTH-3:0])
3711 95 fafa1971
);
3712
//
3713
/*
3714
mux4ds #(`TSA_TTYPE_WIDTH-2) mx_rst_hwdr_ttype (
3715
    .sel0  (rst_hwdr_ttype_sel[0]),
3716
    .sel1  (rst_hwdr_ttype_sel[1]),
3717
        .sel2  (rst_hwdr_ttype_sel[2]),
3718
        .sel3  (rst_hwdr_ttype_sel[3]),
3719
    .in0 ({4'b00,reset_id_g[2:0]}),
3720
    .in1 ({7'b0000010}),
3721
    .in2 (wrap_tlz_ttype[6:0]),
3722
    .in3 (hwint_swint_ttype[6:0]),
3723
    .dout (rst_hwdr_ttype_g[`TSA_TTYPE_WIDTH-3:0])
3724
);
3725
//
3726
// added for timing
3727 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH-2) dff_rst_hwdr_ttype_w2 (
3728 95 fafa1971
    .din (rst_hwdr_ttype_g[`TSA_TTYPE_WIDTH-3:0]),
3729
    .q   (rst_hwdr_ttype_w2[`TSA_TTYPE_WIDTH-3:0]),
3730
    .clk (clk),
3731
    .se  (se),
3732 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3733 95 fafa1971
    .so  ()
3734
);
3735
*/
3736
//
3737
// construct the early_ttype_g for timing to determine whether
3738
// the trap is hypervisor or supervisor traps
3739
// modified for bug 3646, 5117 and timing
3740
assign early_ttype_sel[0] =
3741 113 albert.wat
             reset_sel_g | hwint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0]);
3742 95 fafa1971
             // reset_sel_g | hwint_g | swint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0]);
3743
assign early_ttype_sel[1] =
3744
            local_early_flush_pipe_w;
3745
            // local_early_flush_pipe_w & ~(reset_sel_g | hwint_g | swint_g | 
3746
            // (|tlz_trap_g[`TLU_THRD_NUM-1:0])); 
3747
assign early_ttype_sel[2] =
3748
            ~inst_vld_nf_g | inst_ifu_flush_w | ~(|early_ttype_sel[1:0]);
3749
 
3750 113 albert.wat
assign early_ttype_g[`TSA_TTYPE_WIDTH-1:0] =
3751
           (early_ttype_sel[2])? pending_ttype[`TSA_TTYPE_WIDTH-1:0]:
3752
           (early_ttype_sel[0])? {2'b0,rst_hwint_ttype_g[`TSA_TTYPE_WIDTH-3:0]}:
3753 95 fafa1971
           // (early_ttype_sel[0])? {2'b0,rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]}:
3754 113 albert.wat
            early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0];
3755 95 fafa1971
/*
3756
assign early_ttype_sel[0] =
3757
            reset_sel_g | ((hwint_g | swint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0])) &
3758
            inst_vld_g) ;
3759
assign early_ttype_sel[1] =
3760
            (local_early_flush_pipe_w & ~ifu_tlu_flush_fd_w) & ~rst_tri_en &
3761
           ~((reset_sel_g | hwint_g | swint_g | (|tlz_trap_g[`TLU_THRD_NUM-1:0])) & inst_vld_g);
3762
assign early_ttype_sel[2] =
3763
            ~(|early_ttype_sel[1:0]);
3764
//
3765
mux3ds #(`TSA_TTYPE_WIDTH) mx_early_ttype (
3766
    .sel0 (early_ttype_sel[0]),
3767
    .sel1 (early_ttype_sel[1]),
3768
    .sel2 (early_ttype_sel[2]),
3769
    .in0  ({2'b0,rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]}),
3770
    .in1  (early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
3771
    .in2  (pending_ttype[`TSA_TTYPE_WIDTH-1:0]),
3772
    .dout (early_ttype_g[`TSA_TTYPE_WIDTH-1:0])
3773
);
3774
*/
3775
//
3776
// recoded for timing
3777
assign final_offset_en_g[0] = trap_to_redmode & ~(sir_inst_g | internal_wdr);
3778
assign final_offset_en_g[1] = internal_wdr & ~final_offset_en_g[0];
3779
// modified due to one-hot mux bug
3780
// assign final_offset_en_g[2] = ~(|final_offset_en_g[1:0]); 
3781
 
3782 113 albert.wat
dffr_s #(2) dffr_final_offset_en_w1 (
3783 95 fafa1971
    .din (final_offset_en_g[1:0]),
3784
    .q   (final_offset_en_w1[1:0]),
3785
    .rst (local_rst),
3786
    .clk (clk),
3787
    .se  (se),
3788 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3789 95 fafa1971
    .so  ()
3790
);
3791
 
3792
assign final_offset_sel_w1[2] =
3793
           ~(|final_offset_sel_w1[1:0]);
3794
assign final_offset_sel_w1[1] =
3795
           final_offset_en_w1[1] & ~rst_tri_en;
3796
assign final_offset_sel_w1[0] =
3797
           final_offset_en_w1[0] & ~rst_tri_en;
3798
 
3799 113 albert.wat
mux3ds #(`TSA_TTYPE_WIDTH) mx_final_offset_w1 (
3800 95 fafa1971
    .sel0 (final_offset_sel_w1[0]),
3801
    .sel1 (final_offset_sel_w1[1]),
3802
    .sel2 (final_offset_sel_w1[2]),
3803
    .in0  (9'b000000101),
3804
    .in1  (9'b000000010),
3805 113 albert.wat
    .in2  (tba_ttype_w1[`TSA_TTYPE_WIDTH-1:0]),
3806
    .dout (final_offset_w1[`TSA_TTYPE_WIDTH-1:0])
3807 95 fafa1971
);
3808
 
3809 113 albert.wat
assign tlu_final_offset_w1[`TSA_TTYPE_WIDTH-1:0] =
3810
           final_offset_w1[`TSA_TTYPE_WIDTH-1:0];
3811 95 fafa1971
// 
3812
// generating the trap pc and trap npc
3813
// This section has been modified due to bug 3017 
3814
// pc and npc has been changed from 48 -> 49 bits
3815
// added for one-hot mux problem
3816
assign tlu_pc_mxsel_w2[0] =
3817
           tlu_self_boot_rst_w2 | rst_tri_en;
3818
// modified for bug 3710
3819
assign tlu_pc_mxsel_w2[1] =
3820
           local_select_tba_w2 & ~(rst_tri_en | tlu_self_boot_rst_w2);
3821
assign tlu_pc_mxsel_w2[2] =
3822
           ~(|tlu_pc_mxsel_w2[1:0]);
3823
//
3824
/* logic moved to tlu_misctl
3825
assign  normal_trap_pc_w1 [48:0] =
3826
            {1'b0, tlu_partial_trap_pc_w1[33:0],final_offset_w1[`TSA_TTYPE_WIDTH-1:0],
3827
             5'b00000};
3828
assign  normal_trap_npc_w1[48:0] =
3829
            {1'b0, tlu_partial_trap_pc_w1[33:0],final_offset_w1[`TSA_TTYPE_WIDTH-1:0],
3830
             5'b00100};
3831
//
3832
// code moved from tlu_tdp
3833
mux2ds #(49) mx_trap_pc_w1 (
3834
       .in0  (normal_trap_pc_w1[48:0]),
3835
       .in1  (tlu_restore_pc_w1[48:0]),
3836
       .sel0 (~restore_pc_sel_w1),
3837
       .sel1 (restore_pc_sel_w1),
3838
       .dout (trap_pc_w1[48:0])
3839
);
3840
//
3841 113 albert.wat
dff_s #(49) dff_trap_pc_w2 (
3842 95 fafa1971
    .din (trap_pc_w1[48:0]),
3843
    .q   (trap_pc_w2[48:0]),
3844
    .clk (clk),
3845
    .se  (se),
3846 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3847 95 fafa1971
    .so  ()
3848
);
3849
 
3850
assign tlu_ifu_trappc_w2[48:0] = trap_pc_w2[48:0];
3851
 
3852
mux2ds #(49) mx_trap_npc_w1 (
3853
       .in0  (normal_trap_npc_w1[48:0]),
3854
       .in1  (tlu_restore_npc_w1[48:0]),
3855
       .sel0 (~restore_pc_sel_w1),
3856
       .sel1 (restore_pc_sel_w1),
3857
       .dout (trap_npc_w1[48:0])
3858
);
3859
//
3860 113 albert.wat
dff_s #(49) dff_trap_npc_w2 (
3861 95 fafa1971
    .din (trap_npc_w1[48:0]),
3862
    .q   (trap_npc_w2[48:0]),
3863
    .clk (clk),
3864
    .se  (se),
3865 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3866 95 fafa1971
    .so  ()
3867
);
3868
 
3869
assign tlu_ifu_trapnpc_w2[48:0] = trap_npc_w2[48:0];
3870
*/
3871
 
3872
// determine whether to generate a watch-dog reset using htba as the 
3873
// trap base address instead of the watch-dog reset vector
3874
// added for bug 1894 and modified for bug 1964
3875
// modified for timing 
3876
assign hyper_wdr_early_trap_g = ((true_trap_tid_g[1:0] == 2'b00) ?
3877
               (tlu_hpstate_enb[0] & ~tlu_hpstate_priv[0] & trp_lvl_at_maxstl[0]):
3878
              ((true_trap_tid_g[1:0] == 2'b01) ?
3879
                   (tlu_hpstate_enb[1] & ~tlu_hpstate_priv[1] & trp_lvl_at_maxstl[1]):
3880
                  ((true_trap_tid_g[1:0] == 2'b10) ?
3881
                       (tlu_hpstate_enb[2] & ~tlu_hpstate_priv[2] & trp_lvl_at_maxstl[2]):
3882
                       (tlu_hpstate_enb[3] & ~tlu_hpstate_priv[3] & trp_lvl_at_maxstl[3]))));
3883
 
3884 113 albert.wat
dffr_s dffr_hyper_wdr_early_trap_w2 (
3885 95 fafa1971
   .din (hyper_wdr_early_trap_g),
3886
   .q   (hyper_wdr_early_trap_w2),
3887
   .rst (local_rst),
3888
   .clk (clk),
3889
   .se  (se),
3890 113 albert.wat
   `SIMPLY_RISC_SCANIN,
3891 95 fafa1971
   .so  ()
3892
);
3893
 
3894
assign hyper_wdr_trap_w2 =
3895
           hyper_wdr_early_trap_w2 & (tlu_priv_traps_w2 & ~lsu_defr_trap_w2);
3896
//
3897
// detetermine whehter the trapping thread is in hyperlite mode or is at
3898
// maxstl
3899
// modified for timing and bug 4779
3900
/*
3901
assign tlu_trap_to_hyper_g =
3902
           (true_trap_tid_g[1:0] == 2'b00) ?
3903
               (~tlu_hpstate_enb[0] | tlu_hpstate_priv[0] | trp_lvl_gte_maxstl[0]):
3904
              ((true_trap_tid_g[1:0] == 2'b01) ?
3905
                   (~tlu_hpstate_enb[1] | tlu_hpstate_priv[1] | trp_lvl_gte_maxstl[1]):
3906
                  ((true_trap_tid_g[1:0] == 2'b10) ?
3907
                       (~tlu_hpstate_enb[2] | tlu_hpstate_priv[2] | trp_lvl_gte_maxstl[2]):
3908
                       (~tlu_hpstate_enb[3] | tlu_hpstate_priv[3] | trp_lvl_gte_maxstl[3])));
3909
*/
3910
//
3911
assign tlu_trap_to_hyper_g =
3912
           (true_trap_tid_g[1:0] == 2'b00) ?
3913
               (~tlu_hpstate_enb[0] | tlu_hpstate_priv[0] |
3914
                 trp_lvl_gte_maxstl[0] | (tlz_trap_g[0] & inst_vld_g)):
3915
              ((true_trap_tid_g[1:0] == 2'b01) ?
3916
                   (~tlu_hpstate_enb[1] | tlu_hpstate_priv[1] |
3917
                     trp_lvl_gte_maxstl[1] | (tlz_trap_g[1] & inst_vld_g)):
3918
                  ((true_trap_tid_g[1:0] == 2'b10) ?
3919
                       (~tlu_hpstate_enb[2] | tlu_hpstate_priv[2] |
3920
                         trp_lvl_gte_maxstl[2] | (tlz_trap_g[2] & inst_vld_g)):
3921
                       (~tlu_hpstate_enb[3] | tlu_hpstate_priv[3] |
3922
                         trp_lvl_gte_maxstl[3] | (tlz_trap_g[3] & inst_vld_g))));
3923
// added for timing
3924 113 albert.wat
dffr_s dffr_tlu_tlu_trap_to_hyper_w2 (
3925 95 fafa1971
    .din (tlu_trap_to_hyper_g),
3926
    .q   (tlu_trap_to_hyper_w2),
3927
    .clk (clk),
3928
    .rst (local_rst),
3929
    .se  (se),
3930 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3931 95 fafa1971
    .so  ()
3932
);
3933
 
3934
// recoded for timing
3935
assign select_tba_element_w2[0] =
3936
           ~(tlu_trap_to_hyper_w2 | lsu_defr_trap_w2) & tlu_early_priv_element_w2[0];
3937
assign select_tba_element_w2[1] =
3938
           ~tlu_trap_to_hyper_w2 & (|tlu_early_priv_element_w2[2:1]) & ~lsu_defr_trap_w2;
3939
assign local_select_tba_w2 =
3940
           ~tlu_trap_to_hyper_w2 & (tlu_priv_traps_w2 & ~lsu_defr_trap_w2);
3941
assign tdp_select_tba_w2 = local_select_tba_w2;
3942
assign tlu_select_tba_w2 =
3943
           select_tba_element_w2[1] | (select_tba_element_w2[0] & ~lsu_ttype_vld_w2);
3944
 
3945
/*
3946 113 albert.wat
dffr_s dffr_tlu_select_tba_w2 (
3947 95 fafa1971
    .din (select_tba_g),
3948
    .q   (tlu_select_tba_w2),
3949
    .clk (clk),
3950
    .rst (local_rst),
3951
    .se  (se),
3952 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3953 95 fafa1971
    .so  ()
3954
);
3955
*/
3956
//
3957
// added for bug 2064 and modified for bug 2165
3958
// modified for bug3719
3959
assign early_priv_traps_g =
3960
           ((early_ttype_g[8:4] == 5'b00001)    & (|early_ttype_g[3:0])) |
3961
           ((early_ttype_g[8:4] == 5'b00100)    & (|early_ttype_g[3:0])) |
3962
           ((early_ttype_g[8:4] == 5'b00010)    & ~(early_ttype_g[3] & early_ttype_g[0]))|
3963
           ((early_ttype_g[8:2] == 7'b0011000)  & (early_ttype_g[1] ^ early_ttype_g[0])) |
3964
           ((early_ttype_g[8:4] == 5'b00111)    & (early_ttype_g[3:2]== 2'b11))       |
3965
           (early_ttype_g[8] & ~early_ttype_g[7]) | (early_ttype_g[7] & ~early_ttype_g[8]) |
3966 113 albert.wat
           (pib_wrap_trap_g & ~(|tlz_trap_g[`TLU_THRD_NUM-1:0]) & inst_vld_g) |
3967
           (swint_g & ~(|tlz_trap_g[`TLU_THRD_NUM-1:0]) & inst_vld_g);
3968 95 fafa1971
 
3969
assign exu_hyper_traps_g =
3970
           exu_ttype_vld_g & ((early_ttype_g[8:0] == 9'h029) | (early_ttype_g[8:0] == 9'h034));
3971
 
3972
//
3973
// modified for timing
3974
 
3975
assign tlu_early_priv_element_g[0] =
3976
          early_priv_traps_g & early_ttype_sel[2];
3977
assign tlu_early_priv_element_g[1] =
3978
           early_priv_traps_g & ~early_ttype_sel[2];
3979
// modified for bug 4431, 4443
3980
assign tlu_early_priv_element_g[2] =
3981
          lsu_tlu_wtchpt_trp_g & ~(misalign_addr_jmpl_rtn_g | misalign_addr_ldst_atm_g |
3982
          ifu_ttype_vld_g | exu_hyper_traps_g | lsu_tlu_priv_action_g);
3983
//          lsu_tlu_wtchpt_trp_g & ~(lsu_tlu_priv_violtn_g | misalign_addr_jmpl_rtn_g |
3984
//
3985
// modified for added for timing
3986 113 albert.wat
dffr_s #(3) dffr_tlu_early_priv_element_w2 (
3987 95 fafa1971
    .din (tlu_early_priv_element_g[2:0]),
3988
        .q   (tlu_early_priv_element_w2[2:0]),
3989
    .clk (clk),
3990
    .rst (local_rst),
3991
    .se  (se),
3992 113 albert.wat
    `SIMPLY_RISC_SCANIN,
3993 95 fafa1971
    .so  ()
3994
);
3995
 
3996
assign tlu_priv_traps_w2 =
3997
            tlu_early_priv_element_w2[0] & ~lsu_ttype_vld_w2 |
3998
            tlu_early_priv_element_w2[1] |
3999
            tlu_early_priv_element_w2[2];
4000
 
4001 113 albert.wat
dffr_s dffr_tlu_self_boot_rst_w2 (
4002 95 fafa1971
    .din (tlu_self_boot_rst_g),
4003
        .q   (tlu_self_boot_rst_w2),
4004
    .clk (clk),
4005
    .rst (local_rst),
4006
    .se  (se),
4007 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4008 95 fafa1971
    .so  ()
4009
);
4010
 
4011
//=========================================================================================
4012
//      Generate TSA Control and Data
4013
//=========================================================================================
4014
 
4015
// MODIFY : keep 2b tid
4016
// added for tsa_wr_tid bug
4017
// modified for hypervisor support  and logic loop 
4018
// modified for timing
4019
//
4020
assign tsa_wr_tid_sel_g =
4021
           wsr_inst_g_unflushed & inst_vld_g & (tstate_rw_g | tpc_rw_g |
4022
           tnpc_rw_g  | ttype_rw_g | tlu_htstate_rw_g);
4023
 
4024
// added for timing
4025
 
4026
assign tsa_wr_tid_sel_tim_g =
4027
           (((wsr_inst_g & (tstate_rw_g | tpc_rw_g |
4028
            tnpc_rw_g  | ttype_rw_g | tlu_htstate_rw_g)) |
4029
           ((retry_inst_g | done_inst_g) & cwp_fastcmplt_g)) &
4030
            inst_vld_g) | sync_trap_taken_g ;
4031
 
4032 113 albert.wat
dffr_s dffr_tsa_wr_tid_sel_w2 (
4033 95 fafa1971
    .din (tsa_wr_tid_sel_tim_g),
4034
        .q   (tsa_wr_tid_sel_w2),
4035
    .clk (clk),
4036
    .rst (local_rst),
4037
    .se  (se),
4038 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4039 95 fafa1971
    .so  ()
4040
);
4041
/*
4042
assign tsa_wr_tid_sel_w2 =
4043
           (((wsr_inst_w2 & (tstate_rw_w2 | tpc_rw_w2 |
4044
            tnpc_rw_w2  | ttype_rw_w2 | htstate_rw_w2)) |
4045
           ((retry_inst_w2 | done_inst_w2) & cwp_fastcmplt_w2)) &
4046
            inst_vld_w2) | sync_trap_taken_w2 ;
4047
*/
4048
//
4049
// added for timing
4050
assign  thrid_w2[0] = thread1_wsel_w2 | thread3_wsel_w2;
4051
assign  thrid_w2[1] = thread2_wsel_w2 | thread3_wsel_w2;
4052
//
4053
// 
4054
// modified for bug 4403
4055
/*
4056
mux2ds #(2) mx_tsa_wr_tid (
4057
    .in0  (pend_trap_tid_w2[1:0]),
4058
        .in1  (thrid_w2[1:0]),
4059
    .sel0 (~tsa_wr_tid_sel_w2),
4060
    .sel1 (tsa_wr_tid_sel_w2),
4061
    .dout (tsa_wr_tid[1:0])
4062
);
4063
*/
4064
// modified for bug 4403 dn 4443
4065
assign tsa_wr_tid[1:0] =
4066
           (tsa_wr_tid_sel_w2 & lsu_defr_trap_w2) ? true_trap_tid_w2[1:0]:
4067
           ((tsa_wr_tid_sel_w2 & ~lsu_defr_trap_w2)? thrid_w2[1:0] :
4068
             pend_trap_tid_w2[1:0]);
4069
 
4070
// tsa should not be written by certain resets. May have to extend to wrm etc. !!!
4071
// modified due to the swap of memory from tlu_tsa -> bw_r_rf32x144 -> 2x bw_r_rf32x80
4072
// modified for bug 3384
4073
assign  tsa_wr_vld[0] =
4074
             trap_taken_w2 | local_rst |               // a thread traps
4075
                        ((tpc_rw_w2 | tstate_rw_w2) & wsr_inst_w2); // wrpr-tsa
4076
 
4077
assign  tsa_wr_vld[1] =
4078
                         trap_taken_w2 | local_rst   |                  // a thread traps
4079
                        ((tnpc_rw_w2   | ttype_rw_w2 |
4080
             htstate_rw_w2) & wsr_inst_w2); // wrpr-tsa
4081
// 
4082
// modified due to timing all w stage signals have been moved to w2     
4083
assign  tsa_pc_en           =   tpc_rw_w2        | trap_taken_w2;
4084
assign  tsa_npc_en      =       tnpc_rw_w2       | trap_taken_w2;
4085
assign  tsa_tstate_en   =       tstate_rw_w2 | trap_taken_w2;
4086
assign  tsa_ttype_en    =       ttype_rw_w2  | trap_taken_w2 | local_rst;
4087
//
4088
// added for hypervisor support
4089
assign  tsa_htstate_en  =       htstate_rw_w2 | trap_taken_w2;
4090
 
4091
// Should all these regs enable a read of the tsa ?
4092
assign  tsa_rd_vld =    ifu_tlu_done_inst_d | ifu_tlu_retry_inst_d | // done/retry
4093
                        (tpc_rw_d | tnpc_rw_d | tstate_rw_d | ttype_rw_d |
4094
                         // tick_rw_d | tba_rw_d | pstate_rw_d | tl_rw_d    |
4095
             tlu_htstate_rw_d) & ifu_tlu_rsr_inst_d; // rdpr-tsa
4096
//
4097
// added for timing
4098 113 albert.wat
dff_s dff_tsa_rd_vld_e (
4099 95 fafa1971
    .din (tsa_rd_vld),
4100
        .q   (tsa_rd_vld_e),
4101
    .clk (clk),
4102
    .se  (se),
4103 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4104 95 fafa1971
    .so  ()
4105
);
4106
//
4107
// added for timing
4108
assign  tsa_rd_en = ifu_tlu_done_inst_d | ifu_tlu_retry_inst_d | // done/retry
4109
                    (~(|sraddr2[4:2]) & ifu_tlu_rsr_inst_d); // rdpr-tsa
4110
// 
4111 113 albert.wat
dff_s #(`TLU_THRD_NUM) dff_thread_wsel_w2 (
4112 95 fafa1971
    .din ({thread3_wsel_g, thread2_wsel_g, thread1_wsel_g, thread0_wsel_g}),
4113
    .q   ({thread3_wsel_w2, thread2_wsel_w2, thread1_wsel_w2, thread0_wsel_w2}),
4114
    .clk (clk),
4115
    .se  (se),
4116 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4117 95 fafa1971
    .so  ()
4118
);
4119
 
4120
assign  tlu_thread_wsel_g[0] = thread0_rsel_dec_g;
4121
assign  tlu_thread_wsel_g[1] = thread1_rsel_dec_g;
4122
assign  tlu_thread_wsel_g[2] = thread2_rsel_dec_g;
4123
assign  tlu_thread_wsel_g[3] = thread3_rsel_dec_g;
4124
//
4125
// Added for tsa_wr_tid bug
4126
//
4127
assign  thread0_wtrp_w2 = ~tsa_wr_tid[1] & ~tsa_wr_tid[0];
4128
assign  thread1_wtrp_w2 = ~tsa_wr_tid[1] &  tsa_wr_tid[0];
4129
assign  thread2_wtrp_w2 =  tsa_wr_tid[1] & ~tsa_wr_tid[0];
4130
assign  thread3_wtrp_w2 =  tsa_wr_tid[1] &  tsa_wr_tid[0];
4131
 
4132
// write uses trp-lvl after increment.
4133
mux4ds #(3) tsawthrd (
4134
   .in0  (trp_lvl0_new[2:0]),
4135
   .in1  (trp_lvl1_new[2:0]),
4136
   .in2  (trp_lvl2_new[2:0]),
4137
   .in3  (trp_lvl3_new[2:0]),
4138
   .sel0 (thread0_wtrp_w2),
4139
   .sel1 (thread1_wtrp_w2),
4140
   .sel2 (thread2_wtrp_w2),
4141
   .sel3 (thread3_wtrp_w2),
4142
   .dout (tsa_wr_tpl[2:0])
4143
);
4144
 
4145
// rd use trp-lvl prior to decrement.
4146
mux4ds  #(3) tsarthrd (
4147
        .in0    (trp_lvl0[2:0]),
4148
        .in1    (trp_lvl1[2:0]),
4149
        .in2    (trp_lvl2[2:0]),
4150
        .in3    (trp_lvl3[2:0]),
4151
        .sel0   (thread0_rsel_d),
4152
        .sel1   (thread1_rsel_d),
4153
        .sel2   (thread2_rsel_d),
4154
        .sel3   (thread3_rsel_d),
4155
        .dout   (tsa_rd_tpl[2:0])
4156
);
4157
 
4158
assign  tsa_rd_tid[1:0]  = thrid_d[1:0];
4159
 
4160
//=========================================================================================
4161
//      TT initial state
4162
//=========================================================================================
4163
 
4164
// The initial state of TT should be 1 on por. Since this is required for 4 thread,
4165
// it will be difficult to do this thru a write to the tsa while reset is occuring.
4166
// Instead a bit will be used to mark whether the tt for a thread has been written to.
4167
// If it hasn't then a '1' has to be inserted into the 
4168 113 albert.wat
dff_s dff_rst_d1 (
4169 95 fafa1971
    .din (local_rst),
4170
    .q   (reset_d1),
4171
    .clk (clk),
4172
    .se  (se),
4173 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4174 95 fafa1971
    .so  ()
4175
);
4176
 
4177
assign  tt_init_en =  reset_d1 & tlu_rst_l;
4178
//
4179
// modified for timing all g stage signals have been move to w2
4180
assign  tt_init_rst[0] =
4181
            local_rst | (tsa_ttype_en & (|tsa_wr_vld[1:0]) & thread0_wtrp_w2);
4182
assign  tt_init_rst[1] =
4183
            local_rst | (tsa_ttype_en & (|tsa_wr_vld[1:0]) & thread1_wtrp_w2);
4184
assign  tt_init_rst[2] =
4185
            local_rst | (tsa_ttype_en & (|tsa_wr_vld[1:0]) & thread2_wtrp_w2);
4186
assign  tt_init_rst[3] =
4187
            local_rst | (tsa_ttype_en & (|tsa_wr_vld[1:0]) & thread3_wtrp_w2);
4188
 
4189
assign  lsu_tlu_rsr_data_mod_e[7:0] = ttype_unwritten_sel ? 8'b0000_0001 : lsu_tlu_rsr_data_e[7:0];
4190
 
4191 113 albert.wat
dffre_s dffre_tt_init0  (
4192 95 fafa1971
    .din (tt_init_en),
4193
    .q   (tt_unwritten[0]),
4194
    .rst (tt_init_rst[0]),
4195
    .en  (tt_init_en),
4196
    .clk (clk),
4197
    .se  (se),
4198 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4199 95 fafa1971
    .so  ()
4200
);
4201
 
4202 113 albert.wat
dffre_s dffre_tt_init1  (
4203 95 fafa1971
    .din (tt_init_en),
4204
    .q   (tt_unwritten[1]),
4205
    .rst (tt_init_rst[1]),
4206
    .en  (tt_init_en),
4207
    .clk (clk),
4208
    .se  (se),
4209 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4210 95 fafa1971
    .so  ()
4211
);
4212
 
4213 113 albert.wat
dffre_s dffre_tt_init2  (
4214 95 fafa1971
    .din (tt_init_en),
4215
    .q   (tt_unwritten[2]),
4216
    .rst (tt_init_rst[2]),
4217
    .en  (tt_init_en),
4218
    .clk (clk),
4219
    .se  (se),
4220 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4221 95 fafa1971
    .so  ()
4222
);
4223
 
4224 113 albert.wat
dffre_s dffre_tt_init3  (
4225 95 fafa1971
    .din (tt_init_en),
4226
    .q   (tt_unwritten[3]),
4227
    .rst (tt_init_rst[3]),
4228
    .en  (tt_init_en),
4229
    .clk (clk),
4230
    .se  (se),
4231 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4232 95 fafa1971
    .so  ()
4233
);
4234
 
4235
//=========================================================================================
4236
//      Decode SR Addr
4237
//=========================================================================================
4238
 
4239
// **Exceptions for Write/Reads of Privileged/State Register**
4240
// WRPR:
4241
// - Access to reserved rd fields will cause exception. Done by IFU.
4242
// - A write to TPC, TNPC, TT or TSTATE when the trap level is zero
4243
// (TL=0) causes an illegal_instruction exception.
4244
// - privileged opcode. Use privilege bit in sraddr for exception.
4245
// WRSR :
4246
// - privileged opcode. wrasr only - implementation dependent.
4247
// - illegal inst - done by IFU.
4248
// RDPR :
4249
// - A read from TPC, TNPC, TT or TSTATE when the trap level is zero
4250
// (TL=0) causes an illegal_instruction exception.
4251
// - Access to reserved rs1 fields causes an illegal_inst exception.
4252
// - privileged opcode.
4253
// RDSR :
4254
// - privileged opcode. rdasr only - implementation dependent.
4255
// - Access to reserved rs1 fields causes an illegal_inst exception.
4256 113 albert.wat
assign  sraddr[`TLU_ASR_ADDR_WIDTH-1:0]  =
4257
            ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0];
4258
assign  sraddr2[`TLU_ASR_ADDR_WIDTH-1:0] =
4259
            sraddr[`TLU_ASR_ADDR_WIDTH-1:0];
4260 95 fafa1971
//
4261
// added for hypervisor support
4262
assign  asr_hyperp  =   sraddr2[6];
4263
assign  asr_priv    =   sraddr2[5];
4264
 
4265
assign  stickcmp_rw_d   =  sraddr2[4] & sraddr2[3] &  ~sraddr2[2] &  ~sraddr2[1] &  sraddr2[0] &
4266
                        ~asr_priv;      // 
4267
assign  stick_rw_d = sraddr2[4] & sraddr2[3] &  ~sraddr2[2] & ~sraddr2[1] & ~sraddr2[0];
4268
 
4269
assign  tpc_rw_d        = ~sraddr[4] & ~sraddr[3] & ~sraddr[2] & ~sraddr[1] & ~sraddr[0] &
4270
                        asr_priv;       // =1 ; privileged.
4271
assign  tnpc_rw_d       = ~sraddr[4] & ~sraddr[3] & ~sraddr[2] & ~sraddr[1] &  sraddr[0] &
4272
                        asr_priv;       // =1 ; privileged.
4273
assign  tstate_rw_d     = ~sraddr[4] & ~sraddr[3] & ~sraddr[2] &  sraddr[1] & ~sraddr[0] &
4274
                        asr_priv;       // =1 ; privileged.
4275
assign  ttype_rw_d      = ~sraddr[4] & ~sraddr[3] & ~sraddr[2] &  sraddr[1] &  sraddr[0] &
4276
                        asr_priv;       // =1 ; privileged.
4277
 
4278
// stick and tick are refering to the same register.  
4279
// - privileged action - rdtick only.
4280
assign  tick_rw_d       = ((~sraddr2[4] & ~sraddr2[3] &  sraddr2[2] & ~sraddr2[1] & ~sraddr2[0]) |
4281
                        stick_rw_d) & ~asr_hyperp; // =1 ; privileged.
4282
// 
4283
// modified for bug 1293
4284
// qualified with the rsr read
4285
assign  tick_npriv_r_d = (~sraddr2[4] & ~sraddr2[3] &  sraddr2[2] & ~sraddr2[1] & ~sraddr2[0] |
4286
                          stick_rw_d) & ~asr_priv & ifu_tlu_rsr_inst_d; // =0; non-privileged.
4287
 
4288
assign  tickcmp_rw_d    =  sraddr2[4] & ~sraddr2[3] &  sraddr2[2] &  sraddr2[1] &  sraddr2[0] &
4289
                        ~asr_priv;      // 
4290
assign  tba_rw_d        = ~sraddr[4] & ~sraddr[3] &  sraddr[2] & ~sraddr[1] &  sraddr[0] &
4291
                        asr_priv;       // =1 ; privileged.
4292
assign  pstate_rw_d     = ~sraddr[4] & ~sraddr[3] &  sraddr[2] &  sraddr[1] & ~sraddr[0] &
4293
                        asr_priv;       // =1 ; privileged.
4294
assign  tl_rw_d         = ~sraddr[4] & ~sraddr[3] &  sraddr[2] &  sraddr[1] &  sraddr[0] &
4295
                        asr_priv;       // =1 ; privileged.
4296
assign  pil_rw_d        = ~sraddr2[4] &  sraddr2[3] & ~sraddr2[2] & ~sraddr2[1] & ~sraddr2[0] &
4297
                        asr_priv;       // =1 ; privileged.
4298
assign  set_sftint_d    =  sraddr2[4] &  ~sraddr2[3] & sraddr2[2] & ~sraddr2[1] & ~sraddr2[0] &
4299
                           ~(asr_priv | asr_hyperp);
4300
assign  clr_sftint_d    =  sraddr2[4] &  ~sraddr2[3] & sraddr2[2] & ~sraddr2[1] &  sraddr2[0] &
4301
                           ~(asr_priv | asr_hyperp);
4302
assign  sftint_rg_rw_d  =  sraddr2[4] &  ~sraddr2[3] & sraddr2[2] &  sraddr2[1] & ~sraddr2[0] &
4303
                           ~(asr_priv | asr_hyperp);
4304
//
4305
// pib register decodes
4306
assign pcr_rsr_d =
4307 113 albert.wat
           (sraddr[`TLU_ASR_ADDR_WIDTH-1:0] == `PCR_ASR_ADDR);
4308 95 fafa1971
assign pic_rsr_d =
4309 113 albert.wat
           ((sraddr[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_PRIV_ADDR) |
4310
            (sraddr[`TLU_ASR_ADDR_WIDTH-1:0] == `PIC_ASR_NPRIV_ADDR));
4311 95 fafa1971
 
4312
// Bug 818 fix: The qualification to sraddr[5] is removed due to the sftint and tick_cmp registers
4313
// are priveledged write state registers and not priveledged registers, therefore, the sraddr[5] is 
4314
// not asserted for these
4315
// modified due to timing
4316
// assign       wsr_inst_d      = ifu_tlu_wsr_inst_d; 
4317
//
4318
// added for bug 1293
4319
 
4320
// Stage to E1.
4321
 
4322 113 albert.wat
dff_s dff_tpc_rw_e (
4323 95 fafa1971
    .din (tpc_rw_d),
4324
    .q   (tpc_rw_e),
4325
    .clk (clk),
4326
    .se  (se),
4327 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4328 95 fafa1971
    .so  ()
4329
);
4330
 
4331 113 albert.wat
dff_s dff_tnpc_rw_e (
4332 95 fafa1971
    .din (tnpc_rw_d),
4333
    .q   (tnpc_rw_e),
4334
    .clk (clk),
4335
    .se  (se),
4336 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4337 95 fafa1971
    .so  ()
4338
);
4339
 
4340 113 albert.wat
dff_s dff_tstate_rw_e (
4341 95 fafa1971
    .din (tstate_rw_d),
4342
    .q   (tstate_rw_e),
4343
    .clk (clk),
4344
    .se  (se),
4345 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4346 95 fafa1971
    .so  ()
4347
);
4348
 
4349 113 albert.wat
dff_s dff_ttype_rw_e (
4350 95 fafa1971
    .din (ttype_rw_d),
4351
    .q   (ttype_rw_e),
4352
    .clk (clk),
4353
    .se  (se),
4354 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4355 95 fafa1971
    .so  ()
4356
);
4357
 
4358 113 albert.wat
dff_s dff_tick_rw_e (
4359 95 fafa1971
    .din (tick_rw_d),
4360
    .q   (tick_rw_e),
4361
    .clk (clk),
4362
    .se  (se),
4363 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4364 95 fafa1971
    .so  ()
4365
);
4366
 
4367 113 albert.wat
dff_s dff_tick_npriv_r_e (
4368 95 fafa1971
    .din (tick_npriv_r_d),
4369
    .q   (tick_npriv_r_e),
4370
    .clk (clk),
4371
    .se  (se),
4372 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4373 95 fafa1971
    .so  ()
4374
);
4375
 
4376 113 albert.wat
dff_s dff_tickcmp_rw_e (
4377 95 fafa1971
    .din (tickcmp_rw_d),
4378
    .q   (tickcmp_rw_e),
4379
    .clk (clk),
4380
    .se  (se),
4381 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4382 95 fafa1971
    .so  ()
4383
);
4384
 
4385 113 albert.wat
dff_s dff_tba_rw_e (
4386 95 fafa1971
    .din (tba_rw_d),
4387
    .q   (tba_rw_e),
4388
    .clk (clk),
4389
    .se  (se),
4390 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4391 95 fafa1971
    .so  ()
4392
);
4393
 
4394 113 albert.wat
dff_s dff_pstate_rw_e (
4395 95 fafa1971
    .din (pstate_rw_d),
4396
    .q   (pstate_rw_e),
4397
    .clk (clk),
4398
    .se  (se),
4399 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4400 95 fafa1971
    .so  ()
4401
);
4402
 
4403 113 albert.wat
dff_s dff_tl_rw_d_e (
4404 95 fafa1971
    .din (tl_rw_d),
4405
    .q   (tl_rw_e),
4406
    .clk (clk),
4407
    .se  (se),
4408 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4409 95 fafa1971
    .so  ()
4410
);
4411
 
4412 113 albert.wat
dff_s dff_pil_rw_d_e (
4413 95 fafa1971
    .din (pil_rw_d),
4414
    .q   (pil_rw_e),
4415
    .clk (clk),
4416
    .se  (se),
4417 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4418 95 fafa1971
    .so  ()
4419
);
4420
 
4421 113 albert.wat
dff_s dff_set_sftint_e (
4422 95 fafa1971
    .din (set_sftint_d),
4423
    .q   (set_sftint_e),
4424
    .clk (clk),
4425
    .se  (se),
4426 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4427 95 fafa1971
    .so  ()
4428
);
4429
 
4430 113 albert.wat
dff_s dff_clr_sftint_e (
4431 95 fafa1971
    .din (clr_sftint_d),
4432
    .q   (clr_sftint_e),
4433
    .clk (clk),
4434
    .se  (se),
4435 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4436 95 fafa1971
    .so  ()
4437
);
4438
 
4439 113 albert.wat
dff_s dff_sftint_rg_rw_e (
4440 95 fafa1971
    .din (sftint_rg_rw_d),
4441
    .q   (sftint_rg_rw_e),
4442
    .clk (clk),
4443
    .se  (se),
4444 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4445 95 fafa1971
    .so  ()
4446
);
4447
 
4448 113 albert.wat
dff_s dff_pcr_rsr_e (
4449 95 fafa1971
    .din (pcr_rsr_d),
4450
    .q   (pcr_rsr_e),
4451
    .clk (clk),
4452
    .se  (se),
4453 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4454 95 fafa1971
    .so  ()
4455
);
4456
 
4457 113 albert.wat
dff_s dff_pic_rsr_e (
4458 95 fafa1971
    .din (pic_rsr_d),
4459
    .q   (pic_rsr_e),
4460
    .clk (clk),
4461
    .se  (se),
4462 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4463 95 fafa1971
    .so  ()
4464
);
4465
//
4466
// modified due to timing
4467
/*
4468 113 albert.wat
dff_s dff_wsr_inst_d_e (
4469 95 fafa1971
    .din (wsr_inst_d),
4470
    .q   (wsr_inst_e),
4471
    .clk (clk),
4472
    .se  (se),
4473 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4474 95 fafa1971
    .so  ()
4475
);
4476
*/
4477
assign  wsr_inst_e      = lsu_tlu_wsr_inst_e;
4478
 
4479 113 albert.wat
dff_s dff_stickcmp_rw_e (
4480 95 fafa1971
    .din (stickcmp_rw_d),
4481
    .q   (stickcmp_rw_e),
4482
    .clk (clk),
4483
    .se  (se),
4484 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4485 95 fafa1971
    .so  ()
4486
);
4487
 
4488
// Stage to E2.
4489
 
4490 113 albert.wat
dff_s dff_tpc_rw_m (
4491 95 fafa1971
   .din (tpc_rw_e),
4492
   .q   (tpc_rw_m),
4493
   .clk (clk),
4494
   .se  (se),
4495 113 albert.wat
   `SIMPLY_RISC_SCANIN,
4496 95 fafa1971
   .so  ()
4497
);
4498
 
4499 113 albert.wat
dff_s dff_tnpc_rw_m (
4500 95 fafa1971
   .din (tnpc_rw_e),
4501
   .q   (tnpc_rw_m),
4502
   .clk (clk),
4503
   .se  (se),
4504 113 albert.wat
   `SIMPLY_RISC_SCANIN,
4505 95 fafa1971
   .so  ()
4506
);
4507
 
4508 113 albert.wat
dff_s dff_tstate_rw_m (
4509 95 fafa1971
    .din (tstate_rw_e),
4510
    .q   (tstate_rw_m),
4511
    .clk (clk),
4512
    .se  (se),
4513 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4514 95 fafa1971
    .so  ()
4515
);
4516
 
4517 113 albert.wat
dff_s dff_ttype_rw_m (
4518 95 fafa1971
   .din (ttype_rw_e),
4519
   .q   (ttype_rw_m),
4520
   .clk (clk),
4521
   .se  (se),
4522 113 albert.wat
   `SIMPLY_RISC_SCANIN,
4523 95 fafa1971
   .so  ()
4524
);
4525
 
4526 113 albert.wat
dff_s dff_tick_rw_m (
4527 95 fafa1971
   .din (tick_rw_e),
4528
   .q   (tick_rw_m),
4529
   .clk (clk),
4530
   .se  (se),
4531 113 albert.wat
   `SIMPLY_RISC_SCANIN,
4532 95 fafa1971
   .so  ()
4533
);
4534
 
4535 113 albert.wat
dff_s dff_tick_npriv_r_m (
4536 95 fafa1971
   .din (tick_npriv_r_e),
4537
   .q   (tick_npriv_r_m),
4538
   .clk (clk),
4539
   .se  (se),
4540 113 albert.wat
   `SIMPLY_RISC_SCANIN,
4541 95 fafa1971
   .so  ()
4542
);
4543
 
4544 113 albert.wat
dff_s dff_tickcmp_rw_m (
4545 95 fafa1971
   .din (tickcmp_rw_e),
4546
   .q   (tickcmp_rw_m),
4547
   .clk (clk),
4548
   .se  (se),
4549 113 albert.wat
   `SIMPLY_RISC_SCANIN,
4550 95 fafa1971
   .so  ()
4551
);
4552
//
4553
// added for timing - moved from hypervisor
4554 113 albert.wat
dff_s dff_htickcmp_rw_m_m (
4555 95 fafa1971
    .din (tlu_htickcmp_rw_e),
4556
    .q   (htickcmp_rw_m),
4557
    .clk (clk),
4558
    .se  (se),
4559 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4560 95 fafa1971
    .so  ()
4561
);
4562
 
4563 113 albert.wat
dff_s dff_tba_rw_m (
4564 95 fafa1971
   .din (tba_rw_e),
4565
   .q   (tba_rw_m),
4566
   .clk (clk),
4567
   .se  (se),
4568 113 albert.wat
   `SIMPLY_RISC_SCANIN,
4569 95 fafa1971
   .so  ()
4570
);
4571
 
4572 113 albert.wat
dff_s dff_pstate_rw_m (
4573 95 fafa1971
   .din (pstate_rw_e),
4574
   .q   (pstate_rw_m),
4575
   .clk (clk),
4576
   .se  (se),
4577 113 albert.wat
   `SIMPLY_RISC_SCANIN,
4578 95 fafa1971
   .so  ()
4579
);
4580
 
4581 113 albert.wat
dff_s dff_tl_rw_m (
4582 95 fafa1971
    .din (tl_rw_e),
4583
    .q   (tl_rw_m),
4584
    .clk (clk),
4585
    .se  (se),
4586 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4587 95 fafa1971
    .so  ()
4588
);
4589
 
4590 113 albert.wat
dff_s dff_pil_rw_m (
4591 95 fafa1971
    .din (pil_rw_e),
4592
    .q   (pil_rw_m),
4593
    .clk (clk),
4594
    .se  (se),
4595 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4596 95 fafa1971
    .so  ()
4597
);
4598
 
4599 113 albert.wat
dff_s dff_set_sftint_m (
4600 95 fafa1971
    .din (set_sftint_e),
4601
    .q   (set_sftint_m),
4602
    .clk (clk),
4603
    .se  (se),
4604 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4605 95 fafa1971
    .so  ()
4606
);
4607
 
4608 113 albert.wat
dff_s dff_clr_sftint_m (
4609 95 fafa1971
    .din (clr_sftint_e),
4610
    .q   (clr_sftint_m),
4611
    .clk (clk),
4612
    .se  (se),
4613 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4614 95 fafa1971
    .so  ()
4615
);
4616
 
4617 113 albert.wat
dff_s dff_sftint_rg_rw_m (
4618 95 fafa1971
    .din (sftint_rg_rw_e),
4619
    .q   (sftint_rg_rw_m),
4620
    .clk (clk),
4621
    .se  (se),
4622 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4623 95 fafa1971
    .so  ()
4624
);
4625
 
4626 113 albert.wat
dff_s dff_wsr_inst_m (
4627 95 fafa1971
    .din (wsr_inst_e),
4628
    .q   (wsr_inst_m),
4629
    .clk (clk),
4630
    .se  (se),
4631 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4632 95 fafa1971
    .so  ()
4633
);
4634
//
4635
// added for hypervisor support
4636 113 albert.wat
dff_s dff_stickcmp_rw_m (
4637 95 fafa1971
    .din (stickcmp_rw_e),
4638
    .q   (stickcmp_rw_m),
4639
    .clk (clk),
4640
    .se  (se),
4641 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4642 95 fafa1971
    .so  ()
4643
);
4644
 
4645 113 albert.wat
dff_s dff_tpc_rw_g (
4646 95 fafa1971
    .din (tpc_rw_m),
4647
    .q   (tpc_rw_g),
4648
    .clk (clk),
4649
    .se  (se),
4650 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4651 95 fafa1971
    .so  ()
4652
);
4653
 
4654 113 albert.wat
dff_s dff_tnpc_rw_g (
4655 95 fafa1971
    .din (tnpc_rw_m),
4656
    .q   (tnpc_rw_g),
4657
    .clk (clk),
4658
    .se  (se),
4659 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4660 95 fafa1971
    .so  ()
4661
);
4662
 
4663 113 albert.wat
dff_s dff_tstate_rw_g (
4664 95 fafa1971
    .din (tstate_rw_m),
4665
    .q   (tstate_rw_g),
4666
    .clk (clk),
4667
    .se  (se),
4668 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4669 95 fafa1971
    .so  ()
4670
);
4671
 
4672 113 albert.wat
dff_s dff_ttype_rw_g (
4673 95 fafa1971
    .din (ttype_rw_m),
4674
    .q   (ttype_rw_g),
4675
    .clk (clk),
4676
    .se  (se),
4677 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4678 95 fafa1971
    .so  ()
4679
);
4680
 
4681 113 albert.wat
dff_s dff_tick_rw_g (
4682 95 fafa1971
    .din (tick_rw_m),
4683
    .q   (tick_rw_g),
4684
    .clk (clk),
4685
    .se  (se),
4686 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4687 95 fafa1971
    .so  ()
4688
);
4689
 
4690 113 albert.wat
dff_s dff_tick_npriv_r_g (
4691 95 fafa1971
     .din (tick_npriv_r_m),
4692
     .q   (tick_npriv_r_g),
4693
     .clk (clk),
4694
     .se  (se),
4695 113 albert.wat
     `SIMPLY_RISC_SCANIN,
4696 95 fafa1971
     .so  ()
4697
);
4698
 
4699 113 albert.wat
dff_s dff_tickcmp_rw_g (
4700 95 fafa1971
     .din (tickcmp_rw_m),
4701
     .q   (tickcmp_rw_g),
4702
     .clk (clk),
4703
     .se  (se),
4704 113 albert.wat
     `SIMPLY_RISC_SCANIN,
4705 95 fafa1971
     .so  ()
4706
);
4707
//
4708
// added for timing - moved form hyperv
4709 113 albert.wat
dff_s dff_htickcmp_rw_m_g (
4710 95 fafa1971
    .din (htickcmp_rw_m),
4711
    .q   (htickcmp_rw_g),
4712
    .clk (clk),
4713
    .se  (se),
4714 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4715 95 fafa1971
    .so  ()
4716
);
4717
 
4718 113 albert.wat
dff_s dff_tba_rw_g (
4719 95 fafa1971
     .din (tba_rw_m),
4720
     .q   (tba_rw_g),
4721
     .clk (clk),
4722
     .se  (se),
4723 113 albert.wat
     `SIMPLY_RISC_SCANIN,
4724 95 fafa1971
     .so  ()
4725
);
4726
 
4727 113 albert.wat
dff_s dff_pstate_rw_g (
4728 95 fafa1971
    .din (pstate_rw_m),
4729
    .q   (pstate_rw_g),
4730
    .clk (clk),
4731
    .se  (se),
4732 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4733 95 fafa1971
    .so  ()
4734
);
4735
 
4736 113 albert.wat
dff_s dff_pstate_rw_w2 (
4737 95 fafa1971
    .din (pstate_rw_g),
4738
    .q   (pstate_rw_w2),
4739
    .clk (clk),
4740
    .se  (se),
4741 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4742 95 fafa1971
    .so  ()
4743
);
4744
 
4745 113 albert.wat
dff_s dff_tl_rw_g (
4746 95 fafa1971
    .din (tl_rw_m),
4747
    .q   (tl_rw_g),
4748
    .clk (clk),
4749
    .se  (se),
4750 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4751 95 fafa1971
    .so  ()
4752
);
4753
 
4754 113 albert.wat
dff_s dff_tl_rw_w2 (
4755 95 fafa1971
    .din (tl_rw_g),
4756
    .q   (tl_rw_w2),
4757
    .clk (clk),
4758
    .se  (se),
4759 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4760 95 fafa1971
    .so  ()
4761
);
4762
 
4763 113 albert.wat
dff_s dff_pil_rw_g (
4764 95 fafa1971
    .din (pil_rw_m),
4765
    .q   (pil_rw_g),
4766
    .clk (clk),
4767
    .se  (se),
4768 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4769 95 fafa1971
    .so  ()
4770
);
4771
 
4772 113 albert.wat
dff_s dff_tpc_rw_w2 (
4773 95 fafa1971
    .din (tpc_rw_g),
4774
    .q   (tpc_rw_w2),
4775
    .clk (clk),
4776
    .se  (se),
4777 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4778 95 fafa1971
    .so  ()
4779
);
4780
 
4781 113 albert.wat
dff_s dff_tnpc_rw_w2 (
4782 95 fafa1971
    .din (tnpc_rw_g),
4783
    .q   (tnpc_rw_w2),
4784
    .clk (clk),
4785
    .se  (se),
4786 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4787 95 fafa1971
    .so  ()
4788
);
4789
 
4790 113 albert.wat
dff_s dff_tstate_rw_w2 (
4791 95 fafa1971
    .din (tstate_rw_g),
4792
    .q   (tstate_rw_w2),
4793
    .clk (clk),
4794
    .se  (se),
4795 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4796 95 fafa1971
    .so  ()
4797
);
4798
 
4799 113 albert.wat
dff_s dff_ttype_rw_w2 (
4800 95 fafa1971
    .din (ttype_rw_g),
4801
    .q   (ttype_rw_w2),
4802
    .clk (clk),
4803
    .se  (se),
4804 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4805 95 fafa1971
    .so  ()
4806
);
4807
 
4808 113 albert.wat
dff_s dff_htstate_rw_w2 (
4809 95 fafa1971
    .din (tlu_htstate_rw_g),
4810
    .q   (htstate_rw_w2),
4811
    .clk (clk),
4812
    .se  (se),
4813 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4814 95 fafa1971
    .so  ()
4815
);
4816
 
4817 113 albert.wat
dff_s dff_set_sftint_g (
4818 95 fafa1971
    .din (set_sftint_m),
4819
    .q   (set_sftint_g),
4820
    .clk (clk),
4821
    .se  (se),
4822 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4823 95 fafa1971
    .so  ()
4824
);
4825
 
4826 113 albert.wat
dff_s dff_clr_sftint_g (
4827 95 fafa1971
    .din (clr_sftint_m),
4828
    .q   (clr_sftint_g),
4829
    .clk (clk),
4830
    .se  (se),
4831 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4832 95 fafa1971
    .so  ()
4833
);
4834
 
4835 113 albert.wat
dff_s dff_sftint_rg_rw_g (
4836 95 fafa1971
    .din (sftint_rg_rw_m),
4837
    .q   (sftint_rg_rw_g),
4838
    .clk (clk),
4839
    .se  (se),
4840 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4841 95 fafa1971
    .so  ()
4842
);
4843
 
4844 113 albert.wat
dff_s dff_wsr_inst_g (
4845 95 fafa1971
    .din (wsr_inst_m),
4846
    .q   (wsr_inst_g_unflushed),
4847
    .clk (clk),
4848
    .se  (se),
4849 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4850 95 fafa1971
    .so  ()
4851
);
4852
 
4853 113 albert.wat
dff_s dff_wsr_inst_w2 (
4854 95 fafa1971
    .din (wsr_inst_g),
4855
    .q   (wsr_inst_w2),
4856
    .clk (clk),
4857
    .se  (se),
4858 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4859 95 fafa1971
    .so  ()
4860
);
4861
 
4862 113 albert.wat
dff_s dff_tlu_gl_rw_g (
4863 95 fafa1971
    .din (tlu_gl_rw_m),
4864
    .q   (tlu_gl_rw_g),
4865
    .clk (clk),
4866
    .se  (se),
4867 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4868 95 fafa1971
    .so  ()
4869
);
4870
 
4871
//
4872
// added for hypervisor support
4873 113 albert.wat
dff_s dff_stickcmp_rw_g (
4874 95 fafa1971
    .din (stickcmp_rw_m),
4875
    .q   (stickcmp_rw_g),
4876
    .clk (clk),
4877
    .se  (se),
4878 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4879 95 fafa1971
    .so  ()
4880
);
4881
// modified due to timing violations                                            
4882
// assign       wsr_inst_g = wsr_inst_g_unflushed & ~tlu_ifu_flush_pipe_w & inst_vld_g;
4883
assign  wsr_inst_g = wsr_inst_g_unflushed & ~local_early_flush_pipe_w & inst_vld_g;
4884
assign tlu_wsr_inst_nq_g =
4885
           wsr_inst_g_unflushed & ~local_early_flush_pipe_w & inst_vld_nf_g;
4886
 
4887
 
4888
//=========================================================================================
4889
//      TICK/TICK-CMP RELATED
4890
//=========================================================================================
4891
 
4892
wire    [1:0]    tckctr;
4893
wire    [1:0]    tckctr_in;
4894
 
4895
// modified due to swapping in the incr64 soft macro
4896
// assign tckctr_incr = tckctr + 1;
4897
assign tckctr_in[1:0] = tlu_tckctr_in[1:0];
4898
assign tlu_incr_tick[1:0] = tckctr[1:0];
4899
 
4900 113 albert.wat
dffr_s #(2) dffr_tckctr_cnt (
4901 95 fafa1971
    .din (tckctr_in[1:0]),
4902
    .q (tckctr[1:0]),
4903
    .rst (local_rst | ~tlu_tick_en_l),
4904
    .clk (clk),
4905
    .se  (se),
4906 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4907 95 fafa1971
    .so ()
4908
);
4909
 
4910
// 3rd cycle, increment tick reg.
4911
// assign       tlu_incr_tick = tckctr[1] & tckctr[0];
4912
 
4913
assign  tlu_tickcmp_sel[0] = ~tckctr[1] & ~tckctr[0];
4914
assign  tlu_tickcmp_sel[1] = ~tckctr[1] &  tckctr[0];
4915
assign  tlu_tickcmp_sel[2] =  tckctr[1] & ~tckctr[0];
4916
assign  tlu_tickcmp_sel[3] =  tckctr[1] &  tckctr[0];
4917
 
4918
// TICK.NPT
4919
 
4920
// reset should not be needed in this equation !!!
4921
assign  tick_ctl_din = tlu_wsr_data_b63_w | local_rst | por_rstint_g;
4922
assign  tlu_tick_ctl_din = tick_ctl_din;
4923
 
4924 113 albert.wat
dffe_s dffe_npt0 (
4925 95 fafa1971
    .din (tick_ctl_din),
4926
    .q   (tick_npt0),
4927
    .en  (tick_en[0]),
4928
    .clk (clk),
4929
    .se  (se),
4930 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4931 95 fafa1971
    .so  ()
4932
);
4933
 
4934 113 albert.wat
dffe_s dffe_npt1 (
4935 95 fafa1971
    .din (tick_ctl_din),
4936
    .q   (tick_npt1),
4937
    .en  (tick_en[1]),
4938
    .clk (clk),
4939
    .se  (se),
4940 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4941 95 fafa1971
    .so  ()
4942
);
4943
 
4944 113 albert.wat
dffe_s dffe_npt2 (
4945 95 fafa1971
    .din (tick_ctl_din),
4946
    .q   (tick_npt2),
4947
    .en  (tick_en[2]),
4948
    .clk (clk),
4949
    .se  (se),
4950 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4951 95 fafa1971
    .so  ()
4952
);
4953
 
4954 113 albert.wat
dffe_s dffe_npt3 (
4955 95 fafa1971
    .din (tick_ctl_din),
4956
    .q   (tick_npt3),
4957
    .en  (tick_en[3]),
4958
    .clk (clk),
4959
    .se  (se),
4960 113 albert.wat
    `SIMPLY_RISC_SCANIN,
4961 95 fafa1971
    .so  ()
4962
);
4963
 
4964
assign  tlu_tick_npt =
4965
        (thread0_rsel_e & tick_npt0) |
4966
                (thread1_rsel_e & tick_npt1) |
4967
                        (thread2_rsel_e & tick_npt2) |
4968
                                (thread3_rsel_e & tick_npt3);
4969
 
4970
assign  tick_npt_priv_act_g =
4971
        (tick_npriv_r_g & ~ifu_ttype_vld_tmp_g) &
4972
           ((tick_npt0 & thread0_rsel_g & tlu_none_priv[0]) |
4973
                (tick_npt1 & thread1_rsel_g & tlu_none_priv[1]) |
4974
                (tick_npt2 & thread2_rsel_g & tlu_none_priv[2]) |
4975
                (tick_npt3 & thread3_rsel_g & tlu_none_priv[3]));
4976
//
4977
// added for timing fix
4978
assign  tick_npt_priv_act_m =
4979
         (tick_npriv_r_m & ~ifu_ttype_vld_m) &
4980
        ((tick_npt0 & thread0_rsel_m & tlu_none_priv[0]) |
4981
         (tick_npt1 & thread1_rsel_m & tlu_none_priv[1]) |
4982
         (tick_npt2 & thread2_rsel_m & tlu_none_priv[2]) |
4983
         (tick_npt3 & thread3_rsel_m & tlu_none_priv[3]));
4984
 
4985
assign  exu_tick_npt_priv_act_m =
4986
          tick_npriv_r_m &
4987
        ((tick_npt0 & thread0_stg_m_buf & tlu_none_priv[0]) |
4988
         (tick_npt1 & thread1_stg_m_buf & tlu_none_priv[1]) |
4989
         (tick_npt2 & thread2_stg_m_buf & tlu_none_priv[2]) |
4990
         (tick_npt3 & thread3_stg_m_buf & tlu_none_priv[3]));
4991
 
4992
//=========================================================================================
4993
//      Soft Interrupt Control
4994
//=========================================================================================
4995
 
4996
wire    [1:0]    sftintctr;
4997
wire    [1:0]    sftintctr_incr;
4998
 
4999
assign sftintctr_incr[1:0] = sftintctr[1:0] + 2'b01;
5000
 
5001 113 albert.wat
dffr_s #(2) dffr_sftint_cnt  (
5002 95 fafa1971
   .din (sftintctr_incr[1:0]),
5003
   .q (sftintctr[1:0]),
5004
   .rst (local_rst),
5005
   .clk (clk),
5006
   .se  (se),
5007 113 albert.wat
   `SIMPLY_RISC_SCANIN,
5008 95 fafa1971
   .so ()
5009
);
5010
// 
5011
// modified for bug 4626 and 5117 
5012
/*
5013
assign swint_nq_g = swint_g;
5014
assign swint_thrd_g[0]= swint_nq_g & thread0_rsel_g & tlu_int_pstate_ie[0];
5015
assign swint_thrd_g[1]= swint_nq_g & thread1_rsel_g & tlu_int_pstate_ie[1];
5016
assign swint_thrd_g[2]= swint_nq_g & thread2_rsel_g & tlu_int_pstate_ie[2];
5017
// assign swint_thrd_g[3]= swint_nq_g & thread3_rsel_g & tlu_int_pstate_ie[3];
5018
*/
5019
 
5020
assign sftint_user_update_g =
5021
       clr_sftint_g | sftint_rg_rw_g;
5022
 
5023 113 albert.wat
dffr_s dffr_sftint_user_update_w2 (
5024 95 fafa1971
    .din (sftint_user_update_g),
5025
        .q   (sftint_user_update_w2),
5026
    .clk (clk),
5027
    .rst (local_rst),
5028
    .se  (se),
5029 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5030 95 fafa1971
    .so  ()
5031
);
5032
 
5033
assign penc_sel_user_update = sftint_user_update_w2 & ~swint_g;
5034
 
5035
assign sftint_penc_update = sftint_user_update_w2 | swint_g;
5036
 
5037
assign sftint_penc_thrd[0]=
5038
       (swint_g & thread0_rsel_g) | (penc_sel_user_update & thread0_wsel_w2);
5039
assign sftint_penc_thrd[1]=
5040
       (swint_g & thread1_rsel_g) | (penc_sel_user_update & thread1_wsel_w2);
5041
assign sftint_penc_thrd[2]=
5042
       (swint_g & thread2_rsel_g) | (penc_sel_user_update & thread2_wsel_w2);
5043
 
5044
assign  tlu_sftint_penc_sel[0] =
5045
            ((~sftintctr[1] & ~sftintctr[0] & ~sftint_penc_update) |
5046
             sftint_penc_thrd[0]) & ~rst_tri_en;
5047
assign  tlu_sftint_penc_sel[1] =
5048
            ((~sftintctr[1] &  sftintctr[0] & ~sftint_penc_update) |
5049
             sftint_penc_thrd[1]) & ~rst_tri_en;
5050
assign  tlu_sftint_penc_sel[2] =
5051
            (( sftintctr[1] & ~sftintctr[0] & ~sftint_penc_update) |
5052
             sftint_penc_thrd[2]) & ~rst_tri_en;
5053
//
5054
// added for bug 5117
5055
 
5056
assign sftint_wait_rst[0] =
5057
           sftint_pend_wait[0] & tlu_sftint_penc_sel[0];
5058
assign sftint_wait_rst[1] =
5059
           sftint_pend_wait[1] & tlu_sftint_penc_sel[1];
5060
assign sftint_wait_rst[2] =
5061
           sftint_pend_wait[2] & tlu_sftint_penc_sel[2];
5062
assign sftint_wait_rst[3] =
5063
           sftint_pend_wait[3] & tlu_sftint_penc_sel[3];
5064
 
5065 113 albert.wat
dffr_s dffr_sftint_pend_wait_0 (
5066 95 fafa1971
    .din (sftint_user_update_g & thread0_rsel_dec_g),
5067
        .q   (sftint_pend_wait[0]),
5068
    .clk (clk),
5069
    .rst (local_rst | sftint_wait_rst[0]),
5070
    .se  (se),
5071 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5072 95 fafa1971
    .so  ()
5073
);
5074 113 albert.wat
dffr_s dffr_sftint_pend_wait_1 (
5075 95 fafa1971
    .din (sftint_user_update_g & thread1_rsel_dec_g),
5076
        .q   (sftint_pend_wait[1]),
5077
    .clk (clk),
5078
    .rst (local_rst | sftint_wait_rst[1]),
5079
    .se  (se),
5080 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5081 95 fafa1971
    .so  ()
5082
);
5083
 
5084 113 albert.wat
dffr_s dffr_sftint_pend_wait_2 (
5085 95 fafa1971
    .din (sftint_user_update_g & thread2_rsel_dec_g),
5086
        .q   (sftint_pend_wait[2]),
5087
    .clk (clk),
5088
    .rst (local_rst | sftint_wait_rst[2]),
5089
    .se  (se),
5090 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5091 95 fafa1971
    .so  ()
5092
);
5093
 
5094 113 albert.wat
dffr_s dffr_sftint_pend_wait_3 (
5095 95 fafa1971
    .din (sftint_user_update_g & thread3_rsel_dec_g),
5096
        .q   (sftint_pend_wait[3]),
5097
    .clk (clk),
5098
    .rst (local_rst | sftint_wait_rst[3]),
5099
    .se  (se),
5100 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5101 95 fafa1971
    .so  ()
5102
);
5103
/*
5104
assign  tlu_sftint_penc_sel[0] =
5105
            (~sftintctr[1] & ~sftintctr[0] & ~swint_nq_g) | swint_thrd_g[0];
5106
assign  tlu_sftint_penc_sel[1] =
5107
            (~sftintctr[1] &  sftintctr[0] & ~swint_nq_g) | swint_thrd_g[1];
5108
assign  tlu_sftint_penc_sel[2] =
5109
            ( sftintctr[1] & ~sftintctr[0] & ~swint_nq_g) | swint_thrd_g[2];
5110
//
5111
*/
5112
// 
5113
// modified for one-hot problem
5114
assign  tlu_sftint_penc_sel[3] =
5115
            ~(|tlu_sftint_penc_sel[2:0]);
5116
// assign       tlu_sftint_penc_sel[3] =
5117
//             ( sftintctr[1] &  sftintctr[0] & ~swint_nq_g) | swint_thrd_g[3];
5118
/*
5119
assign  tlu_sftint_penc_sel[0] = ~sftintctr[1] & ~sftintctr[0];
5120
assign  tlu_sftint_penc_sel[1] = ~sftintctr[1] &  sftintctr[0];
5121
assign  tlu_sftint_penc_sel[2] =  sftintctr[1] & ~sftintctr[0];
5122
assign  tlu_sftint_penc_sel[3] =  sftintctr[1] &  sftintctr[0];
5123
*/
5124
 
5125
//  Flop sftint values on a per thread basis.
5126 113 albert.wat
dffe_s #(4) dffe_sftint_id0  (
5127 95 fafa1971
    .din (tlu_sftint_id[3:0]),
5128
    .q   (sftint0_id[3:0]),
5129
    .en  (tlu_sftint_penc_sel[0]),
5130
    .clk (clk),
5131
    .se  (se),
5132 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5133 95 fafa1971
    .so  ()
5134
);
5135
 
5136 113 albert.wat
dffe_s #(4) dffe_sftint_id1  (
5137 95 fafa1971
    .din (tlu_sftint_id[3:0]),
5138
    .q   (sftint1_id[3:0]),
5139
    .en  (tlu_sftint_penc_sel[1]),
5140
    .clk (clk),
5141
    .se  (se),
5142 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5143 95 fafa1971
    .so  ()
5144
);
5145
 
5146 113 albert.wat
dffe_s #(4) dffe_sftint_id2  (
5147 95 fafa1971
    .din (tlu_sftint_id[3:0]),
5148
    .q   (sftint2_id[3:0]),
5149
    .en  (tlu_sftint_penc_sel[2]),
5150
    .clk (clk),
5151
    .se  (se),
5152 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5153 95 fafa1971
    .so  ()
5154
);
5155
 
5156 113 albert.wat
dffe_s #(4) dffe_sftint_id3  (
5157 95 fafa1971
    .din (tlu_sftint_id[3:0]),
5158
    .q   (sftint3_id[3:0]),
5159
    .en  (tlu_sftint_penc_sel[3]),
5160
    .clk (clk),
5161
    .se  (se),
5162 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5163 95 fafa1971
    .so  ()
5164
);
5165
 
5166
// Soft Int Control
5167
// modified to fix one-hot problem
5168
assign  tlu_set_sftint_l_g   =  ~(set_sftint_g) | rst_tri_en;
5169
assign  tlu_clr_sftint_l_g   =  ~(clr_sftint_g) | rst_tri_en;
5170
assign  tlu_wr_sftint_l_g    =  ~(sftint_rg_rw_g) | rst_tri_en;
5171
// modified for timing
5172
/*
5173
assign  tlu_set_sftint_l_g   =  ~(set_sftint_g & wsr_inst_g);
5174
assign  tlu_clr_sftint_l_g   =  ~(clr_sftint_g & wsr_inst_g);
5175
assign  tlu_wr_sftint_l_g    =  ~(sftint_rg_rw_g & wsr_inst_g);
5176
*/
5177
 
5178
// modified for pib support
5179
//
5180
assign tlu_sftint_en_l_g[0] =
5181
           ~((set_sftint_g | clr_sftint_g | sftint_rg_rw_g) &
5182
              wsr_inst_g & thread0_rsel_dec_g) & tlu_rst_l;
5183
assign tlu_sftint_en_l_g[1] =
5184
           ~((set_sftint_g | clr_sftint_g | sftint_rg_rw_g) &
5185
              wsr_inst_g & thread1_rsel_dec_g) & tlu_rst_l;
5186
assign tlu_sftint_en_l_g[2] =
5187
           ~((set_sftint_g | clr_sftint_g | sftint_rg_rw_g) &
5188
              wsr_inst_g & thread2_rsel_dec_g) & tlu_rst_l;
5189
assign tlu_sftint_en_l_g[3] =
5190
           ~((set_sftint_g | clr_sftint_g | sftint_rg_rw_g) &
5191
              wsr_inst_g & thread3_rsel_dec_g) & tlu_rst_l;
5192
 
5193
// added for one-hot mux bug
5194
// modified for timing
5195
assign tlu_sftint_mx_sel[0] =
5196
           ~(|tlu_sftint_mx_sel[3:1]);
5197
assign tlu_sftint_mx_sel[1] =
5198
           (set_sftint_g | clr_sftint_g | sftint_rg_rw_g) &
5199
            thread1_rsel_dec_g & ~rst_tri_en;
5200
assign tlu_sftint_mx_sel[2] =
5201
           (set_sftint_g | clr_sftint_g | sftint_rg_rw_g) &
5202
            thread2_rsel_dec_g & ~rst_tri_en;
5203
assign tlu_sftint_mx_sel[3] =
5204
           (set_sftint_g | clr_sftint_g | sftint_rg_rw_g) &
5205
            thread3_rsel_dec_g & ~rst_tri_en;
5206
//
5207
// determine whether there is a pending sftint interrupt for each thread
5208
//
5209
assign tlu_int_sftint_pend[0] = |(sftint0_id[3:0]) & ~sftint_pend_wait[0];
5210
assign tlu_int_sftint_pend[1] = |(sftint1_id[3:0]) & ~sftint_pend_wait[1];
5211
assign tlu_int_sftint_pend[2] = |(sftint2_id[3:0]) & ~sftint_pend_wait[2];
5212
assign tlu_int_sftint_pend[3] = |(sftint3_id[3:0]) & ~sftint_pend_wait[3];
5213
 
5214
// if there is no existing sft interrupt, then sftint_id = 0, and vld would never be asserted. 
5215
// this is why a 15b vector has been encoded as a 16b vector.
5216
// modified for hypervisor support
5217
 
5218
// fix for bug 7027
5219
/*
5220
assign sftint_only_vld[0] = (tlu_int_sftint_pend[0]) ?
5221
                            (sftint0_id[3:0] > true_pil0[3:0]) & pil_cmp_en[0] : 1'b0;
5222
assign sftint_only_vld[1] = (tlu_int_sftint_pend[1]) ?
5223
                            (sftint1_id[3:0] > true_pil1[3:0]) & pil_cmp_en[1] : 1'b0;
5224
assign sftint_only_vld[2] = (tlu_int_sftint_pend[2]) ?
5225
                            (sftint2_id[3:0] > true_pil2[3:0]) & pil_cmp_en[2] : 1'b0;
5226
assign sftint_only_vld[3] = (tlu_int_sftint_pend[3]) ?
5227
                            (sftint3_id[3:0] > true_pil3[3:0]) & pil_cmp_en[3] : 1'b0;
5228
*/
5229
 
5230
assign sftint_only_vld[0] = (tlu_int_sftint_pend[0]) ?
5231
                            (sftint0_id[3:0] > true_pil0[3:0]) : 1'b0;
5232
assign sftint_only_vld[1] = (tlu_int_sftint_pend[1]) ?
5233
                            (sftint1_id[3:0] > true_pil1[3:0]) : 1'b0;
5234
assign sftint_only_vld[2] = (tlu_int_sftint_pend[2]) ?
5235
                            (sftint2_id[3:0] > true_pil2[3:0]) : 1'b0;
5236
assign sftint_only_vld[3] = (tlu_int_sftint_pend[3]) ?
5237
                            (sftint3_id[3:0] > true_pil3[3:0]) : 1'b0;
5238
 
5239
 
5240
// swint 
5241
// removed the qualification of the tlu_int_pstate_ie - otherwise, IFU might never wakeup
5242
// after the thread has been suspended.
5243
// 
5244
// modified for timing
5245
assign tlu_sftint_vld[0] =
5246
           (tlu_cpu_mondo_trap[0] | tlu_dev_mondo_trap[0] | sftint_only_vld[0]);
5247
assign tlu_sftint_vld[1] =
5248
           (tlu_cpu_mondo_trap[1] | tlu_dev_mondo_trap[1] | sftint_only_vld[1]);
5249
assign tlu_sftint_vld[2] =
5250
           (tlu_cpu_mondo_trap[2] | tlu_dev_mondo_trap[2] | sftint_only_vld[2]);
5251
assign tlu_sftint_vld[3] =
5252
           (tlu_cpu_mondo_trap[3] | tlu_dev_mondo_trap[3] | sftint_only_vld[3]);
5253
//
5254
// added for hypervisor support
5255
// htick_match traps 
5256
 
5257
// fix for bug 7027
5258
/*
5259
assign tlu_hintp_vld[0] =
5260
           tlu_hintp[0] & (~tlu_hpstate_priv[0] |
5261
          (tlu_hpstate_priv[0] & tlu_int_pstate_ie[0]));
5262
assign tlu_hintp_vld[1] =
5263
           tlu_hintp[1] & (~tlu_hpstate_priv[1] |
5264
          (tlu_hpstate_priv[1] & tlu_int_pstate_ie[1]));
5265
assign tlu_hintp_vld[2] =
5266
           tlu_hintp[2] & (~tlu_hpstate_priv[2] |
5267
          (tlu_hpstate_priv[2] & tlu_int_pstate_ie[2]));
5268
assign tlu_hintp_vld[3] =
5269
           tlu_hintp[3] & (~tlu_hpstate_priv[3] |
5270
          (tlu_hpstate_priv[3] & tlu_int_pstate_ie[3]));
5271
*/
5272
 
5273
assign tlu_hintp_vld[0] = tlu_hintp[0];
5274
assign tlu_hintp_vld[1] = tlu_hintp[1];
5275
assign tlu_hintp_vld[2] = tlu_hintp[2];
5276
assign tlu_hintp_vld[3] = tlu_hintp[3];
5277
 
5278
 
5279
//
5280
// resum_err traps
5281
// modified for timing
5282
 
5283
// fix for bug 7027
5284
/*
5285
assign tlu_rerr_vld[0] = tlu_resum_err_trap[0] & tlu_int_pstate_ie[0];
5286
assign tlu_rerr_vld[1] = tlu_resum_err_trap[1] & tlu_int_pstate_ie[1];
5287
assign tlu_rerr_vld[2] = tlu_resum_err_trap[2] & tlu_int_pstate_ie[2];
5288
assign tlu_rerr_vld[3] = tlu_resum_err_trap[3] & tlu_int_pstate_ie[3];
5289
*/
5290
assign tlu_rerr_vld[0] = tlu_resum_err_trap[0];
5291
assign tlu_rerr_vld[1] = tlu_resum_err_trap[1];
5292
assign tlu_rerr_vld[2] = tlu_resum_err_trap[2];
5293
assign tlu_rerr_vld[3] = tlu_resum_err_trap[3];
5294
 
5295
 
5296
assign pil_cmp_en[0] =
5297
           ~(tlu_hpstate_priv[0] & tlu_hpstate_enb[0]);
5298
assign pil_cmp_en[1] =
5299
           ~(tlu_hpstate_priv[1] & tlu_hpstate_enb[1]);
5300
assign pil_cmp_en[2] =
5301
           ~(tlu_hpstate_priv[2] & tlu_hpstate_enb[2]);
5302
assign pil_cmp_en[3] =
5303
           ~(tlu_hpstate_priv[3] & tlu_hpstate_enb[3]);
5304
 
5305
// TLU.TICK_INT - The tick and stick interrupt logic has been moved to tlu_tdp
5306
// the interrupt will be report back to tlu_tcl via the softint settings
5307
/*
5308
assign wsr_tick_intclr_g =  (tlu_clr_sftint_l_g | ~tlu_wsr_data_w[0]) & (tlu_wr_sftint_l_g | tlu_wsr_data_w[0]);
5309
assign wsr_tick_intset_g = ~(tlu_set_sftint_l_g & tlu_wr_sftint_l_g) & tlu_wsr_data_w[0];
5310
//
5311
// added for hypervisor suppor for tlu_stck_int
5312
assign wsr_stick_intclr_g =  (tlu_clr_sftint_l_g | ~tlu_wsr_data_b16_w) & (tlu_wr_sftint_l_g | tlu_wsr_data_b16_w);
5313
assign wsr_stick_intset_g = ~(tlu_set_sftint_l_g & tlu_wr_sftint_l_g) & tlu_wsr_data_b16_w;
5314
*/
5315
// The following code has been moved to tlu_tdp
5316
/*
5317
assign  tick_intclr[0] = tlu_tick_int[0] & wsr_tick_intclr_g;
5318
assign  tick_intclr[1] = tlu_tick_int[1] & wsr_tick_intclr_g;
5319
assign  tick_intclr[2] = tlu_tick_int[2] & wsr_tick_intclr_g;
5320
assign  tick_intclr[3] = tlu_tick_int[3] & wsr_tick_intclr_g;
5321
//
5322
assign  tickcmp_int[0] = tlu_tick_match & ~tick_intdis0 & tlu_tickcmp_sel[0];
5323
assign  tickcmp_int[1] = tlu_tick_match & ~tick_intdis1 & tlu_tickcmp_sel[1];
5324
assign  tickcmp_int[2] = tlu_tick_match & ~tick_intdis2 & tlu_tickcmp_sel[2];
5325
assign  tickcmp_int[3] = tlu_tick_match & ~tick_intdis3 & tlu_tickcmp_sel[3];
5326
 
5327
assign  tick_intrpt[0] = tickcmp_int[0] | tick_intclr[0];
5328
assign  tick_intrpt[1] = tickcmp_int[1] | tick_intclr[1];
5329
assign  tick_intrpt[2] = tickcmp_int[2] | tick_intclr[2];
5330
assign  tick_intrpt[3] = tickcmp_int[3] | tick_intclr[3];
5331
 
5332
// modified for bug 1022
5333
// qualified tlu_set_sftint with wsr_data_w[0]
5334
//
5335
assign  tick_int_en[0] = ~tlu_sftint_en_l_g[0] | tick_intrpt[0];
5336
assign  tick_int_din[0] = (tick_intrpt[0] | wsr_tick_intset_g) ? 1'b1 : 1'b0;
5337
 
5338
assign  tick_int_en[1] = ~tlu_sftint_en_l_g[1] | tick_intrpt[1];
5339
assign  tick_int_din[1] = (tick_intrpt[1] | wsr_tick_intset_g) ? 1'b1 : 1'b0;
5340
 
5341
assign  tick_int_en[2] = ~tlu_sftint_en_l_g[2] | tick_intrpt[2];
5342
assign  tick_int_din[2] = (tick_intrpt[2] | wsr_tick_intset_g) ? 1'b1 : 1'b0;
5343
 
5344
assign  tick_int_en[3] = ~tlu_sftint_en_l_g[3] | tick_intrpt[3];
5345
assign  tick_int_din[3] = (tick_intrpt[3] | wsr_tick_intset_g) ? 1'b1 : 1'b0;
5346
//
5347
// recoded tlu_tick_int for bug 818
5348 113 albert.wat
dffre_s dffre_tick_int0 (
5349 95 fafa1971
    .din (tick_int_din[0]),
5350
    .q   (tlu_tick_int[0]),
5351
    .rst (local_rst),
5352
    .en  (tick_int_en[0]),
5353
    .clk (clk),
5354
    .se  (se),
5355 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5356 95 fafa1971
    .so  ()
5357
);
5358
//
5359
// recoded tlu_tick_int for bug 818
5360 113 albert.wat
dffre_s dffre_tick_int1 (
5361 95 fafa1971
    .din (tick_int_din[1]),
5362
    .q   (tlu_tick_int[1]),
5363
    .rst (local_rst),
5364
    .en  (tick_int_en[1]),
5365
    .clk (clk),
5366
    .se  (se),
5367 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5368 95 fafa1971
    .so  ()
5369
);
5370
// recoded tlu_tick_int for bug 818
5371
//
5372 113 albert.wat
dffre_s dffre_tick_int2 (
5373 95 fafa1971
    .din (tick_int_din[2]),
5374
    .q   (tlu_tick_int[2]),
5375
    .rst (local_rst),
5376
    .en  (tick_int_en[2]),
5377
    .clk (clk),
5378
    .se  (se),
5379 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5380 95 fafa1971
    .so  ()
5381
);
5382
//
5383
// recoded tlu_tick_int for bug 818
5384 113 albert.wat
dffre_s dffre_tick_int3 (
5385 95 fafa1971
    .din (tick_int_din[3]),
5386
    .q   (tlu_tick_int[3]),
5387
    .rst (local_rst),
5388
    .en  (tick_int_en[3]),
5389
    .clk (clk),
5390
    .se  (se),
5391 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5392 95 fafa1971
    .so  ()
5393
);
5394
*/
5395
//
5396
// added and/or modified for hypervisor support
5397
// the following logic has been moved to tlu_tdp
5398
/*
5399
assign  stick_intclr[0] = tlu_stick_int[0] & wsr_stick_intclr_g;
5400
assign  stick_intclr[1] = tlu_stick_int[1] & wsr_stick_intclr_g;
5401
assign  stick_intclr[2] = tlu_stick_int[2] & wsr_stick_intclr_g;
5402
assign  stick_intclr[3] = tlu_stick_int[3] & wsr_stick_intclr_g;
5403
//
5404
assign  stickcmp_int[0] = tlu_stick_match & ~stick_intdis0 & tlu_tickcmp_sel[0];
5405
assign  stickcmp_int[1] = tlu_stick_match & ~stick_intdis1 & tlu_tickcmp_sel[1];
5406
assign  stickcmp_int[2] = tlu_stick_match & ~stick_intdis2 & tlu_tickcmp_sel[2];
5407
assign  stickcmp_int[3] = tlu_stick_match & ~stick_intdis3 & tlu_tickcmp_sel[3];
5408
//
5409
assign  stick_intrpt[0] = stickcmp_int[0] | stick_intclr[0];
5410
assign  stick_intrpt[1] = stickcmp_int[1] | stick_intclr[1];
5411
assign  stick_intrpt[2] = stickcmp_int[2] | stick_intclr[2];
5412
assign  stick_intrpt[3] = stickcmp_int[3] | stick_intclr[3];
5413
//
5414
// modified for bug 1022
5415
// qualified tlu_set_sftint with wsr_data_w[16]
5416
//
5417
assign  stick_int_en[0] = ~tlu_sftint_en_l_g[0] | stick_intrpt[0];
5418
assign  stick_int_din[0] = (stick_intrpt[0] | wsr_stick_intset_g) ? 1'b1 : 1'b0;
5419
 
5420
assign  stick_int_en[1] = ~tlu_sftint_en_l_g[1] | stick_intrpt[1];
5421
assign  stick_int_din[1] = (stick_intrpt[1] | wsr_stick_intset_g) ? 1'b1 : 1'b0;
5422
 
5423
assign  stick_int_en[2] = ~tlu_sftint_en_l_g[2] | stick_intrpt[2];
5424
assign  stick_int_din[2] = (stick_intrpt[2] | wsr_stick_intset_g) ? 1'b1 : 1'b0;
5425
 
5426
assign  stick_int_en[3] = ~tlu_sftint_en_l_g[3] | stick_intrpt[3];
5427
assign  stick_int_din[3] = (stick_intrpt[3] | wsr_stick_intset_g) ? 1'b1 : 1'b0;
5428
 
5429
// recoded tlu_tick_int for bug 818
5430
//
5431 113 albert.wat
dffre_s dffre_stick_int0 (
5432 95 fafa1971
    .din (stick_int_din[0]),
5433
    .q   (tlu_stick_int[0]),
5434
    .rst (local_rst),
5435
    .en  (stick_int_en[0]),
5436
    .clk (clk),
5437
    .se  (se),
5438 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5439 95 fafa1971
    .so  ()
5440
);
5441
//
5442 113 albert.wat
dffre_s dffre_stick_int1 (
5443 95 fafa1971
    .din (stick_int_din[1]),
5444
    .q   (tlu_stick_int[1]),
5445
    .rst (local_rst),
5446
    .en  (stick_int_en[1]),
5447
    .clk (clk),
5448
    .se  (se),
5449 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5450 95 fafa1971
    .so  ()
5451
);
5452
//
5453 113 albert.wat
dffre_s dffre_stick_int2  (
5454 95 fafa1971
    .din (stick_int_din[2]),
5455
    .q   (tlu_stick_int[2]),
5456
    .rst (local_rst),
5457
    .en  (stick_int_en[2]),
5458
    .clk (clk),
5459
    .se  (se),
5460 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5461 95 fafa1971
    .so ()
5462
);
5463
//
5464 113 albert.wat
dffre_s dffre_stick_int3 (
5465 95 fafa1971
    .din (stick_int_din[3]),
5466
    .q   (tlu_stick_int[3]),
5467
    .rst (local_rst),
5468
    .en  (stick_int_en[3]),
5469
    .clk (clk),
5470
    .se  (se),
5471 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5472 95 fafa1971
    .so  ()
5473
);
5474
// modified for hypervisor support
5475
//
5476
assign  tlu_sftint_lvl14_all[0] =
5477
            tlu_sftint_lvl14[0] | tlu_tick_int[0] | tlu_stick_int[0];
5478
assign  tlu_sftint_lvl14_all[1] =
5479
            tlu_sftint_lvl14[1] | tlu_tick_int[1] | tlu_stick_int[1];
5480
assign  tlu_sftint_lvl14_all[2] =
5481
            tlu_sftint_lvl14[2] | tlu_tick_int[2] | tlu_stick_int[2];
5482
assign  tlu_sftint_lvl14_all[3] =
5483
            tlu_sftint_lvl14[3] | tlu_tick_int[3] | tlu_stick_int[3];
5484
//
5485
assign  tlu_sftint_lvl14_int[0] = tickcmp_int[0] | stickcmp_int[0];
5486
assign  tlu_sftint_lvl14_int[1] = tickcmp_int[1] | stickcmp_int[1];
5487
assign  tlu_sftint_lvl14_int[2] = tickcmp_int[2] | stickcmp_int[2];
5488
assign  tlu_sftint_lvl14_int[3] = tickcmp_int[3] | stickcmp_int[3];
5489
*/
5490
 
5491
//=========================================================================================
5492
//      PIL for Threads
5493
//=========================================================================================
5494
 
5495
assign  pil0_en = pil_rw_g & wsr_inst_g & thread0_wsel_g;
5496
assign  pil1_en = pil_rw_g & wsr_inst_g & thread1_wsel_g;
5497
assign  pil2_en = pil_rw_g & wsr_inst_g & thread2_wsel_g;
5498
assign  pil3_en = pil_rw_g & wsr_inst_g & thread3_wsel_g;
5499
 
5500
// THREAD 0
5501 113 albert.wat
dffe_s #(4) dffe_pil0 (
5502 95 fafa1971
    .din (tlu_wsr_data_w[3:0]),
5503
    .q   (true_pil0[3:0]),
5504
    .en  (pil0_en),
5505
    .clk (clk),
5506
    .se  (se),
5507 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5508 95 fafa1971
    .so  ()
5509
);
5510
// 
5511
// THREAD 1
5512 113 albert.wat
dffe_s #(4) dffe_pil1 (
5513 95 fafa1971
    .din (tlu_wsr_data_w[3:0]),
5514
    .q   (true_pil1[3:0]),
5515
    .en  (pil1_en),
5516
    .clk (clk),
5517
    .se  (se),
5518 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5519 95 fafa1971
    .so  ()
5520
);
5521
// 
5522
// THREAD 2
5523 113 albert.wat
dffe_s #(4) dffe_pil2 (
5524 95 fafa1971
    .din (tlu_wsr_data_w[3:0]),
5525
    .q   (true_pil2[3:0]),
5526
    .en  (pil2_en),
5527
    .clk (clk),
5528
    .se  (se),
5529 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5530 95 fafa1971
    .so  ()
5531
);
5532
//
5533
// THREAD 3
5534 113 albert.wat
dffe_s #(4) dffe_pil3 (
5535 95 fafa1971
    .din (tlu_wsr_data_w[3:0]),
5536
    .q   (true_pil3[3:0]),
5537
    .en  (pil3_en),
5538
    .clk (clk),
5539
    .se  (se),
5540 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5541 95 fafa1971
    .so  ()
5542
);
5543
 
5544
//=========================================================================================
5545
//      TL for Threads
5546
//=========================================================================================
5547
//
5548 113 albert.wat
dff_s dff_stgim_g (
5549 95 fafa1971
    .din (ifu_tlu_immu_miss_m),
5550
    .q  (immu_miss_g),
5551
    .clk (clk),
5552
    .se  (se),
5553 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5554 95 fafa1971
    .so  ()
5555
);
5556
 
5557
// wrpr supplies new value else increment on trap.
5558
// wrpr %tl when tl=0 will cause a trap.
5559
// trap in MAXTL-1 enters RED_MODE. 
5560
// added for hypervisor support
5561
// capped the tl value by supervisor write at MAXSTL 
5562
//
5563
assign maxstl_wr_sel[0] =
5564 113 albert.wat
           ~tlu_hyper_lite[0] & (tlu_wsr_data_w[2:0] > `MAXSTL);
5565 95 fafa1971
assign maxstl_wr_sel[1] =
5566 113 albert.wat
           ~tlu_hyper_lite[1] & (tlu_wsr_data_w[2:0] > `MAXSTL);
5567 95 fafa1971
assign maxstl_wr_sel[2] =
5568 113 albert.wat
           ~tlu_hyper_lite[2] & (tlu_wsr_data_w[2:0] > `MAXSTL);
5569 95 fafa1971
assign maxstl_wr_sel[3] =
5570 113 albert.wat
           ~tlu_hyper_lite[3] & (tlu_wsr_data_w[2:0] > `MAXSTL);
5571 95 fafa1971
 
5572
assign maxtl_wr_sel =  (tlu_wsr_data_w[2:0] == 3'b111);
5573
 
5574
// THREAD0
5575
// Use to signal page fault for now.
5576
// sync_trap_taken_g already qualified with inst_vld_g.
5577
// long-latency sparc traps have to be killed in own pipeline
5578
// hwint interrupts are qualified elsewhere
5579
// modified due to timing
5580
// modified for bug 4561
5581
assign thrd0_traps =
5582
            (sync_trap_taken_g & thread0_rsel_g) |
5583
            (pending_trap_sel[0] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
5584
             ifu_thrd_flush_w[0] | cwp_cmplt0_pending | sync_trap_taken_g |
5585
            (tlu_gl_rw_g & wsr_inst_g)));
5586
//
5587
// trap level will get updated next cycle.
5588 113 albert.wat
dff_s #(1) dff_stgw2_0 (
5589 95 fafa1971
    .din (thrd0_traps),
5590
    .q   (thrd0_traps_w2),
5591
    .clk (clk),
5592
    .se  (se),
5593 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5594 95 fafa1971
    .so  ()
5595
);
5596
 
5597
assign tlu_thrd_traps_w2[0] = thrd0_traps_w2;
5598
 
5599 113 albert.wat
assign  trp_lvl0_at_maxtl = (trp_lvl0[2:0] == `MAXTL);
5600
assign  trp_lvl0_at_maxtlless1 = (trp_lvl0[2:0] == `MAXTL_LESSONE);
5601 95 fafa1971
//
5602
// added for modified for hypervisor support
5603 113 albert.wat
assign trp_lvl_at_maxstl[0]   = (trp_lvl0[2:0] == `MAXSTL);
5604
assign trp_lvl_gte_maxstl[0]  = (trp_lvl0[2:0] > `MAXSTL) | trp_lvl_at_maxstl[0];
5605 95 fafa1971
assign wsr_trp_lvl0_data_w[2:0] =
5606 113 albert.wat
           (maxstl_wr_sel[0])? `MAXSTL_TL:
5607
           ((maxtl_wr_sel)? `MAXTL: tlu_wsr_data_w[2:0]);
5608 95 fafa1971
//
5609
// added for timing
5610 113 albert.wat
dff_s #(3) dff_wsr_trp_lvl0_data_w2 (
5611 95 fafa1971
    .din (wsr_trp_lvl0_data_w[2:0]),
5612
    .q   (wsr_trp_lvl0_data_w2[2:0]),
5613
    .clk (clk),
5614
    .se  (se),
5615 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5616 95 fafa1971
    .so  ()
5617
);
5618
 
5619
//=========================================================================================
5620
// The following section has been recoded due to timing
5621
//=========================================================================================
5622
// trap level to be incremented if thread not at MAXTL and not in redmode
5623
assign  trp_lvl0_incr_w2 = thrd0_traps_w2 & ~trp_lvl0_at_maxtl;
5624
 
5625
assign trp_lvl0_new[2:0] =
5626
           (tl_rw_w2 & wsr_inst_w2 & thread0_wsel_w2) ?
5627
                        wsr_trp_lvl0_data_w2[2:0] :
5628 113 albert.wat
                        (local_rst | por_rstint0_w2) ? `MAXTL :
5629 95 fafa1971
                        (dnrtry_inst_w2[0]) ?
5630
                                trp_lvl0[2:0] - 3'b001:// done/retry decrements
5631
                                trp_lvl0[2:0] + {2'b00,trp_lvl0_incr_w2};// trap increments
5632
assign tl0_en =
5633
           (tl_rw_w2 & wsr_inst_w2 & thread0_wsel_w2) |
5634
                        trp_lvl0_incr_w2| local_rst | por_rstint0_w2 |
5635
            dnrtry_inst_w2[0];
5636
 
5637
// Reset required as processor will start out at tl0 after reset.
5638
// tl has to be correctly defined for all conditions !!!
5639 113 albert.wat
dffe_s #(3) dffe_tl0 (
5640 95 fafa1971
    .din (trp_lvl0_new[2:0]),
5641
    .q   (trp_lvl0[2:0]),
5642
    .en  (tl0_en),
5643
    .clk (clk),
5644
    .se  (se),
5645 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5646 95 fafa1971
    .so  ()
5647
);
5648
assign  tlu_lsu_tl_zero[0] = ~trp_lvl0[2] & ~trp_lvl0[1] & ~trp_lvl0[0];
5649
assign  tl0_gt_0 = trp_lvl0[2] | trp_lvl0[1] | trp_lvl0[0];
5650
//
5651
// THREAD1
5652
// Use to signal page fault for now.
5653
// sync_trap_taken_g already qualified with inst_vld_g.
5654
// long-latency sparc traps have to be killed in own pipeline
5655
// hwint interrupts are qualified elsewhere
5656
// modified due to timing
5657
assign thrd1_traps =
5658
            (sync_trap_taken_g & thread1_rsel_g ) |
5659
            (pending_trap_sel[1] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
5660
             ifu_thrd_flush_w[1] | cwp_cmplt1_pending | sync_trap_taken_g |
5661
            (tlu_gl_rw_g & wsr_inst_g)));
5662
//
5663
// trap level will get updated next cycle.
5664 113 albert.wat
dff_s #(1) dff_stgw2_1 (
5665 95 fafa1971
    .din (thrd1_traps),
5666
    .q  (thrd1_traps_w2),
5667
    .clk (clk),
5668
    .se  (se),
5669 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5670 95 fafa1971
    .so ()
5671
);
5672
 
5673
assign tlu_thrd_traps_w2[1] = thrd1_traps_w2;
5674
 
5675 113 albert.wat
assign  trp_lvl1_at_maxtl = (trp_lvl1[2:0] == `MAXTL);
5676
assign  trp_lvl1_at_maxtlless1 = (trp_lvl1[2:0] == `MAXTL_LESSONE);
5677 95 fafa1971
//
5678
// added for modified for hypervisor support
5679 113 albert.wat
assign trp_lvl_at_maxstl[1]   = (trp_lvl1[2:0] == `MAXSTL);
5680
assign trp_lvl_gte_maxstl[1]  = (trp_lvl1[2:0] > `MAXSTL) | trp_lvl_at_maxstl[1];
5681 95 fafa1971
assign wsr_trp_lvl1_data_w[2:0] =
5682 113 albert.wat
           (maxstl_wr_sel[1])? `MAXSTL_TL:
5683
           ((maxtl_wr_sel)? `MAXTL: tlu_wsr_data_w[2:0]);
5684 95 fafa1971
//
5685
// added for timing
5686 113 albert.wat
dff_s #(3) dff_wsr_trp_lvl1_data_w2 (
5687 95 fafa1971
    .din (wsr_trp_lvl1_data_w[2:0]),
5688
    .q   (wsr_trp_lvl1_data_w2[2:0]),
5689
    .clk (clk),
5690
    .se  (se),
5691 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5692 95 fafa1971
    .so  ()
5693
);
5694
 
5695
//=========================================================================================
5696
// The following section has been recoded due to timing
5697
//=========================================================================================
5698
// trap level to be incremented if thread not at MAXTL and not in redmode
5699
assign  trp_lvl1_incr_w2 = thrd1_traps_w2 & ~trp_lvl1_at_maxtl;
5700
 
5701
assign trp_lvl1_new[2:0] =
5702
           (tl_rw_w2 & wsr_inst_w2 & thread1_wsel_w2) ?
5703
                        wsr_trp_lvl1_data_w2[2:0] :
5704 113 albert.wat
                        (local_rst | por_rstint1_w2) ? `MAXTL :
5705 95 fafa1971
                        (dnrtry_inst_w2[1]) ?
5706
                                trp_lvl1[2:0] - 3'b001:// done/retry decrements
5707
                                trp_lvl1[2:0] + {2'b00,trp_lvl1_incr_w2};// trap increments
5708
assign tl1_en =
5709
           (tl_rw_w2 & wsr_inst_w2 & thread1_wsel_w2) |
5710
                        trp_lvl1_incr_w2| local_rst | por_rstint1_w2 |
5711
            dnrtry_inst_w2[1];
5712
 
5713
// Reset required as processor will start out at tl1 after reset.
5714
// tl has to be correctly defined for all conditions !!!
5715 113 albert.wat
dffe_s #(3) dffe_tl1 (
5716 95 fafa1971
    .din (trp_lvl1_new[2:0]),
5717
    .q   (trp_lvl1[2:0]),
5718
    .en  (tl1_en),
5719
    .clk (clk),
5720
    .se  (se),
5721 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5722 95 fafa1971
    .so  ()
5723
);
5724
assign  tlu_lsu_tl_zero[1] = ~trp_lvl1[2] & ~trp_lvl1[1] & ~trp_lvl1[0];
5725
assign  tl1_gt_0 = trp_lvl1[2] | trp_lvl1[1] | trp_lvl1[0];
5726
//
5727
// THREAD2
5728
// Use to signal page fault for now.
5729
// sync_trap_taken_g already qualified with inst_vld_g.
5730
// long-latency sparc traps have to be killed in own pipeline
5731
// hwint interrupts are qualified elsewhere
5732
// modified due to timing
5733
// modified for bug 3827
5734
assign thrd2_traps =
5735
            (sync_trap_taken_g & thread2_rsel_g) |
5736
            (pending_trap_sel[2] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
5737
             ifu_thrd_flush_w[2] | cwp_cmplt2_pending | sync_trap_taken_g |
5738
             (tlu_gl_rw_g & wsr_inst_g)));
5739
 
5740
// trap level will get updated next cycle.
5741 113 albert.wat
dff_s #(1) dff_stgw2_2 (
5742 95 fafa1971
    .din (thrd2_traps),
5743
    .q   (thrd2_traps_w2),
5744
    .clk (clk),
5745
    .se  (se),
5746 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5747 95 fafa1971
    .so  ()
5748
);
5749
 
5750
assign tlu_thrd_traps_w2[2] = thrd2_traps_w2;
5751
 
5752 113 albert.wat
assign  trp_lvl2_at_maxtl = (trp_lvl2[2:0] == `MAXTL);
5753
assign  trp_lvl2_at_maxtlless1 = (trp_lvl2[2:0] == `MAXTL_LESSONE);
5754 95 fafa1971
//
5755
// added or modified for hypervisor support
5756 113 albert.wat
assign trp_lvl_at_maxstl[2]   = (trp_lvl2[2:0] == `MAXSTL);
5757
assign trp_lvl_gte_maxstl[2]  = (trp_lvl2[2:0] > `MAXSTL) | trp_lvl_at_maxstl[2];
5758 95 fafa1971
assign wsr_trp_lvl2_data_w[2:0] =
5759 113 albert.wat
           (maxstl_wr_sel[2])? `MAXSTL_TL:
5760
           ((maxtl_wr_sel)? `MAXTL: tlu_wsr_data_w[2:0]);
5761 95 fafa1971
//
5762
// added for timing
5763 113 albert.wat
dff_s #(3) dff_wsr_trp_lvl2_data_w2 (
5764 95 fafa1971
    .din (wsr_trp_lvl2_data_w[2:0]),
5765
    .q   (wsr_trp_lvl2_data_w2[2:0]),
5766
    .clk (clk),
5767
    .se  (se),
5768 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5769 95 fafa1971
    .so  ()
5770
);
5771
 
5772
//=========================================================================================
5773
// The following section has been recoded due to timing
5774
//=========================================================================================
5775
// trap level to be incremented if thread not at MAXTL and not in redmode
5776
assign  trp_lvl2_incr_w2 = thrd2_traps_w2 & ~trp_lvl2_at_maxtl;
5777
 
5778
assign trp_lvl2_new[2:0] =
5779
           (tl_rw_w2 & wsr_inst_w2 & thread2_wsel_w2) ?
5780
                        wsr_trp_lvl2_data_w2[2:0] :
5781 113 albert.wat
                        (local_rst | por_rstint2_w2) ? `MAXTL :
5782 95 fafa1971
                        (dnrtry_inst_w2[2]) ?
5783
                                trp_lvl2[2:0] - 3'b001:// done/retry decrements
5784
                                trp_lvl2[2:0] + {2'b00,trp_lvl2_incr_w2};// trap increments
5785
assign tl2_en =
5786
           (tl_rw_w2 & wsr_inst_w2 & thread2_wsel_w2) |
5787
                        trp_lvl2_incr_w2| local_rst | por_rstint2_w2 |
5788
            dnrtry_inst_w2[2];
5789
 
5790
// Reset required as processor will start out at tl1 after reset.
5791
// tl has to be correctly defined for all conditions !!!
5792 113 albert.wat
dffe_s #(3) dffe_tl2 (
5793 95 fafa1971
    .din (trp_lvl2_new[2:0]),
5794
    .q   (trp_lvl2[2:0]),
5795
    .en  (tl2_en),
5796
    .clk (clk),
5797
    .se  (se),
5798 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5799 95 fafa1971
    .so  ()
5800
);
5801
assign  tlu_lsu_tl_zero[2] = ~trp_lvl2[2] & ~trp_lvl2[1] & ~trp_lvl2[0];
5802
assign  tl2_gt_0 = trp_lvl2[2] | trp_lvl2[1] | trp_lvl2[0];
5803
//
5804
// THREAD3
5805
// Use to signal page fault for now.
5806
// sync_trap_taken_g already qualified with inst_vld_g.
5807
// long-latency sparc traps have to be killed in own pipeline
5808
// hwint interrupts are qualified elsewhere
5809
// modified due to timing
5810
assign thrd3_traps =
5811
            (sync_trap_taken_g & thread3_rsel_g) |
5812
            (pending_trap_sel[3] & ~(dnrtry_inst_g | tsa_wr_tid_sel_g |
5813
             ifu_thrd_flush_w[3] | cwp_cmplt3_pending | sync_trap_taken_g |
5814
            (tlu_gl_rw_g & wsr_inst_g)));
5815
 
5816
// trap level will get updated next cycle.
5817 113 albert.wat
dff_s #(1) dff_stgw2_3 (
5818 95 fafa1971
    .din (thrd3_traps),
5819
    .q   (thrd3_traps_w2),
5820
    .clk (clk),
5821
    .se  (se),
5822 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5823 95 fafa1971
    .so ()
5824
);
5825
 
5826
assign tlu_thrd_traps_w2[3] = thrd3_traps_w2;
5827
 
5828 113 albert.wat
assign  trp_lvl3_at_maxtl = (trp_lvl3[2:0] == `MAXTL);
5829
assign  trp_lvl3_at_maxtlless1 = (trp_lvl3[2:0] == `MAXTL_LESSONE);
5830 95 fafa1971
//
5831
// added for modified for hypervisor support
5832 113 albert.wat
assign trp_lvl_at_maxstl[3]   = (trp_lvl3[2:0] == `MAXSTL);
5833
assign trp_lvl_gte_maxstl[3]  = (trp_lvl3[2:0] > `MAXSTL) | trp_lvl_at_maxstl[3];
5834 95 fafa1971
assign wsr_trp_lvl3_data_w[2:0] =
5835 113 albert.wat
           (maxstl_wr_sel[3])? `MAXSTL_TL:
5836
           ((maxtl_wr_sel)? `MAXTL: tlu_wsr_data_w[2:0]);
5837 95 fafa1971
//
5838
// added for timing
5839 113 albert.wat
dff_s #(3) dff_wsr_trp_lvl3_data_w2 (
5840 95 fafa1971
    .din (wsr_trp_lvl3_data_w[2:0]),
5841
    .q   (wsr_trp_lvl3_data_w2[2:0]),
5842
    .clk (clk),
5843
    .se  (se),
5844 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5845 95 fafa1971
    .so  ()
5846
);
5847
 
5848
//=========================================================================================
5849
// The following section has been recoded due to timing
5850
//=========================================================================================
5851
// trap level to be incremented if thread not at MAXTL and not in redmode
5852
assign  trp_lvl3_incr_w2 = thrd3_traps_w2 & ~trp_lvl3_at_maxtl;
5853
 
5854
assign trp_lvl3_new[2:0] =
5855
           (tl_rw_w2 & wsr_inst_w2 & thread3_wsel_w2) ?
5856
                        wsr_trp_lvl3_data_w2[2:0] :
5857 113 albert.wat
                        (local_rst | por_rstint3_w2) ? `MAXTL :
5858 95 fafa1971
                        (dnrtry_inst_w2[3]) ?
5859
                                trp_lvl3[2:0] - 3'b001:// done/retry decrements
5860
                                trp_lvl3[2:0] + {2'b00,trp_lvl3_incr_w2};// trap increments
5861
 
5862
assign tl3_en =
5863
           (tl_rw_w2 & wsr_inst_w2 & thread3_wsel_w2) |
5864
                        trp_lvl3_incr_w2| local_rst | por_rstint3_w2 |
5865
            dnrtry_inst_w2[3];
5866
 
5867
// Reset required as processor will start out at tl1 after reset.
5868 113 albert.wat
dffe_s #(3) dffe_tl3 (
5869 95 fafa1971
    .din (trp_lvl3_new[2:0]),
5870
    .q   (trp_lvl3[2:0]),
5871
    .en  (tl3_en),
5872
    .clk (clk),
5873
    .se  (se),
5874 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5875 95 fafa1971
    .so  ()
5876
);
5877
assign  tlu_lsu_tl_zero[3] = ~trp_lvl3[2] & ~trp_lvl3[1] & ~trp_lvl3[0];
5878
assign  tl3_gt_0 = trp_lvl3[2] | trp_lvl3[1] | trp_lvl3[0];
5879
//
5880
// added for hypervisor support - TLZ trap
5881
// detection of transition of trap-level from <> 0 to 0
5882
// modified for bug 3192
5883
 
5884
assign tlz_thread_set[0] = ~(tlu_lsu_tl_zero[0] | (|(trp_lvl0_new[2:0]))) & tl0_en;
5885
assign tlz_thread_set[1] = ~(tlu_lsu_tl_zero[1] | (|(trp_lvl1_new[2:0]))) & tl1_en;
5886
assign tlz_thread_set[2] = ~(tlu_lsu_tl_zero[2] | (|(trp_lvl2_new[2:0]))) & tl2_en;
5887
assign tlz_thread_set[3] = ~(tlu_lsu_tl_zero[3] | (|(trp_lvl3_new[2:0]))) & tl3_en;
5888
 
5889 113 albert.wat
dff_s #(`TLU_THRD_NUM) dff_tlz_thread_data (
5890
    .din (tlz_thread_set[`TLU_THRD_NUM-1:0]),
5891
        .q   (tlz_thread_data[`TLU_THRD_NUM-1:0]),
5892 95 fafa1971
    .clk (clk),
5893
    .se  (se),
5894 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5895 95 fafa1971
    .so  ()
5896
);
5897
 
5898
//
5899
// storing the state of the tlz trap to take the trap on the next valid
5900
// instruction 
5901
// modified for bug 3646
5902 113 albert.wat
dffre_s dffr_tlz_thread_0  (
5903 95 fafa1971
    .din (tlz_thread_data[0]),
5904
    .q   (tlz_thread[0]),
5905
    .rst (local_rst | tlz_trap_g[0] | thread_inst_vld_g[0]),
5906
    .en  (tlz_thread_data[0] & tlu_hpstate_tlz[0]),
5907
    .clk (clk),
5908
    .se  (se),
5909 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5910 95 fafa1971
    .so  ()
5911
);
5912
 
5913 113 albert.wat
dffre_s dffr_tlz_thread_1  (
5914 95 fafa1971
    .din (tlz_thread_data[1]),
5915
    .q   (tlz_thread[1]),
5916
    .rst (local_rst | tlz_trap_g[1] | thread_inst_vld_g[1]),
5917
    .en  (tlz_thread_data[1] & tlu_hpstate_tlz[1]),
5918
    .clk (clk),
5919
    .se  (se),
5920 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5921 95 fafa1971
    .so  ()
5922
);
5923
 
5924 113 albert.wat
dffre_s dffr_tlz_thread_2  (
5925 95 fafa1971
    .din (tlz_thread_data[2]),
5926
    .q   (tlz_thread[2]),
5927
    .rst (local_rst | tlz_trap_g[2] | thread_inst_vld_g[2]),
5928
    .en  (tlz_thread_data[2] & tlu_hpstate_tlz[2]),
5929
    .clk (clk),
5930
    .se  (se),
5931 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5932 95 fafa1971
    .so  ()
5933
);
5934
 
5935 113 albert.wat
dffre_s dffr_tlz_thread_3  (
5936 95 fafa1971
    .din (tlz_thread_data[3]),
5937
    .q   (tlz_thread[3]),
5938
    .rst (local_rst | tlz_trap_g[3] | thread_inst_vld_g[3]),
5939
    .en  (tlz_thread_data[3] & tlu_hpstate_tlz[3]),
5940
    .clk (clk),
5941
    .se  (se),
5942 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5943 95 fafa1971
    .so  ()
5944
);
5945
//
5946
// initiate the trap for the appropriate thread
5947
// modified for bug 4434 & 4758
5948
assign tlz_trap_m[0] =
5949
          ~ifu_rstint_m &
5950
          // ~(ifu_rstint_m | (ifu_hwint_m  & tlu_int_pstate_ie[0])) & 
5951
            inst_vld_m & tlu_lsu_tl_zero[0] & thread0_rsel_m & tlz_thread[0] &
5952
          ~tlu_hpstate_priv[0] & tlu_hpstate_tlz[0];
5953
assign tlz_trap_m[1] =
5954
          ~ifu_rstint_m &
5955
          // ~(ifu_rstint_m | (ifu_hwint_m & tlu_int_pstate_ie[1])) & 
5956
            inst_vld_m & tlu_lsu_tl_zero[1] & thread1_rsel_m & tlz_thread[1] &
5957
          ~tlu_hpstate_priv[1] & tlu_hpstate_tlz[1];
5958
assign tlz_trap_m[2] =
5959
          ~ifu_rstint_m &
5960
          // ~(ifu_rstint_m | (ifu_hwint_m & tlu_int_pstate_ie[2])) & 
5961
            inst_vld_m & tlu_lsu_tl_zero[2] & thread2_rsel_m & tlz_thread[2] &
5962
          ~tlu_hpstate_priv[2] & tlu_hpstate_tlz[2];
5963
assign tlz_trap_m[3] =
5964
          ~ifu_rstint_m &
5965
          // ~(ifu_rstint_m | (ifu_hwint_m & tlu_int_pstate_ie[3])) & 
5966
            inst_vld_m & tlu_lsu_tl_zero[3] & thread3_rsel_m & tlz_thread[3] &
5967
          ~tlu_hpstate_priv[3] & tlu_hpstate_tlz[3];
5968
//
5969
// added for timing - modifed to removed the qualification of the interrupts from
5970
// IFU
5971
assign tlz_exu_trap_m[0] =
5972
            tlu_lsu_tl_zero[0] & thread0_rsel_m & tlz_thread[0] & ~tlu_hpstate_priv[0] &
5973
            tlu_hpstate_tlz[0];
5974
assign tlz_exu_trap_m[1] =
5975
            tlu_lsu_tl_zero[1] & thread1_rsel_m & tlz_thread[1] & ~tlu_hpstate_priv[1] &
5976
            tlu_hpstate_tlz[1];
5977
assign tlz_exu_trap_m[2] =
5978
            tlu_lsu_tl_zero[2] & thread2_rsel_m & tlz_thread[2] & ~tlu_hpstate_priv[2] &
5979
            tlu_hpstate_tlz[2];
5980
assign tlz_exu_trap_m[3] =
5981
            tlu_lsu_tl_zero[3] & thread3_rsel_m & tlz_thread[3] & ~tlu_hpstate_priv[3] &
5982
            tlu_hpstate_tlz[3];
5983
//
5984
// modified for bug 4862
5985
// indicate that a TLZ trap needs to be taken
5986 113 albert.wat
dffr_s #(`TLU_THRD_NUM) dffr_tlz_trap_g  (
5987
    .din (tlz_trap_m[`TLU_THRD_NUM-1:0]),
5988
    .q   (tlz_trap_nq_g[`TLU_THRD_NUM-1:0]),
5989 95 fafa1971
    .rst (local_rst),
5990
    .clk (clk),
5991
    .se  (se),
5992 113 albert.wat
    `SIMPLY_RISC_SCANIN,
5993 95 fafa1971
    .so  ()
5994
);
5995
 
5996
assign tlz_trap_g[0] = tlz_trap_nq_g[0] & ~inst_ifu_flush2_w;
5997
assign tlz_trap_g[1] = tlz_trap_nq_g[1] & ~inst_ifu_flush2_w;
5998
assign tlz_trap_g[2] = tlz_trap_nq_g[2] & ~inst_ifu_flush2_w;
5999
assign tlz_trap_g[3] = tlz_trap_nq_g[3] & ~inst_ifu_flush2_w;
6000
 
6001
//=========================================================================================
6002
//      EXCEPTION HANDLING
6003
//=========================================================================================
6004
// modified to test out timing - 
6005
/*
6006
assign  tlu_ifu_flush_pipe_w =
6007
        (thrd0_traps_flush | thrd1_traps_flush | thrd2_traps_flush | thrd3_traps_flush) &
6008
     inst_vld_g;
6009
//
6010
assign  tlu_ifu_flush_pipe_w =
6011
            (dside_sync_trap_g & inst_vld_g) | local_early_flush_pipe_w;
6012
*/
6013
assign tlu_ifu_flush_pipe_w =
6014
           (early_dside_trap_g & inst_vld_g) | lsu_tlu_defr_trp_taken_g |
6015
            local_early_flush_pipe_w | lsu_ttype_vld_w;
6016
           // modified for bug 4561
6017
           // (lsu_defr_trap_g & (thrid_g[1:0] == thrid_w2[1:0]))  |
6018
 
6019
//
6020
// modified for timing fix
6021
assign tlu_flush_all_w =
6022
           inst_ifu_flush_w | local_early_flush_pipe_w |
6023
           (lsu_tlu_early_flush_w & inst_vld_nf_g);
6024
 
6025
 
6026
// staging the all flush signal 
6027 113 albert.wat
dffr_s dffr_tlu_flush_all_w2 (
6028 95 fafa1971
    .din (tlu_flush_all_w),
6029
    .q   (tlu_flush_all_w2),
6030
    .rst (local_rst),
6031
    .clk (clk),
6032
    .se  (se),
6033 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6034 95 fafa1971
    .so  ()
6035
);
6036
//
6037
// added for timing
6038
assign lsu_ttype_vld_w =
6039
           lsu_tlu_ttype_vld_m2 & inst_vld_g;
6040
// 
6041
// staging the flush-pipe signal 
6042 113 albert.wat
dffr_s dffr_lsu_ttype_vld_w2 (
6043 95 fafa1971
    .din (lsu_ttype_vld_w),
6044
    .q   (lsu_ttype_vld_w2),
6045
    .rst (local_rst),
6046
    .clk (clk),
6047
    .se  (se),
6048 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6049 95 fafa1971
    .so  ()
6050
);
6051
 
6052
assign  tlu_flush_pipe_w = tlu_ifu_flush_pipe_w;
6053
//
6054
// added for timing 
6055
assign  tlu_full_flush_pipe_w2 =
6056
            lsu_ttype_vld_w2 | tlu_flush_all_w2;
6057
 
6058
// added for early flush pipe timing fix
6059
// assign tlu_early_flush_pipe_m = sync_trap_taken_m;  
6060
 
6061
assign tlu_local_flush_w          = local_early_flush_pipe_w;
6062
assign tlu_early_flush_pipe2_w    = local_early_flush_pipe2_w;
6063
assign tlu_exu_early_flush_pipe_w = local_early_flush_pipe3_w;
6064
assign tlu_early_flush_pipe_w     = local_early_flush_pipe4_w;
6065
 
6066
// added local early flush pipe timing fix
6067
 
6068 113 albert.wat
dffr_s dffr_local_early_flush_pipe_w (
6069 95 fafa1971
    .din (sync_trap_taken_m),
6070
    .q   (local_early_flush_pipe_w),
6071
    .rst (local_rst),
6072
    .clk (clk),
6073
    .se  (se),
6074 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6075 95 fafa1971
    .so ()
6076
);
6077
 
6078 113 albert.wat
dffr_s dffr_local_early_flush_pipe2_w (
6079 95 fafa1971
    .din (sync_trap_taken_m),
6080
    .q   (local_early_flush_pipe2_w),
6081
    .rst (local_rst),
6082
    .clk (clk),
6083
    .se  (se),
6084 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6085 95 fafa1971
    .so ()
6086
);
6087
 
6088 113 albert.wat
dffr_s dffr_local_early_flush_pipe3_w (
6089 95 fafa1971
    .din (sync_trap_taken_m),
6090
    .q   (local_early_flush_pipe3_w),
6091
    .rst (local_rst),
6092
    .clk (clk),
6093
    .se  (se),
6094 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6095 95 fafa1971
    .so ()
6096
);
6097
 
6098 113 albert.wat
dffr_s dffr_local_early_flush_pipe4_w (
6099 95 fafa1971
    .din (sync_trap_taken_m),
6100
    .q   (local_early_flush_pipe4_w),
6101
    .rst (local_rst),
6102
    .clk (clk),
6103
    .se  (se),
6104 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6105 95 fafa1971
    .so ()
6106
);
6107
 
6108
//=========================================================================================
6109
//      SFSR/SFAR HANDLING
6110
//=========================================================================================
6111
 
6112
assign thread_tl_zero =
6113
        thread0_rsel_e ? tlu_lsu_tl_zero[0] :
6114
                thread1_rsel_e ? tlu_lsu_tl_zero[1] :
6115
                        thread2_rsel_e ? tlu_lsu_tl_zero[2] : tlu_lsu_tl_zero[3];
6116
 
6117
// Generate selects for ctxt to be written to tag_access
6118
// iside trap meant to cover immu_miss and inst_access_excp
6119
// modified for hypervisor support
6120
// assign       iside_trap = exu_tlu_ttype_vld_m | immu_va_oor_brnchetc_m | exu_tlu_va_oor_jl_ret_m;
6121
// removed for timing 
6122
/*
6123
assign  iside_trap =
6124
            ifu_tlu_immu_miss_m | exu_tlu_ttype_vld_m |
6125
            immu_va_oor_brnchetc_m | exu_tlu_va_oor_jl_ret_m ;
6126
 
6127
assign  tlu_tag_access_ctxt_sel_m[0] = iside_trap &  thread_tl_zero_m;
6128
assign  tlu_tag_access_ctxt_sel_m[1] = iside_trap & ~thread_tl_zero_m;
6129
assign  tlu_tag_access_ctxt_sel_m[2] = ~iside_trap;
6130
*/
6131
 
6132
// ISFSR
6133
 
6134
// voor reported for both ifetch and memref - need to distinguish.
6135
// va-out-of-range for ldst,branch,call,sequential 
6136
// modified for bug 4763
6137
// assign       immu_va_oor_brnchetc_m
6138
//      = exu_tlu_va_oor_m & ~pstate_am & ~memref_m;
6139
 
6140 113 albert.wat
dffr_s dffr_immu_va_oor_brnchetc_m (
6141 95 fafa1971
    .din (ifu_tlu_pc_oor_e),
6142
    .q   (immu_va_oor_brnchetc_m),
6143
    .rst (local_rst),
6144
    .clk (clk),
6145
    .se  (se),
6146 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6147 95 fafa1971
    .so  ()
6148
);
6149
 
6150 113 albert.wat
dff_s dff_memref_e (
6151 95 fafa1971
    .din (ifu_lsu_memref_d),
6152
    .q   (memref_e),
6153
    .clk (clk),
6154
    .se  (se),
6155 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6156 95 fafa1971
    .so ()
6157
);
6158
 
6159
 
6160 113 albert.wat
dff_s dff_memref_m (
6161 95 fafa1971
    .din (memref_e),// ifu_tlu_flsh_inst_e
6162
    .q   (memref_m),// flsh_inst_m
6163
    .clk (clk),
6164
    .se  (se),
6165 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6166 95 fafa1971
    .so  ()
6167
);
6168
 
6169
assign isfsr_flt_vld_m =
6170
        (thread0_rsel_m & tlu_isfsr_flt_vld[0]) |
6171
        (thread1_rsel_m & tlu_isfsr_flt_vld[1]) |
6172
        (thread2_rsel_m & tlu_isfsr_flt_vld[2]) |
6173
        (thread3_rsel_m & tlu_isfsr_flt_vld[3]);
6174
 
6175
assign tlu_lsu_pstate_am[3:0] = tlu_pstate_am[3:0];
6176
 
6177
assign  pstate_am =
6178
        (thread0_rsel_m & tlu_pstate_am[0]) |
6179
        (thread1_rsel_m & tlu_pstate_am[1]) |
6180
        (thread2_rsel_m & tlu_pstate_am[2]) |
6181
        (thread3_rsel_m & tlu_pstate_am[3]);
6182
 
6183 113 albert.wat
dff_s #(1) dff_am_stgg (
6184 95 fafa1971
    .din (pstate_am),
6185
    .q   (tlu_addr_msk_g),
6186
    .clk (clk),
6187
    .se  (se),
6188 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6189 95 fafa1971
    .so  ()
6190
);
6191
//
6192
// logic moved to lsu_expctl due to timing
6193
/*
6194
assign  pstate_priv =
6195
        (thread0_rsel_m & tlu_pstate_priv[0]) |
6196
        (thread1_rsel_m & tlu_pstate_priv[1]) |
6197
        (thread2_rsel_m & tlu_pstate_priv[2]) |
6198
        (thread3_rsel_m & tlu_pstate_priv[3]);
6199
*/
6200
 
6201
 
6202
assign trp_lvl_zero =
6203
        (thread0_rsel_g & tlu_lsu_tl_zero[0]) |
6204
        (thread1_rsel_g & tlu_lsu_tl_zero[1]) |
6205
        (thread2_rsel_g & tlu_lsu_tl_zero[2]) |
6206
        (thread3_rsel_g & tlu_lsu_tl_zero[3]);
6207
 
6208
assign  isfsr_ftype_sel[0] =  ifu_tlu_priv_violtn_m;
6209
// The 2 out of range exceptions are mutex as they are based on inst type.
6210
assign  isfsr_ftype_sel[1] = ~isfsr_ftype_sel[0] & immu_va_oor_brnchetc_m;
6211
// modified for bug 4452
6212
assign isfsr_ftype_sel[2] =
6213
           ~isfsr_ftype_sel[0] & exu_tlu_va_oor_jl_ret_m &
6214
           ~(exu_tlu_ttype_vld_m | ifu_tlu_ttype_vld_m) & ~pstate_am;
6215
 
6216
assign  isfsr_trp_wr_m = |isfsr_ftype_sel[2:0];
6217
 
6218 113 albert.wat
dff_s #(1) dff_isfsrw_stgg (
6219 95 fafa1971
        .din (isfsr_trp_wr_m),
6220
        .q   (isfsr_trp_wr_g),
6221
        .clk (clk),
6222
        .se  (se),
6223 113 albert.wat
        `SIMPLY_RISC_SCANIN,
6224 95 fafa1971
        .so  ()
6225
);
6226
 
6227 113 albert.wat
dff_s #(1) dff_itag_acc_sel_g (
6228 95 fafa1971
        .din (isfsr_trp_wr_m | ifu_tlu_immu_miss_m),
6229
        .q   (itag_acc_sel_g),
6230
        .clk (clk),
6231
        .se  (se),
6232 113 albert.wat
        `SIMPLY_RISC_SCANIN,
6233 95 fafa1971
        .so ()
6234
);
6235
 
6236
assign tlu_itag_acc_sel_g = itag_acc_sel_g;
6237
 
6238
// terms below can be made common. (grape)
6239
// recoded for timing - flush qualification moved to mmu_ctl
6240
assign  immu_sfsr_trp_wr[0] =
6241
            isfsr_trp_wr_g & inst_vld_nf_g & thread0_rsel_g;
6242
assign  immu_sfsr_trp_wr[1] =
6243
            isfsr_trp_wr_g & inst_vld_nf_g & thread1_rsel_g;
6244
assign  immu_sfsr_trp_wr[2] =
6245
            isfsr_trp_wr_g & inst_vld_nf_g & thread2_rsel_g;
6246
assign  immu_sfsr_trp_wr[3] =
6247
            isfsr_trp_wr_g & inst_vld_nf_g & thread3_rsel_g;
6248
 
6249
assign  isfsr_ftype_m[6] = isfsr_ftype_sel[2];
6250
assign  isfsr_ftype_m[5] = isfsr_ftype_sel[1];
6251
assign  isfsr_ftype_m[4:1] = 4'b0000;
6252
assign  isfsr_ftype_m[0] = isfsr_ftype_sel[0];
6253
//
6254
// modified due to timing
6255 113 albert.wat
dff_s #(8) dff_isfsr_stgg (
6256 95 fafa1971
    .din ({isfsr_ftype_m[6:0],isfsr_flt_vld_m}), // pstate_priv, 
6257
        .q   ({isfsr_ftype_g[6:0],isfsr_flt_vld_g}), // pstate_priv_g,
6258
    .clk (clk),
6259
    .se  (se),
6260 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6261 95 fafa1971
    .so  ()
6262
);
6263
 
6264
// Can we remove the excessive bits in isfsr ?
6265
// Do jmpl/rtrn define the asi in i or dsfsr ? seems only jmpl_rtrn mem_addr_not_aligned
6266
// traps set the asi and that too in the dsfsr
6267
// Need to add ctxt !!!
6268
 
6269
assign isfsr_ctxt_g[1:0] =
6270
               trp_lvl_zero ? 2'b00 : 2'b10;
6271
 
6272 113 albert.wat
dff_s #(1) dff_thread_tl_zero_m (
6273 95 fafa1971
    .din (thread_tl_zero),
6274
    .q   (thread_tl_zero_m),
6275
    .clk (clk),
6276
    .se  (se),
6277 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6278 95 fafa1971
    .so ()
6279
);
6280
 
6281 113 albert.wat
dff_s #(1) dff_thread_tl_zero_g (
6282 95 fafa1971
    .din (thread_tl_zero_m),
6283
    .q   (thread_tl_zero_g),
6284
    .clk (clk),
6285
    .se  (se),
6286 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6287 95 fafa1971
    .so  ()
6288
);
6289
 
6290
assign isfsr_asi_g[7:0] =
6291
           thread_tl_zero_g ? 8'h80 : 8'h04;
6292
//
6293
// modified for bug 3323
6294
assign  tlu_isfsr_din_g[23:0] =
6295
        {isfsr_asi_g[7:0],2'b0,isfsr_ftype_g[6:0],1'b0,isfsr_ctxt_g[1:0],2'b0,isfsr_flt_vld_g,1'b1};
6296
 
6297
assign  dmmu_va_oor_m = exu_tlu_va_oor_m & ~pstate_am & memref_m & ~lsu_tlu_squash_va_oor_m;
6298
 
6299 113 albert.wat
dff_s #(3) dff_dsfsr_stgg (
6300 95 fafa1971
    .din ({dmmu_va_oor_m,// memref_m,
6301
           exu_tlu_misalign_addr_jmpl_rtn_m,
6302
               lsu_tlu_misalign_addr_ldst_atm_m}),
6303
    .q   ({dmmu_va_oor_g,
6304
               misalign_addr_jmpl_rtn_g,
6305
           misalign_addr_ldst_atm_g}),
6306
    .clk (clk),
6307
    .se  (se),
6308 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6309 95 fafa1971
    .so ()
6310
);
6311
 
6312
//=========================================================================================
6313
//      GLOBAL REGISTER SWITCHING
6314
//=========================================================================================
6315
// modified for bug 3827
6316
//
6317
assign agp_tid_sel =
6318
           (dnrtry_inst_g) | (tlu_gl_rw_g & wsr_inst_g);
6319
assign  agp_tid_g[1:0] =
6320
            agp_tid_sel ? thrid_g[1:0] : trap_tid_g[1:0];
6321
 
6322 113 albert.wat
dff_s #(2) dff_tlu_agp_tid_w2 (
6323 95 fafa1971
    .din (agp_tid_g[1:0]),
6324
    .q   (agp_tid_w2[1:0]),
6325
    .clk (clk),
6326
    .se  (se),
6327 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6328 95 fafa1971
    .so  ()
6329
);
6330
//
6331
// added for timing
6332 113 albert.wat
dff_s #(2) dff_agp_tid_w3 (
6333 95 fafa1971
    .din (agp_tid_w2[1:0]),
6334
    .q   (agp_tid_w3[1:0]),
6335
    .clk (clk),
6336
    .se  (se),
6337 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6338 95 fafa1971
    .so  ()
6339
);
6340
 
6341
assign tlu_agp_tid_w2[1:0]  = agp_tid_w2[1:0];
6342
assign tlu_exu_agp_tid[1:0] = agp_tid_w3[1:0];
6343
 
6344
//=========================================================================================
6345
//      CWP/CCR restoration
6346
//=========================================================================================
6347
// code moved to tlu_misctl
6348
/*
6349 113 albert.wat
dff_s #(8) dff_ccr_stgm (
6350 95 fafa1971
    .din (tsa_rdata_ccr[7:0]),
6351
    .q   (tlu_exu_ccr_m[7:0]),
6352
    .clk (clk),
6353
    .se  (se),
6354 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6355 95 fafa1971
    .so  ()
6356
);
6357
 
6358 113 albert.wat
dff_s #(3) dff_cwp_stgm (
6359 95 fafa1971
    .din (tsa_rdata_cwp[2:0]),
6360
    .q   (tlu_exu_cwp_m[2:0]),
6361
    .clk (clk),
6362
    .se  (se),
6363 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6364 95 fafa1971
    .so  ()
6365
);
6366
 
6367 113 albert.wat
dff_s #(8) dff_lsu_asi_m (
6368 95 fafa1971
    .din (tsa_rdata_asi[7:0]),
6369
    .q   (tlu_lsu_asi_m[7:0]),
6370
    .clk (clk),
6371
    .se  (se),
6372 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6373 95 fafa1971
    .so  ()
6374
    );
6375
*/
6376
//
6377
 
6378
assign  tlu_exu_tid_m[1:0] = thrid_m[1:0];
6379
 
6380
assign  tlu_int_tid_m[1:0] = tlu_exu_tid_m[1:0];
6381
assign  tlu_lsu_tid_m[1:0] = tlu_exu_tid_m[1:0];
6382
 
6383
// modified due to timing violations
6384
assign  tlu_lsu_asi_update_m = tlu_exu_cwpccr_update_m;
6385
 
6386
// Assumption is that this will be transmitted in the equivalent
6387
// of the w-stage from the exu.
6388
assign  cwp_cmplt0 = ~exu_tlu_cwp_cmplt_tid[1] & ~exu_tlu_cwp_cmplt_tid[0]
6389
                        & exu_tlu_cwp_cmplt;
6390
assign  cwp_cmplt1 = ~exu_tlu_cwp_cmplt_tid[1] &  exu_tlu_cwp_cmplt_tid[0]
6391
                        & exu_tlu_cwp_cmplt;
6392
assign  cwp_cmplt2 =  exu_tlu_cwp_cmplt_tid[1] & ~exu_tlu_cwp_cmplt_tid[0]
6393
                        & exu_tlu_cwp_cmplt;
6394
assign  cwp_cmplt3 =  exu_tlu_cwp_cmplt_tid[1] &  exu_tlu_cwp_cmplt_tid[0]
6395
                        & exu_tlu_cwp_cmplt;
6396
 
6397
 
6398
assign  pending_dntry0_taken = cwp_cmplt0_pending & pending_thrd0_event_taken;
6399
assign  pending_dntry1_taken = cwp_cmplt1_pending & pending_thrd1_event_taken;
6400
assign  pending_dntry2_taken = cwp_cmplt2_pending & pending_thrd2_event_taken;
6401
assign  pending_dntry3_taken = cwp_cmplt3_pending & pending_thrd3_event_taken;
6402
 
6403
// Any pending cwp change completes.
6404
// ** This equation can be optimized in terms of gate count **
6405
assign  cwp_cmplt_g =
6406
                pending_dntry0_taken | pending_dntry1_taken |
6407
                pending_dntry2_taken | pending_dntry3_taken;
6408
 
6409
// A cwp change related to retry completes.
6410
assign  cwp_cmplt_rtry_g =
6411
                (cwp_cmplt0_pending & pending_thrd0_event_taken & cwp_retry0) |
6412
                (cwp_cmplt1_pending & pending_thrd1_event_taken & cwp_retry1) |
6413
                (cwp_cmplt2_pending & pending_thrd2_event_taken & cwp_retry2) |
6414
                (cwp_cmplt3_pending & pending_thrd3_event_taken & cwp_retry3);
6415
// 
6416
 
6417 113 albert.wat
dff_s #(2) dff_ccmplt_stgw2 (
6418 95 fafa1971
    .din ({cwp_cmplt_g,cwp_cmplt_rtry_g}),
6419
    .q   ({cwp_cmplt_w2,cwp_cmplt_rtry_w2}),
6420
    .clk (clk),
6421
    .se  (se),
6422 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6423 95 fafa1971
    .so  ()
6424
);
6425
 
6426
//=========================================================================================
6427
//      Generate SSCAN data 
6428
//=========================================================================================
6429
// 
6430 113 albert.wat
assign sscan_tid_sel[`TLU_THRD_NUM-1:0] = ctu_sscan_tid[`TLU_THRD_NUM-1:0];
6431 95 fafa1971
/*
6432
// logic moved to tlu_misctl
6433
// generating write indicators of ttype to the tsa
6434
assign sscan_tt_wr_sel[0] =
6435
           tsa_ttype_en & tsa_wr_vld[1] & thread0_wtrp_w2;
6436
assign sscan_tt_wr_sel[1] =
6437
           tsa_ttype_en & tsa_wr_vld[1] & thread1_wtrp_w2;
6438
assign sscan_tt_wr_sel[2] =
6439
           tsa_ttype_en & tsa_wr_vld[1] & thread2_wtrp_w2;
6440
assign sscan_tt_wr_sel[3] =
6441
           tsa_ttype_en & tsa_wr_vld[1] & thread3_wtrp_w2;
6442
//
6443
// generating read indicators of ttype from the tsa
6444
assign sscan_tt_rd_sel[0] =
6445
           tsa_rd_vld_m & thread0_rsel_m;
6446
assign sscan_tt_rd_sel[1] =
6447
           tsa_rd_vld_m & thread1_rsel_m;
6448
assign sscan_tt_rd_sel[2] =
6449
           tsa_rd_vld_m & thread2_rsel_m;
6450
assign sscan_tt_rd_sel[3] =
6451
           tsa_rd_vld_m & thread3_rsel_m;
6452
 
6453
assign sscan_ttype_en[0] =
6454
           sscan_tt_rd_sel[0] | sscan_tt_wr_sel[0];
6455
assign sscan_ttype_en[1] =
6456
           sscan_tt_rd_sel[1] | sscan_tt_wr_sel[1];
6457
assign sscan_ttype_en[2] =
6458
           sscan_tt_rd_sel[2] | sscan_tt_wr_sel[2];
6459
assign sscan_ttype_en[3] =
6460
           sscan_tt_rd_sel[3] | sscan_tt_wr_sel[3];
6461
//
6462
assign sscan_tt0_din[`TSA_TTYPE_WIDTH-1:0] =
6463
           (sscan_tt_wr_sel[0]) ?
6464
            final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] : tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0];
6465
assign sscan_tt1_din[`TSA_TTYPE_WIDTH-1:0] =
6466
           (sscan_tt_wr_sel[1]) ?
6467
            final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] : tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0];
6468
assign sscan_tt2_din[`TSA_TTYPE_WIDTH-1:0] =
6469
           (sscan_tt_wr_sel[2]) ?
6470
            final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] : tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0];
6471
assign sscan_tt3_din[`TSA_TTYPE_WIDTH-1:0] =
6472
           (sscan_tt_wr_sel[3]) ?
6473
            final_ttype_w2[`TSA_TTYPE_WIDTH-1:0] : tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0];
6474
//
6475 113 albert.wat
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt0_data (
6476 95 fafa1971
    .din (sscan_tt0_din[`TSA_TTYPE_WIDTH-1:0]),
6477
    .q   (sscan_tt0_data[`TSA_TTYPE_WIDTH-1:0]),
6478
    .en  (sscan_ttype_en[0]),
6479
    .clk (clk),
6480
    .se  (se),
6481 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6482 95 fafa1971
    .so  ()
6483
);
6484
 
6485 113 albert.wat
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt1_data (
6486 95 fafa1971
    .din (sscan_tt1_din[`TSA_TTYPE_WIDTH-1:0]),
6487
    .q   (sscan_tt1_data[`TSA_TTYPE_WIDTH-1:0]),
6488
    .en  (sscan_ttype_en[1]),
6489
    .clk (clk),
6490
    .se  (se),
6491 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6492 95 fafa1971
    .so  ()
6493
);
6494
 
6495 113 albert.wat
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt2_data (
6496 95 fafa1971
    .din (sscan_tt2_din[`TSA_TTYPE_WIDTH-1:0]),
6497
    .q   (sscan_tt2_data[`TSA_TTYPE_WIDTH-1:0]),
6498
    .en  (sscan_ttype_en[2]),
6499
    .clk (clk),
6500
    .se  (se),
6501 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6502 95 fafa1971
    .so  ()
6503
);
6504
 
6505 113 albert.wat
dffe_s #(`TSA_TTYPE_WIDTH) dffe_sscan_tt3_data (
6506 95 fafa1971
    .din (sscan_tt3_din[`TSA_TTYPE_WIDTH-1:0]),
6507
    .q   (sscan_tt3_data[`TSA_TTYPE_WIDTH-1:0]),
6508
    .en  (sscan_ttype_en[3]),
6509
    .clk (clk),
6510
    .se  (se),
6511 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6512 95 fafa1971
    .so  ()
6513
);
6514
 
6515 113 albert.wat
dff_s #(`TSA_TTYPE_WIDTH) dff_tsa_rdata_ttype_m (
6516 95 fafa1971
    .din (tsa_rdata_ttype[`TSA_TTYPE_WIDTH-1:0]),
6517
        .q   (tsa_rdata_ttype_m[`TSA_TTYPE_WIDTH-1:0]),
6518
    .clk (clk),
6519
    .se  (se),
6520 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6521 95 fafa1971
    .so  ()
6522
);
6523
 
6524 113 albert.wat
dff_s dff_tsa_rd_vld_e (
6525 95 fafa1971
    .din (tsa_rd_vld),
6526
        .q   (tsa_rd_vld_e),
6527
    .clk (clk),
6528
    .se  (se),
6529 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6530 95 fafa1971
    .so  ()
6531
);
6532
 
6533 113 albert.wat
dff_s dff_tsa_rd_vld_m (
6534 95 fafa1971
    .din (tsa_rd_vld_e),
6535
        .q   (tsa_rd_vld_m),
6536
    .clk (clk),
6537
    .se  (se),
6538 113 albert.wat
    `SIMPLY_RISC_SCANIN,
6539 95 fafa1971
    .so  ()
6540
);
6541
//
6542
// modified - due to sscan_tt[0-3]_data moved to tlu_misctl
6543
mux4ds #(`TCL_SSCAN_WIDTH) mx_sscan_test_data (
6544
       .in0  ({trp_lvl0[2:0],sscan_tt0_data[`TSA_TTYPE_WIDTH-1:0]}),
6545
       .in1  ({trp_lvl1[2:0],sscan_tt1_data[`TSA_TTYPE_WIDTH-1:0]}),
6546
       .in2  ({trp_lvl2[2:0],sscan_tt2_data[`TSA_TTYPE_WIDTH-1:0]}),
6547
       .in3  ({trp_lvl3[2:0],sscan_tt3_data[`TSA_TTYPE_WIDTH-1:0]}),
6548
       .sel0 (sscan_tid_sel[0]),
6549
       .sel1 (sscan_tid_sel[1]),
6550
       .sel2 (sscan_tid_sel[2]),
6551
       .sel3 (sscan_tid_sel[3]),
6552
       .dout (tcl_sscan_test_data[`TCL_SSCAN_WIDTH-1:0])
6553
);
6554
*/
6555
 
6556 113 albert.wat
mux4ds #(`TCL_SSCAN_WIDTH) mx_sscan_test_data (
6557 95 fafa1971
       .in0  (trp_lvl0[2:0]),
6558
       .in1  (trp_lvl1[2:0]),
6559
       .in2  (trp_lvl2[2:0]),
6560
       .in3  (trp_lvl3[2:0]),
6561
       .sel0 (sscan_tid_sel[0]),
6562
       .sel1 (sscan_tid_sel[1]),
6563
       .sel2 (sscan_tid_sel[2]),
6564
       .sel3 (sscan_tid_sel[3]),
6565 113 albert.wat
       .dout (tcl_sscan_test_data[`TCL_SSCAN_WIDTH-1:0])
6566 95 fafa1971
);
6567
 
6568 113 albert.wat
assign tlu_sscan_tcl_data[`TCL_SSCAN_WIDTH-1:0] =
6569
           tcl_sscan_test_data[`TCL_SSCAN_WIDTH-1:0];
6570 95 fafa1971
 
6571
//=========================================================================================
6572
//      Instrumentation signals created for sas 
6573
//=========================================================================================
6574
// 
6575
// synopsys translate_off
6576 113 albert.wat
wire [`TSA_TTYPE_WIDTH-1:0] sas_final_ttype_g;
6577
wire [`TSA_TTYPE_WIDTH-1:0] sas_adj_lsu_ttype_m2;
6578 95 fafa1971
wire [6:0] sas_hwint_swint_ttype;
6579 113 albert.wat
wire [`TSA_TTYPE_WIDTH-3:0] sas_rst_ttype_g;
6580 95 fafa1971
 
6581 113 albert.wat
mux4ds #(`TSA_TTYPE_WIDTH) mx_sas_final_ttype_g (
6582 95 fafa1971
    .sel0 (final_ttype_sel_g[0]),
6583
    .sel1 (final_ttype_sel_g[1]),
6584
    .sel2 (final_ttype_sel_g[2]),
6585
    .sel3 (final_ttype_sel_g[3]),
6586 113 albert.wat
    .in0  ({2'b0,sas_rst_ttype_g[`TSA_TTYPE_WIDTH-3:0]}),
6587
    .in1  (early_sync_ttype_g[`TSA_TTYPE_WIDTH-1:0]),
6588
    .in2  (sas_adj_lsu_ttype_m2[`TSA_TTYPE_WIDTH-1:0]),
6589
    .in3  (pending_ttype[`TSA_TTYPE_WIDTH-1:0]),
6590
    .dout (sas_final_ttype_g[`TSA_TTYPE_WIDTH-1:0])
6591 95 fafa1971
);
6592
 
6593 113 albert.wat
mux3ds #(`TSA_TTYPE_WIDTH) mx_sas_adj_lsu_ttype_m2 (
6594 95 fafa1971
    .sel0 (lsu_defr_trap_g),
6595
    .sel1 (va_oor_data_acc_excp_g & ~lsu_defr_trap_g),
6596
    .sel2 (~(va_oor_data_acc_excp_g | lsu_defr_trap_g)),
6597
    .in0  (9'h032),
6598
    .in1  (9'h030),
6599
    .in2  (lsu_tlu_ttype_m2),
6600 113 albert.wat
    .dout (sas_adj_lsu_ttype_m2[`TSA_TTYPE_WIDTH-1:0])
6601 95 fafa1971
);
6602
 
6603
assign sas_hwint_swint_ttype[6:0] =
6604 113 albert.wat
       (hwint_g)? `HWINT_INT:
6605
       (cpu_mondo_trap_g)? `CPU_MONDO_TRAP:
6606
       (dev_mondo_trap_g)? `DEV_MONDO_TRAP:
6607 95 fafa1971
        {3'b100, tlu_sftint_id[3:0]};
6608
 
6609 113 albert.wat
assign sas_rst_ttype_g[`TSA_TTYPE_WIDTH-3:0] =
6610 95 fafa1971
       (rst_ttype_sel[0])? {4'b00,reset_id_g[2:0]}:
6611
       (rst_ttype_sel[1])? wrap_tlz_ttype[6:0]:
6612
        sas_hwint_swint_ttype[6:0];
6613
 
6614
// synopsys translate_on
6615
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.