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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: tlu_tcl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

////////////////////////////////////////////////////////////////////

/*

//      Description:    Trap Control Logic

*/

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

`include "tlu.h"

module tlu_tcl (/*AUTOARG*/

   // Outputs

   tlu_ifu_trappc_vld_w1, tlu_ifu_trapnpc_vld_w1, tlu_ifu_trap_tid_w1,

   tlu_trap_hpstate_enb, tsa_wr_tpl, tsa_rd_tid, tsa_rd_tpl, tsa_rd_en,

   tsa_wr_tid, tsa_wr_vld, tsa_rd_vld_e, tlu_lsu_tl_zero, tlu_restore_pc_sel_w1,

   tlu_early_flush_pipe_w, tlu_early_flush_pipe2_w, tlu_exu_early_flush_pipe_w,

   tlu_agp_tid_w2, tsa_tstate_en, tsa_ttype_en, tlu_tl_gt_0_w2,

   tlu_exu_agp_tid, tlu_true_pc_sel_w, // tlu_retry_inst_m, tlu_done_inst_m, 

   tlu_tick_en_l, tlu_tickcmp_en_l, tlu_stickcmp_en_l, tlu_local_flush_w,

   tlu_tba_en_l, tlu_thrd_wsel_w2, tlu_thread_wsel_g, tlu_final_ttype_w2,

   tlu_thread_inst_vld_g, tlu_update_pc_l_w, tlu_htickcmp_en_l,

   tsa_pc_en, tsa_npc_en, tlu_hyperv_rdpr_sel, tlu_wsr_inst_nq_g,

   tlu_exu_priv_trap_m, tlu_ibrkpt_trap_w2, tlu_full_flush_pipe_w2,

   tlu_pstate_din_sel0, tlu_pstate_din_sel1, tlu_pstate_din_sel2,

   tlu_pstate_din_sel3, tlu_update_pstate_l_w2, tlu_trp_lvl,

   tlu_pil, tlu_wr_tsa_inst_w2, tlu_trap_cwp_en, // tlu_lsu_priv_trap_w,

   tlu_exu_cwp_retry_m, tlu_exu_cwpccr_update_m, tlu_lsu_priv_trap_m,

   tlu_lsu_asi_update_m, tlu_lsu_tid_m, tlu_pc_mxsel_w2, // tlu_lsu_asi_m,

   tlu_select_tba_w2, tdp_select_tba_w2, tlu_set_sftint_l_g,

   tlu_clr_sftint_l_g, tlu_wr_sftint_l_g, tlu_sftint_mx_sel, tlu_itag_acc_sel_g,

   tlu_sftint_en_l_g, tlu_sftint_penc_sel, tlu_sftint_vld, tlu_int_tid_m,

   tlu_tickcmp_sel, tlu_incr_tick, immu_sfsr_trp_wr, tlu_select_redmode,

   tlu_isfsr_din_g, // tlu_dsfsr_din_g, tlu_tag_access_ctxt_sel_m, 

   tlu_tick_npt, tlu_thrd_rsel_e, tlu_inst_vld_nq_m, tlu_pic_cnt_en_m,

   tlu_rdpr_mx1_sel, tlu_rdpr_mx2_sel, tlu_rdpr_mx3_sel, tlu_rdpr_mx4_sel,

   tlu_rdpr_mx5_sel, tlu_rdpr_mx6_sel, tlu_rdpr_mx7_sel, tlu_lsu_pstate_am,

   tlu_lsu_redmode_rst_d1, lsu_tlu_rsr_data_mod_e, tlu_addr_msk_g,

   // added for hypervisor support

   tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g, tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g,

   tlu_thrd_traps_w2, tlu_tick_ctl_din, tsa_htstate_en, tlu_por_rstint_g,

   tlu_hintp_vld, tlu_rerr_vld, tlu_final_offset_w1, // tlu_ifu_trapnpc_w2, 

   so, tlu_sscan_tcl_data, tlu_rst, // tlu_ifu_trappc_w2, tlu_rst_l, 

   // Inputs

   ifu_tlu_sraddr_d, ifu_tlu_rsr_inst_d, lsu_tlu_early_flush_w, ifu_tlu_pc_oor_e,

   tlu_wsr_data_b63_w, tlu_wsr_data_w, lsu_tlu_ttype_m2, ifu_tlu_flush_fd_w,

   lsu_tlu_ttype_vld_m2, ifu_tlu_done_inst_d, ifu_tlu_retry_inst_d, ifu_tlu_ttype_m,

   ifu_tlu_ttype_vld_m, exu_tlu_ttype_m, exu_tlu_ttype_vld_m, exu_tlu_spill,

   exu_tlu_spill_other, exu_tlu_spill_wtype, exu_tlu_va_oor_m, exu_tlu_spill_tid,

   ifu_tlu_sir_inst_m, ifu_tlu_inst_vld_m, ifu_tlu_thrid_d, tlu_tckctr_in,

   ifu_tlu_immu_miss_m, exu_tlu_va_oor_jl_ret_m, ifu_tlu_trap_m, lsu_tlu_wsr_inst_e,

   exu_tlu_cwp_cmplt, exu_tlu_cwp_retry, exu_tlu_cwp_cmplt_tid, exu_tlu_ue_trap_m,

   ifu_tlu_rstint_m, ifu_tlu_hwint_m, ifu_tlu_swint_m, pich_wrap_flg, tlu_pic_wrap_e,

   pich_onebelow_flg, pich_twobelow_flg, pib_picl_wrap, pib_pich_wrap, tlu_tcc_inst_w,

   int_tlu_rstid_m, tlu_int_pstate_ie, tlu_int_redmode, ifu_npc_w, tlu_pcr_ut,

   tlu_sftint_id, lsu_tlu_async_ttype_vld_g, lsu_tlu_defr_trp_taken_g, tlu_pcr_st,

   lsu_tlu_misalign_addr_ldst_atm_m, exu_tlu_misalign_addr_jmpl_rtn_m,

   lsu_tlu_async_tid_g, lsu_tlu_priv_action_g, lsu_tlu_async_ttype_g, lsu_tlu_wtchpt_trp_g,

   ifu_tlu_priv_violtn_m, ifu_lsu_memref_d, tlu_pstate_priv, tlu_isfsr_flt_vld,

   tlu_pstate_am, ffu_tlu_trap_ieee754, ffu_tlu_trap_other, ffu_tlu_trap_ue,

   ffu_ifu_tid_w2, ffu_tlu_ill_inst_m, ifu_tlu_npc_m,  // ifu_tlu_pc_m, 

   lsu_tlu_rsr_data_e, lsu_tlu_squash_va_oor_m, // tlu_restore_npc_w1,

   spu_tlu_rsrv_illgl_m, // exu_tlu_cwp0, exu_tlu_cwp1, exu_tlu_cwp2, exu_tlu_cwp3, 

   //

   // added for hypervisor support

   tlu_hpstate_priv, tlu_htstate_rw_d, tlu_htstate_rw_g, tlu_cwp_no_change_m,

   tlu_hscpd_dacc_excpt_m, tlu_htickcmp_rw_e, tlu_gl_rw_m, // tlu_gl_rw_g, 

   tlu_hpstate_enb, tlu_cpu_mondo_cmp, tlu_dev_mondo_cmp,

   tlu_resum_err_cmp, tlu_hintp, tlu_hpstate_tlz, tlu_qtail_dacc_excpt_m,

   pib_priv_act_trap_m, rclk, arst_l, grst_l, si, se, rst_tri_en, ctu_sscan_tid

   );

/*AUTOINPUT*/

// Beginning of automatic inputs (from unused autoinst inputs)

// End of automatics

input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d;      // addr of sr(st/pr)

input       ifu_tlu_rsr_inst_d;    // valid rd sr(st/pr)

// input       ifu_tlu_wsr_inst_d;    // valid wr sr(st/pr)

input       lsu_tlu_wsr_inst_e;    // valid wr sr(st/pr)

input           tlu_wsr_data_b63_w;    // b63 of wsr data

// input        tlu_wsr_data_b16_w;    // b16 of wsr data

input [3:0] tlu_wsr_data_w;    // pr/st data to irf.

input [8:0]      lsu_tlu_ttype_m2;       // trap type in m2.

input           lsu_tlu_ttype_vld_m2;   // trap is signaled.

// added asynchronize trap to handle correctable dmmu parity errors

input       lsu_tlu_defr_trp_taken_g; // lsu asynchronous trap valid

input       lsu_tlu_async_ttype_vld_g; // lsu asynchronous trap valid

input [6:0] lsu_tlu_async_ttype_g;  // lsu asynchronous trap type 

input [1:0] lsu_tlu_async_tid_g; // asynchronous trap - thread

// Removed unused bits 

// input        [1:0]   lsu_tlu_ttype_tid_m2;   // trapping thread

input           ifu_tlu_done_inst_d;    // done is valid

input           ifu_tlu_retry_inst_d;  // retry is valid

input [8:0]      ifu_tlu_ttype_m;        // trap type in m2.

input           ifu_tlu_ttype_vld_m;    // trap is signaled.

input           ifu_tlu_trap_m;     // trap is signaled.

// modified for timing

input       ifu_tlu_flush_fd_w;     // instruction flush signal 

// input                ifu_tlu_flush_m;            // instruction flush signal 

input           lsu_tlu_early_flush_w;  // early flush with tlb from LSU 

input [8:0]      exu_tlu_ttype_m;        // exu src ttype

input           exu_tlu_ttype_vld_m;    // exu src ttype vld

input           exu_tlu_ue_trap_m;      // exu ue ecc trap indicator 

//

// added for timing

/*

input [2:0]  exu_tlu_cwp0;  // cwp - thread0

input [2:0]  exu_tlu_cwp1;  // cwp - thread1

input [2:0]  exu_tlu_cwp2;  // cwp - thread2

input [2:0]  exu_tlu_cwp3;  // cwp - thread3

*/

//

input           exu_tlu_spill;          // spill trap

input [1:0]      exu_tlu_spill_tid;      // spill trap - thrid

input       exu_tlu_spill_other;    // From exu of sparc_exu.v

input [2:0] exu_tlu_spill_wtype;    // From exu of sparc_exu.v

input           exu_tlu_va_oor_m;       // ??? - to be used in sfsr

input           exu_tlu_va_oor_jl_ret_m; // ??? - to be used in sfsr

input           ifu_tlu_sir_inst_m;     // sir instruction executed

input       ifu_tlu_inst_vld_m;    // inst in w-stage of pipe.

input       ifu_tlu_pc_oor_e;    // inst in w-stage of pipe.

input [1:0] ifu_tlu_thrid_d;     // Thread id.

// input       lsu_tlu_dmmu_miss_g;   // ld/st misses in dtlb.

//

// modified the stage for timing 

//input     ifu_tlu_immu_miss_e;   // i-side page fault

input       ifu_tlu_immu_miss_m;   // i-side page fault

input       exu_tlu_cwp_cmplt;

input       exu_tlu_cwp_retry;

input [1:0] exu_tlu_cwp_cmplt_tid;

input       tlu_cwp_no_change_m;

// input       exu_tlu_cwp_fastcmplt_w;

// input moved to tlu_misctl

// input [2:0]  tsa_rdata_cwp;

// input [`TSA_TTYPE_WIDTH-1:0] tsa_rdata_ttype;

// input [7:0]  tsa_rdata_ccr;

// input [7:0]  tsa_rdata_asi;

input           ifu_tlu_rstint_m;       // reset interrupt

input           ifu_tlu_hwint_m;        // hw interrupt

input           ifu_tlu_swint_m;        // sw interrupt

input [5:0]      int_tlu_rstid_m;        // reset type

input [`TLU_THRD_NUM-1:0] tlu_int_pstate_ie;      // interrupt enable

input [`TLU_THRD_NUM-1:0] tlu_int_redmode;        // redmode

// input  [`TLU_THRD_NUM-1:0]   const_cpuid;

input [`TLU_THRD_NUM-1:0] tlu_sftint_id;

input [`TLU_THRD_NUM-1:0] pich_wrap_flg;

input [`TLU_THRD_NUM-1:0] pich_onebelow_flg;

input [`TLU_THRD_NUM-1:0] pich_twobelow_flg;

input [`TLU_THRD_NUM-1:0] pib_picl_wrap;

// modified for bug 5436: Niagara 2.0

input [`TLU_THRD_NUM-1:0] tlu_pcr_ut;

input [`TLU_THRD_NUM-1:0] tlu_pcr_st;

// input tlu_pic_wrap_e, tlu_pcr_ut_e, tlu_pcr_st_e;

input tlu_pic_wrap_e;

// input                tlu_tick_match; // match between tick and tick-cmp 

// input                tlu_stick_match;        // match between tick and stick-cmp 

// input  [`TLU_THRD_NUM-1:0] pib_pic_wrap; // overflow for the pic registers - lvl15 int 

// modified for timing support

// input  [`TLU_THRD_NUM-1:0] pib_priv_act_trap; // access priv violation of the pics 

input  [`TLU_THRD_NUM-1:0] pib_priv_act_trap_m; // access priv violation of the pics 

input           lsu_tlu_misalign_addr_ldst_atm_m;// misaligned addr - ld,st,atomic 

input           exu_tlu_misalign_addr_jmpl_rtn_m;// misaligned addr - jmpl or return addr

// input                lsu_tlu_priv_violtn_g;          // privileged violation trap

input           lsu_tlu_priv_action_g;          // privileged action trap

input           lsu_tlu_wtchpt_trp_g;           // watchpt trap has occurred.

input           ifu_tlu_priv_violtn_m;

input           ifu_lsu_memref_d;

input [3:0] tlu_pstate_priv;

input [3:0] tlu_pstate_am;

input [3:0]      tlu_isfsr_flt_vld;

input           ffu_tlu_trap_ieee754;

input           ffu_tlu_trap_other;

input           ffu_tlu_trap_ue;

input           ffu_tlu_ill_inst_m; // illegal instruction trap from ffu                

input [1:0]      ffu_ifu_tid_w2;

input [7:0]      lsu_tlu_rsr_data_e;

input       lsu_tlu_squash_va_oor_m;  // squash va_oor for mem-op.

input       spu_tlu_rsrv_illgl_m;    // illegal instruction trap from spu 

input       tlu_htstate_rw_d;

input       tlu_htstate_rw_g;

input       tlu_htickcmp_rw_e;

// input       tlu_gl_rw_g;

input       tlu_gl_rw_m;

input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;

input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb;

input [`TLU_THRD_NUM-1:0] tlu_hpstate_tlz;

input [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_cmp;

input [`TLU_THRD_NUM-1:0] tlu_dev_mondo_cmp;

input [`TLU_THRD_NUM-1:0] tlu_resum_err_cmp;

input [`TLU_THRD_NUM-1:0] tlu_hintp;

// input [48:0] ifu_tlu_pc_m;

input [48:0] ifu_tlu_npc_m;

// input [33:0] tlu_partial_trap_pc_w1;

// modified for bug 3017

// logic moved to tlu_misctl

input tlu_hscpd_dacc_excpt_m;

input tlu_qtail_dacc_excpt_m;

// added for timing

input [4:0] tlu_hyperv_rdpr_sel;

input [1:0]      tlu_tckctr_in;

input           rclk; // clock

// sscan tid

input [`TLU_THRD_NUM-1:0] ctu_sscan_tid;

//

// modified to abide to the niagara reset methodology

input           grst_l;                         // global reset - active log

input           arst_l;                         // global reset - active log

input           rst_tri_en;                     // global reset - active log

input           si;                                 // global scan-in 

input           se;                                 // global scan-out 

/*autooutput*/

// beginning of automatic outputs (from unused autoinst outputs)

// end of automatics

output           tlu_ifu_trappc_vld_w1; // trap pc or pc on retry.

output           tlu_ifu_trapnpc_vld_w1;// trap pc or pc on retry.

output [1:0] tlu_ifu_trap_tid_w1;        // thread id.

output       tlu_trap_hpstate_enb;

output       tlu_restore_pc_sel_w1;

output [`TLU_THRD_NUM-1:0] pib_pich_wrap;

output tlu_tcc_inst_w;

output [2:0] tsa_wr_tpl;         // trap level for wr.

output [1:0] tsa_rd_tid;         // thread id for wr.

output [2:0] tsa_rd_tpl;         // trap level for rd.

output [1:0] tsa_wr_tid;         // thread id for rd.

output [1:0] tsa_wr_vld;         // write pointer vld

// modified for timing

output           tsa_rd_vld_e;          // read pointer

output           tsa_rd_en;                 // read pointer

output [3:0] tlu_lsu_tl_zero;    // trap level is zero.

// output                tlu_ifu_flush_pipe_w;  // exception related flush

// output                tlu_flush_pipe_w;      // exception related flush - local copy

// added for timing 

// output                tlu_flush_all_w2;      // exception related flush - local copy

// output                tlu_flush_all_w;       // exception related flush - local copy

output           tlu_local_flush_w;     // exception related flush - local copy

output           tlu_early_flush_pipe_w;        // exception related flush - local copy

output           tlu_early_flush_pipe2_w;       // exception related flush - local copy

output           tlu_exu_early_flush_pipe_w;    // exception related flush - to exu

output           tlu_full_flush_pipe_w2;            // exception related flush - to exu

// output  [2:0]   tlu_exu_agp;            // alternate global pointer

// output          tlu_exu_agp_swap;       // switch globals

// modified due to timing

// output [1:0] tlu_agp_tid_g;        // thread that agp refers to

output [1:0] tlu_agp_tid_w2;        // thread that agp refers to

output [1:0] tlu_exu_agp_tid;        // thread that agp refers to

output           tsa_pc_en;             // enable write of pc in tsa.

output       tsa_npc_en;                // enable write of npc in tsa.

output       tsa_tstate_en;             // enable write of tstate in tsa.

output       tsa_htstate_en;    // enable write of htstate in tsa.

output       tsa_ttype_en;              // enable write of ttype in tsa.

// modified due to timing

// output       tlu_tl_gt_0_g;     // trp lvl gt then 0

output       tlu_tl_gt_0_w2;     // trp lvl gt then 0

// modified for timing

output [2:0] tlu_true_pc_sel_w;

// output       tlu_retry_inst_m;  // valid retry inst

// output       tlu_done_inst_m;   // valid done inst

// output       tlu_dnrtry_inst_m_l; // valid done/retry inst - g

output       tlu_tick_en_l;     // tick reg write enable

output [`TLU_THRD_NUM-1:0]  tlu_tickcmp_en_l;  // tick compare reg write enable

output [`TLU_THRD_NUM-1:0]  tlu_stickcmp_en_l; // stick compare reg write enable

output [`TLU_THRD_NUM-1:0]  tlu_htickcmp_en_l; // update htickcmp register 

output [`TLU_THRD_NUM-1:0]  tlu_tba_en_l;      // tba reg write enable

output [`TLU_THRD_NUM-1:0]  tlu_thrd_wsel_w2;   // thread requiring tsa write.

output [`TLU_THRD_NUM-1:0]  tlu_thread_wsel_g; // thread for instruction fetched 

output [`TSA_TTYPE_WIDTH-1:0] tlu_final_ttype_w2;  // selected ttype - w2

// output   tlu_async_trap_taken_g; // async trap taken

output [`TLU_THRD_NUM-1:0]  tlu_thread_inst_vld_g; // valid inst for a thread

// output [`TLU_THRD_NUM-1:0]  tlu_thread_inst_vld_w2; // valid inst for a thread

// output [`TLU_THRD_NUM-1:0]  tlu_update_pc_l_m; // update pc or npc for a thread

output [`TLU_THRD_NUM-1:0]  tlu_update_pc_l_w; // update pc or npc for a thread

// output [`TLU_THRD_NUM-1:0]  tlu_thrd_rsel_g; // thread requiring tsa read

// modified for bug 1767

// output               tlu_select_tle; // tle/cle value on trap 

// output [1:0]   tlu_select_mmodel;    // mem. model on trap

output          tlu_select_redmode;     // redmode setting on trap

// Modified for bug 1575

//

// output   [2:0]  tlu_pstate_din_sel;    // sel source of tsa wdata

output [1:0] tlu_pstate_din_sel0;    // sel source of tsa wdata

output [1:0] tlu_pstate_din_sel1;    // sel source of tsa wdata

output [1:0] tlu_pstate_din_sel2;    // sel source of tsa wdata

output [1:0] tlu_pstate_din_sel3;    // sel source of tsa wdata

//

// modified due to timing

// output [3:0] tlu_update_pstate_l_g; // pstate write enable

output [3:0] tlu_update_pstate_l_w2; // pstate write enable

output [2:0] tlu_trp_lvl;    // trp lvl - mx'ed

output [3:0] tlu_pil;              // pil - mx'ed

// output       tlu_wsr_inst_g; // write state inst

// 

// added for timing

output       tlu_wsr_inst_nq_g; // write state inst

// output       tlu_wr_tsa_inst_g; // write state inst

output       tlu_wr_tsa_inst_w2; // write state inst

output       tlu_exu_priv_trap_m; // local traps send to exu 

output       tlu_lsu_priv_trap_m; // local traps send to lsu 

// output       tlu_lsu_priv_trap_w; // local traps send to lsu 

// experiment

output       tlu_pic_cnt_en_m; // local traps send to exu 

// output       tlu_exu_pic_onebelow_m; // local traps send to exu 

// output       tlu_exu_pic_twobelow_m; // local traps send to exu 

output       tlu_exu_cwp_retry_m;

output       tlu_exu_cwpccr_update_m;

// output moved to tlu_misctl

// output [2:0] tlu_exu_cwp_m;

// output [7:0] tlu_exu_ccr_m;

// output [7:0] tlu_lsu_asi_m;          // asi from stack

// added for bug3499

output [`TLU_THRD_NUM-1:0] tlu_trap_cwp_en;

output       tlu_lsu_asi_update_m; // update asi

output [1:0] tlu_lsu_tid_m;              // thread for asi update

// output        tlu_assist_boot_rst_g; // use rstvaddr all zeroes

// modified due to timing

// output                tlu_self_boot_rst_g;   // use rstvaddr all ones

// output                tlu_select_tba_g;      // use tba

// output                tlu_select_htba_g;     // use htba

// modified for one-hot mux problem

// output                tlu_self_boot_rst_w2;  // use rstvaddr all ones

// output                tlu_select_htba_w2;    // use htba

output [2:0] tlu_pc_mxsel_w2;

output           tlu_select_tba_w2;     // use tba

output           tdp_select_tba_w2;     // use tba

//

output           tlu_set_sftint_l_g;    // set sftint

output           tlu_clr_sftint_l_g;    // clr sftint

output           tlu_wr_sftint_l_g;     // wr to sftin (asr 16)

output [`TLU_THRD_NUM-1:0] tlu_sftint_en_l_g; // wr en sftint regs.

output [`TLU_THRD_NUM-1:0] tlu_sftint_mx_sel; // mux sel sftint regs.

//

// removed due to sftint recode

// output       [3:0]   tlu_sftint_lvl14_int;   // level 14 sft interrupt

output [3:0] tlu_sftint_penc_sel;        // select appr. thread for pr. encd.

output [3:0] tlu_sftint_vld;     // a sftint is valid for a thread       

output [1:0] tlu_int_tid_m;              // thread id

output [1:0] tlu_incr_tick;         // increment tick reg

output [3:0] tlu_tickcmp_sel;       // select src for tickcmp

output [3:0]  immu_sfsr_trp_wr;

output tlu_itag_acc_sel_g;

output [23:0] tlu_isfsr_din_g;

//

// removed due to sftint code cleanup

output           tlu_tick_npt;          // npt bit of tick

output [3:0] tlu_thrd_rsel_e;    // read select for threaded regs

output           tlu_inst_vld_nq_m;     // not qualified inst vld

output [3:0] tlu_lsu_pstate_am;  // ship to lsu

output [2:0] tlu_rdpr_mx1_sel;

output [2:0] tlu_rdpr_mx2_sel;

output [1:0] tlu_rdpr_mx3_sel;

output [1:0] tlu_rdpr_mx4_sel;

output [2:0] tlu_rdpr_mx5_sel;

output [2:0] tlu_rdpr_mx6_sel;

output [3:0] tlu_rdpr_mx7_sel;

//

output [`TSA_TTYPE_WIDTH-1:0] tlu_final_offset_w1;

// output   [3:0]   tlu_lsu_redmode;            // redmode

// output [3:0] tlu_lsu_redmode_rst;

// output [`TLU_THRD_NUM-1:0] tlu_lsu_async_ack_w2;

output [3:0] tlu_lsu_redmode_rst_d1;

output [7:0] lsu_tlu_rsr_data_mod_e;

output       tlu_addr_msk_g;        // address masking active for thread in pipe.

//

// added for hypervisor support

// modified for timing

// output tlu_thrd0_traps, tlu_thrd1_traps;

// output tlu_thrd2_traps, tlu_thrd3_traps;

output [`TLU_THRD_NUM-1:0] tlu_thrd_traps_w2;

output tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g;

output tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g;

// output tlu_ibrkpt_trap_g; 

output tlu_ibrkpt_trap_w2;

output tlu_tick_ctl_din;

output [`TLU_THRD_NUM-1:0] tlu_por_rstint_g;

output [`TLU_THRD_NUM-1:0] tlu_hintp_vld;  // From tcl of tlu_tcl.v

output [`TLU_THRD_NUM-1:0] tlu_rerr_vld;  // From tcl of tlu_tcl.v

// modified for bug 3017

// moved to tlu_misctl

output [48:0] ifu_npc_w; //ifu_pc_w, 

// 

// shadow scan data from tcl tl and ttype

output [`TCL_SSCAN_WIDTH-1:0] tlu_sscan_tcl_data;

//

// added to abide to the niagara reset methodology

output tlu_rst;     // local unit reset - active high

// output tlu_rst_l;    // local unit reset - active low

output so;                      // global scan-out 

/*AUTOWIRE*/

// Beginning of automatic wires (for undeclared instantiated-module outputs)

// End of automatics

// this signal were added to abide to the niagara reset methodology

wire local_rst;

wire local_rst_l;

wire tlu_rst_l; // local unit reset - active low

wire [1:0]  tlu_exu_tid_m;

wire [3:0]       pstate_rmode;

// wire select_tba_g;   // use tba

wire local_select_tba_w2;       // use tba

wire [1:0] select_tba_element_w2;        // use tba

// wire select_htba_g;  // use htba

//

// added for early flush timing fix

// wire tlu_early_flush_pipe_m; 

wire local_early_flush_pipe_w;

wire local_early_flush_pipe2_w;

wire local_early_flush_pipe3_w;

wire local_early_flush_pipe4_w;

wire lsu_ttype_vld_w, lsu_ttype_vld_w2;

wire tlu_flush_all_w;

wire tlu_ifu_flush_pipe_w;  // exception related flush

wire tlu_flush_pipe_w;  // exception related flush

wire tlu_flush_all_w2;

// wire tlu_wr_tsa_inst_g; // write state inst

wire tlu_self_boot_rst_g, tlu_self_boot_rst_w2;

wire dnrtry_inst_g;

wire dnrtry0_inst_g, dnrtry1_inst_g;

wire dnrtry2_inst_g, dnrtry3_inst_g;

wire [`TLU_THRD_NUM-1:0] dnrtry_inst_w2;

wire thrd0_traps,thrd1_traps;

wire thrd2_traps,thrd3_traps;

// wire [`TLU_THRD_NUM-1:0] async_trap_ack_g;

// wire [`TLU_THRD_NUM-1:0] async_trap_ack_w2;

wire [2:0]       trp_lvl0,trp_lvl0_new;

wire [2:0]       trp_lvl1,trp_lvl1_new;

wire [2:0]       trp_lvl2,trp_lvl2_new;

wire [2:0]       trp_lvl3,trp_lvl3_new;

wire tl0_en, tl0_gt_0;

wire tl1_en, tl1_gt_0;

wire tl2_en, tl2_gt_0;

wire tl3_en, tl3_gt_0;

wire [1:0] agp_tid_g, agp_tid_w2, agp_tid_w3; // thread that agp refers to

// wire tlu_pic_onebelow_e, tlu_pic_twobelow_e; 

// experiment

wire pich_wrap_flg_m, tlu_pich_wrap_flg_m; // pich_wrap_flg_e, 

wire tlu_picl_wrap_flg_m; // pich_wrap_flg_e, 

// modified for bug 5436 - Niagara 2.0

wire [`TLU_THRD_NUM-1:0] pic_cnt_en;

wire pic_cnt_en_e, pic_cnt_en_m, pic_cnt_en_w, pic_cnt_en_w2;

// wire pic_trap_en_e; 

//wire pcr_ut_e, pcr_st_e; 

// wire [`TLU_THRD_NUM-1:0] pich_exu_wrap_e;

// wire pic_hpstate_enb_e, pic_hpstate_priv_e, pic_pstate_priv_e; 

//

wire [`TLU_THRD_NUM-1:0] tlz_thread_set, tlz_thread_data;

wire [`TLU_THRD_NUM-1:0] tlz_thread;

wire [`TLU_THRD_NUM-1:0] tlz_trap_m, tlz_exu_trap_m;

wire [`TLU_THRD_NUM-1:0] tlz_trap_nq_g, tlz_trap_g;

wire [`TLU_THRD_NUM-1:0] ifu_thrd_flush_w;

wire [`TLU_THRD_NUM-1:0] tlu_none_priv;

wire cpu_mondo_trap_g, dev_mondo_trap_g;

wire cpu_mondo_trap_w2, dev_mondo_trap_w2;

wire [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_trap;

wire [`TLU_THRD_NUM-1:0] tlu_dev_mondo_trap;

wire [`TLU_THRD_NUM-1:0] tlu_resum_err_trap;

wire [`TLU_THRD_NUM-1:0] tlu_hyper_lite;

wire [3:0] local_rdpr_mx6_sel;

wire [3:0] local_rdpr_mx5_sel;

wire [2:0] local_rdpr_mx4_sel;

wire [2:0] local_rdpr_mx3_sel;

wire [3:0] local_rdpr_mx2_sel;

wire [3:0] local_rdpr_mx1_sel;

wire tlu_none_priv_m;

wire ibrkpt_trap_m, ibrkpt_trap_g, ibrkpt_trap_w2;

wire va_oor_jl_ret_g;

wire done_inst_m_tmp;

wire retry_inst_m_tmp;

wire done_inst_w2;

wire retry_inst_w2;

wire [2:0] true_pc_sel_m, true_pc_sel_w;

// wire dsfsr_flt_vld_g;

wire done_inst_e, retry_inst_e;

wire done_inst_m, retry_inst_m;

wire exu_done_inst_m, exu_retry_inst_m;

// logic moved to misctl

// wire cwp_no_change_m;

// wire [2:0] cwp_xor_m, trap_old_cwp_m; 

wire done_inst_g, retry_inst_g;

wire [1:0] thrid_d, thrid_e, thrid_m, thrid_g;

wire [1:0] thrid_w2;

//

// added for tsa_wr_tid bug

//

// wire thread0_wtrp_g, thread1_wtrp_g, thread2_wtrp_g, thread3_wtrp_g;

wire thread0_wtrp_w2, thread1_wtrp_w2, thread2_wtrp_w2, thread3_wtrp_w2;

wire thread0_wsel_g, thread1_wsel_g, thread2_wsel_g, thread3_wsel_g;

wire thread0_wsel_w2, thread1_wsel_w2, thread2_wsel_w2, thread3_wsel_w2;

wire thread0_rsel_dec_g,thread1_rsel_dec_g;

wire thread2_rsel_dec_g,thread3_rsel_dec_g;

wire thread0_rsel_d, thread1_rsel_d, thread2_rsel_d, thread3_rsel_d;

wire thread0_rsel_m, thread1_rsel_m, thread2_rsel_m, thread3_rsel_m;

wire thread0_stg_m, thread1_stg_m, thread2_stg_m, thread3_stg_m;

wire thread0_stg_m_buf, thread1_stg_m_buf, thread2_stg_m_buf, thread3_stg_m_buf;

wire thread0_rsel_g, thread1_rsel_g, thread2_rsel_g, thread3_rsel_g;

wire thread0_rsel_e, thread1_rsel_e, thread2_rsel_e, thread3_rsel_e;

wire inst_vld_w2, inst_vld_g, inst_vld_m, inst_vld_nf_g;

wire [`TLU_THRD_NUM-1:0] thread_inst_vld_g;

wire [`TLU_THRD_NUM-1:0] thread_inst_vld_w2;

// wire tlu_inst_vld_m; // qualified inst vld

wire exu_ttype_vld_g, ifu_ttype_vld_g, exu_ue_trap_g;

wire [8:0]       exu_ttype_g, ifu_ttype_tmp_g, ifu_ttype_g;

wire [8:0]       exu_spill_ttype;

// added for timing fix

wire    spu_ill_inst_m ;      // illegal instruction trap from spu 

wire    spu_ill_inst_uf_g ;      // illegal instruction trap from spu 

wire    spu_ill_inst_g ;      // illegal instruction trap from spu 

wire    pib_priv_act_trap_g ;   // privilege action trap from pib 

wire    pib_priv_act_trap_uf_g ;   // privilege action trap from pib 

wire    pib_priv_act_early_trap_m ; // privilege action trap from pib 

wire    ffu_ill_inst_uf_g ;   // illegal instruction trap from ffu - unflushed 

wire    ffu_ill_inst_g ;      // illegal instruction trap from ffu 

wire    ffu_higher_pri_g ;      // illegal instruction trap from ffu 

wire    exu_higher_pri_g ;      // UE ECC trap from exu 

// wire    lsu_ill_inst_uf_g ;   // illegal instruction trap from lsu - unflushed

// wire    lsu_ill_inst_g ;      // illegal instruction trap from lsu 

// wire [`TLU_THRD_NUM-1:0] lsu_defr_thrd_g; 

wire    lsu_defr_trap_g, lsu_defr_trap_w2 ;     // deferred trap from lsu 

wire    local_lsu_async_ttype_vld_w; // deferred trap from lsu 

// wire    local_lsu_defr_trp_taken_g; // deferred trap from lsu 

wire [`TLU_THRD_NUM-1:0] lsu_defr_trp_taken_w2;

// wire    lsu_tlu_defr_trp_taken_w2 ;  // deferred trap from lsu - signled in g for w2

                                     // trap need to sync up with lsu_tlu_async_ttype_vld_g  

wire    htrap_ill_inst_m ;      // illegal instruction trap from htrap 

wire    htrap_ill_inst_uf_g ;   // illegal instruction trap from htrap - unflushed

wire    htrap_ill_inst_g ;      // illegal instruction trap from htrap 

wire    [`TLU_ASR_ADDR_WIDTH-1:0] sraddr;

wire    [`TLU_ASR_ADDR_WIDTH-1:0] sraddr2;

// modified due to timing

// wire         wsr_inst_d;

wire        asr_hyperp, asr_priv;

wire            tpc_rw_d, tnpc_rw_d, tstate_rw_d, ttype_rw_d;

wire            tick_rw_d, tickcmp_rw_d, tick_npriv_r_d;

wire        pcr_rsr_d, pic_rsr_d;

wire        pcr_rsr_e, pic_rsr_e;

wire        tlu_gl_rw_g;

//

// added for hypervisor support

wire maxtl_wr_sel;

wire [3:0] maxstl_wr_sel;

wire [2:0] wsr_trp_lvl0_data_w, wsr_trp_lvl1_data_w;

wire [2:0] wsr_trp_lvl2_data_w, wsr_trp_lvl3_data_w;

wire [2:0] wsr_trp_lvl0_data_w2, wsr_trp_lvl1_data_w2;

wire [2:0] wsr_trp_lvl2_data_w2, wsr_trp_lvl3_data_w2;

wire       stick_rw_d, stickcmp_rw_d, stickcmp_rw_e;

wire       stickcmp_rw_m, stickcmp_rw_g;

// wire [3:0] stickcmp_int;       // interrupt caused by stick_ticktmp 

// wire [3:0] stick_intclr;  // use to clear the stick_int bit

wire tba_rw_d, pstate_rw_d, pil_rw_d, tl_rw_d;

wire tsa_wr_tid_sel_g, tsa_wr_tid_sel_tim_g, tsa_wr_tid_sel_w2;

wire immu_miss_g;

wire trap_taken_g, trap_taken_w2;

wire [1:0] trap_tid_g;

// wire [1:0] tsa_wr_tid_g;

wire [1:0] pend_trap_tid_g, pend_trap_tid_w2;

wire [`TSA_TTYPE_WIDTH-1:0] final_ttype_w2;

wire [`TSA_TTYPE_WIDTH-1:0] tba_ttype_w1;

wire [`TSA_TTYPE_WIDTH-1:0] final_offset_w1;

wire tsa_rd_vld;

// modified for bug 3017

// logic moved to tlu_misctl

// wire [48:0] normal_trap_pc_w1, normal_trap_npc_w1; 

// wire [48:0] trap_pc_w1, trap_npc_w1; 

// wire [48:0] trap_pc_w2, trap_npc_w2; 

// wire tsa_rd_vld_e, tsa_rd_vld_m;

wire [`TLU_THRD_NUM-1:0] sscan_tid_sel;

// logic moved to tlu_misctl

/*

wire [`TLU_THRD_NUM-1:0] sscan_ttype_en;

wire [`TLU_THRD_NUM-1:0] sscan_tt_rd_sel;

wire [`TLU_THRD_NUM-1:0] sscan_tt_wr_sel;

wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt0_data;

wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt1_data;

wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt2_data;

wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt3_data;

wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt0_din;

wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt1_din;

wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt2_din;

wire [`TSA_TTYPE_WIDTH-1:0] sscan_tt3_din;

wire [`TSA_TTYPE_WIDTH-1:0] tsa_rdata_ttype_m;

*/

wire [`TCL_SSCAN_WIDTH-1:0] tcl_sscan_test_data;

wire tba_ttype_sel_w2;

wire [3:0] final_ttype_sel_g, final_ttype_sel_w2;

// modified due to one-hot mux bug

wire [1:0] final_offset_en_g, final_offset_en_w1;