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1 95 fafa1971 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: tlu_tdp.v
4 
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5 
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6 
//
7 
// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19 
//
20 
// ========== Copyright Header End ============================================
21 113 albert.wat 
`ifdef SIMPLY_RISC_TWEAKS
22 
`define SIMPLY_RISC_SCANIN .si(0)
23 
`else
24 
`define SIMPLY_RISC_SCANIN .si()
25 
`endif
26 95 fafa1971 
///////////////////////////////////////////////////////////////////////
27 
/*
28 
//      Description:    Trap Datapath
29 
*/
30 
////////////////////////////////////////////////////////////////////////
31 
// Global header file includes
32 
////////////////////////////////////////////////////////////////////////
33 113 albert.wat 
`include "sys.h" // system level definition file which contains the
34 95 fafa1971 
                             // time scale definition
35 
 
36 
////////////////////////////////////////////////////////////////////////
37 
// Local header file includes / local defines
38 
////////////////////////////////////////////////////////////////////////
39 113 albert.wat 
`include "tlu.h"
40 95 fafa1971 
 
41 
//FPGA_SYN enables all FPGA related modifications
42 113 albert.wat 
`ifdef FPGA_SYN
43 
`define FPGA_SYN_CLK_EN
44 
`define FPGA_SYN_CLK_DFF
45 
`endif
46 95 fafa1971 
 
47 
module tlu_tdp (/*AUTOARG*/
48 
   // Outputs
49 
   tlu_pib_rsr_data_e, tlu_restore_pc_w1, tlu_restore_npc_w1, tlu_partial_trap_pc_w1,
50 
   tsa_wdata, tlu_int_pstate_ie, local_pstate_ie, tlu_ifu_pstate_pef,
51 
   tlu_lsu_pstate_cle, tlu_lsu_pstate_priv, tlu_int_redmode, tlu_lsu_redmode,
52 
   tlu_sscan_test_data,
53 
   // modified for bug 1767
54 
   tlu_pstate_am, tlu_sftint_id,
55 
   // added for timing
56 
   // modfied for hypervisor support
57 
   tlu_dnrtry_global_g, tlu_tick_incr_din, tlu_exu_rsr_data_m,
58 
   tlu_hpstate_priv, local_hpstate_priv, local_hpstate_enb, local_pstate_priv,
59 
   tlu_hpstate_enb, tlu_hintp, tlu_por_rstint_g, tcl_hpstate_priv, tcl_hpstate_enb,
60 
   tlu_trap_hpstate_enb, tlu_hpstate_tlz, tlu_asi_state_e, tlu_hpstate_ibe,
61 
   so,
62 
   // Inputs
63 
   tsa_rdata, tlu_wsr_data_w, lsu_tlu_rsr_data_e, tlu_ibrkpt_trap_w2,
64 
   // reset was modified to abide to the Niagara reset methodology
65 
   rclk, tlu_rst, tlu_thrd_wsel_w2, ifu_lsu_imm_asi_d, // tm_l,
66 
   tlu_final_ttype_w2, tlu_pstate_din_sel0, tlu_pstate_din_sel1,
67 
   tlu_pstate_din_sel2, tlu_pstate_din_sel3, ifu_lsu_imm_asi_vld_d,
68 
   lsu_asi_reg0, lsu_asi_reg1, lsu_asi_reg2, lsu_asi_reg3,
69 
   exu_tlu_ccr0_w, exu_tlu_ccr1_w, exu_tlu_ccr2_w, exu_tlu_ccr3_w,
70 
   exu_tlu_cwp0, exu_tlu_cwp1, exu_tlu_cwp2, exu_tlu_cwp3, tlu_trap_cwp_en,
71 
   tlu_pc_new_w, tlu_npc_new_w, tlu_sftint_en_l_g, tlu_sftint_mx_sel,
72 
   tlu_set_sftint_l_g, tlu_wr_tsa_inst_w2,  tlu_clr_sftint_l_g,
73 
   tlu_wr_sftint_l_g, tlu_sftint_penc_sel, tlu_tba_en_l, tlu_tick_en_l,
74 
   tlu_tickcmp_sel, tlu_tickcmp_en_l, // tlu_retry_inst_m, tlu_done_inst_m,
75 
   tlu_update_pc_l_w, tlu_tl_gt_0_w2, pib_pich_wrap, // tlu_dnrtry_inst_m_l,
76 
   tlu_select_tba_w2, tlu_select_redmode, tlu_update_pstate_l_w2, tlu_pil,
77 
   tlu_trp_lvl, tlu_tick_npt, tlu_thrd_rsel_e, tlu_tick_incr_dout,
78 
   tlu_rdpr_mx1_sel, tlu_rdpr_mx2_sel, tlu_rdpr_mx3_sel, tlu_rdpr_mx4_sel,
79 
   tlu_hpstate_din_sel0, tlu_hpstate_din_sel1, tlu_pc_mxsel_w2,
80 
   tlu_hpstate_din_sel2, tlu_hpstate_din_sel3, tlu_update_hpstate_l_w2,
81 
   tlu_htba_en_l, tlu_rdpr_mx5_sel, tlu_rdpr_mx6_sel, pib_picl_wrap,
82 
   tlu_rdpr_mx7_sel, tlu_htickcmp_intdis, tlu_stickcmp_en_l, tlu_htickcmp_en_l,
83 
   tlu_gl_lvl0, tlu_gl_lvl1, tlu_gl_lvl2, tlu_gl_lvl3, tlu_wr_hintp_g,
84 
   tlu_set_hintp_sel_g, ctu_sscan_tid, si, se
85 
   );
86 
 
87 
/*AUTOINPUT*/
88 
// Beginning of automatic inputs (from unused autoinst inputs)
89 
// End of automatics
90 113 albert.wat 
input   [`TLU_TDP_TSA_WIDTH-1:0] tsa_rdata;                 // rd data for tsa.
91 
input   [`TLU_THRD_NUM-1:0] tlu_por_rstint_g;
92 95 fafa1971 
//
93 
// modified for timing
94 113 albert.wat 
input   [`TLU_ASR_DATA_WIDTH-1:0] tlu_wsr_data_w; // pr/st data from irf.
95 95 fafa1971 
 
96 
input   [7:0]    lsu_tlu_rsr_data_e;     // lsu sr/pr read data
97 
 
98 
input           rclk;                   // clock
99 
//
100 
// reset was removed to abide to the Niagara reset methodology
101 
input tlu_rst;                             // unit-reset
102 113 albert.wat 
input [`TLU_THRD_NUM-1:0] tlu_thrd_wsel_w2;// thread requiring tsa write.
103 
input [`TSA_TTYPE_WIDTH-1:0]     tlu_final_ttype_w2;        // selected ttype - g
104 95 fafa1971 
input tlu_ibrkpt_trap_w2;       // instruction brkpt trap
105 
input tlu_trap_hpstate_enb;     // mode indicator for the trapped thrd
106 
input tlu_wr_tsa_inst_w2;       // write state inst
107 
input [1:0]  tlu_pstate_din_sel0; // sel source of tsa wdata
108 
input [1:0]  tlu_pstate_din_sel1; // sel source of tsa wdata
109 
input [1:0]  tlu_pstate_din_sel2; // sel source of tsa wdata
110 
input [1:0]  tlu_pstate_din_sel3; // sel source of tsa wdata
111 113 albert.wat 
input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_reg0; // asi state - thread0
112 
input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_reg1; // asi state - thread1
113 
input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_reg2; // asi state - thread2
114 
input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_reg3; // asi state - thread3
115 
input [`TLU_ASI_STATE_WIDTH-1:0] ifu_lsu_imm_asi_d; // asi state value from imm
116 95 fafa1971 
input ifu_lsu_imm_asi_vld_d; // valid asi state value from imm
117 
 
118 
input [3:0]       tlu_tickcmp_sel;  // select src for tickcmp
119 
input [3:0]       tlu_tickcmp_en_l; // tick cmp reg write enable
120 
input        tlu_tick_en_l;        // tick reg write enable
121 
 
122 
// overflow for the pic registers - lvl15 int
123 
// input  [`TLU_THRD_NUM-1:0] pib_pic_wrap;
124 113 albert.wat 
input  [`TLU_THRD_NUM-1:0] pib_pich_wrap;
125 
input  [`TLU_THRD_NUM-1:0] pib_picl_wrap;
126 95 fafa1971 
 
127 
input [7:0]  exu_tlu_ccr0_w;  // ccr - thread0
128 
input [7:0]  exu_tlu_ccr1_w;  // ccr - thread1
129 
input [7:0]  exu_tlu_ccr2_w;  // ccr - thread2
130 
input [7:0]  exu_tlu_ccr3_w;  // ccr - thread3
131 
// input [2:0]  exu_tlu_cwp0_w;  // cwp - thread0
132 
// input [2:0]  exu_tlu_cwp1_w;  // cwp - thread1
133 
// input [2:0]  exu_tlu_cwp2_w;  // cwp - thread2
134 
// input [2:0]  exu_tlu_cwp3_w;  // cwp - thread3
135 
input [2:0]  exu_tlu_cwp0;  // cwp - thread0
136 
input [2:0]  exu_tlu_cwp1;  // cwp - thread1
137 
input [2:0]  exu_tlu_cwp2;  // cwp - thread2
138 
input [2:0]  exu_tlu_cwp3;  // cwp - thread3
139 
// added for bug3499
140 113 albert.wat 
input [`TLU_THRD_NUM-1:0] tlu_trap_cwp_en;
141 95 fafa1971 
// modified due to bug 3017
142 
// input [47:0] ifu_tlu_pc_m;     // pc
143 
// input [47:0] ifu_tlu_npc_m;   // npc
144 
// modified due to redistribution of logic
145 
// input [48:0] ifu_tlu_pc_m;     // pc
146 
// input [48:0] ifu_tlu_npc_m;   // npc
147 
input [48:0] tlu_pc_new_w;         // pc
148 
input [48:0] tlu_npc_new_w;   // npc
149 
 
150 
input [3:0]       tlu_sftint_en_l_g; // wr enable for sftint regs.
151 
input [3:0]       tlu_sftint_mx_sel; // mux select for sftint regs
152 
input        tlu_set_sftint_l_g;       // set sftint
153 
input        tlu_clr_sftint_l_g;       // clr sftint
154 
input        tlu_wr_sftint_l_g;        // wr to sftin (asr 16)
155 
//
156 
// removed due to sftint recode
157 
// input [3:0]   tlu_sftint_lvl14_int;  // sftint lvl 14 plus tick int
158 
input [3:0]       tlu_sftint_penc_sel;
159 
input [3:0]       tlu_tba_en_l;             // tba reg write enable
160 
// logic moved to tlu_misctl
161 
// input                 tlu_retry_inst_m;         // valid retry inst
162 
// input                 tlu_done_inst_m;          // valid done inst
163 
// input                 tlu_dnrtry_inst_m;        // valid done/retry inst - g
164 
// input                 tlu_dnrtry_inst_m_l;      // valid done/retry inst - g
165 
// input [3:0]   tlu_update_pc_l_m;        // update pc or npc for a thread
166 
input [3:0]       tlu_update_pc_l_w;        // update pc or npc for a thread
167 
// modified due to timing
168 
// input                 tlu_self_boot_rst_g;
169 
// input                 tlu_tl_gt_0_g;            // trp lvl gt then 0
170 
// input                 tlu_select_tba_g;
171 
// input tlu_select_htba_g;   // choosing htba for forming trappc/trapnpc
172 
// input tlu_self_boot_rst_w2;
173 
// added for one-hot mux problem
174 
input [2:0] tlu_pc_mxsel_w2;
175 
input tlu_tl_gt_0_w2;     // trp lvl gt then 0
176 
input tlu_select_tba_w2;
177 113 albert.wat 
input [`TLU_THRD_NUM-1:0] tlu_update_pstate_l_w2; // pstate write enable
178 
input [`TLU_THRD_NUM-1:0] tlu_thrd_rsel_e; // read select for threaded regs
179 95 fafa1971 
input [3:0] tlu_pil;     // mx'ed pil
180 
input [2:0] tlu_trp_lvl; // mx'ed trp lvl
181 
 
182 
input tlu_select_redmode;
183 
input tlu_tick_npt;       // npt bit of tick
184 
 
185 113 albert.wat 
input [`TLU_ASR_DATA_WIDTH-4:0] tlu_tick_incr_dout;
186 95 fafa1971 
//
187 
// added and/or modified for hypervisor support
188 
input [1:0] tlu_hpstate_din_sel0; // sel source of tsa wdata
189 
input [1:0] tlu_hpstate_din_sel1; // sel source of tsa wdata
190 
input [1:0] tlu_hpstate_din_sel2; // sel source of tsa wdata
191 
input [1:0] tlu_hpstate_din_sel3; // sel source of tsa wdata
192 113 albert.wat 
input [`TLU_THRD_NUM-1:0] tlu_stickcmp_en_l; // stick cmp reg write enable
193 
input [`TLU_THRD_NUM-1:0] tlu_htickcmp_en_l; // htick cmp reg write enable
194 
input [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g;    // wr control for hintp regs.
195 
input [`TLU_THRD_NUM-1:0] tlu_set_hintp_sel_g; // set control for hintp regs.
196 
input [`TLU_THRD_NUM-1:0] tlu_htba_en_l;     // htba reg write enable
197 
input [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_w2; // hpstate write enable
198 95 fafa1971 
input tlu_htickcmp_intdis; // int. disable bit of htick-cmp
199 113 albert.wat 
input [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl0; // global register value t0
200 
input [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl1; // global register value t1
201 
input [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl2; // global register value t2
202 
input [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl3; // global register value t3
203 95 fafa1971 
// mux select to read the new ASR registers
204 
input [3:1] tlu_rdpr_mx1_sel;
205 
input [3:1] tlu_rdpr_mx2_sel;
206 
input [2:1] tlu_rdpr_mx3_sel;
207 
input [2:1] tlu_rdpr_mx4_sel;
208 
input [3:1] tlu_rdpr_mx5_sel;
209 
input [2:0] tlu_rdpr_mx6_sel;
210 
input [3:0] tlu_rdpr_mx7_sel;
211 
//
212 113 albert.wat 
input [`TLU_THRD_NUM-1:0] ctu_sscan_tid;
213 
input [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // rsr data from pib
214 95 fafa1971 
 
215 
input si; // scan-in
216 
input se; // scan-en
217 
 
218 
/*AUTOOUTPUT*/
219 
// Beginning of automatic outputs (from unused autoinst outputs)
220 
// End of automatics
221 
//
222 
// modified due to bug 3017
223 
output [48:0] tlu_restore_pc_w1;  // trap pc or pc on retry.
224 
output [48:0] tlu_restore_npc_w1; // trap pc or pc on retry.
225 
output [33:0] tlu_partial_trap_pc_w1;
226 
// the tlu_exu_rsr_data_e will become obsolete, to be removed
227 
// added for timing
228 
// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_e; // rsr data to exu
229 113 albert.wat 
output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_m; // rsr data to exu
230 95 fafa1971 
// modified due to timing violations
231 
// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // trap pc or pc on retry.
232 
//
233 
// modified for hypervisor support
234 113 albert.wat 
output [`TLU_TSA_WIDTH-1:0] tsa_wdata; // wr data for tsa.
235 95 fafa1971 
//
236 113 albert.wat 
output [`TLU_THRD_NUM-1:0] tlu_int_pstate_ie;   // interrupt enable
237 
output [`TLU_THRD_NUM-1:0] local_pstate_ie;   // interrupt enable
238 
output [`TLU_THRD_NUM-1:0] tlu_ifu_pstate_pef;  // fp enable
239 
output [`TLU_THRD_NUM-1:0] tlu_lsu_pstate_cle;  // current little endian
240 
output [`TLU_THRD_NUM-1:0] tlu_lsu_pstate_priv; // privilege mode
241 
output [`TLU_THRD_NUM-1:0] tlu_int_redmode;        // redmode
242 
output [`TLU_THRD_NUM-1:0] tlu_lsu_redmode;        // redmode
243 95 fafa1971 
// modified for bug 1767
244 
// output   [1:0] tlu_pstate0_mmodel; // mem. model - thread0
245 
// output   [1:0] tlu_pstate1_mmodel; // mem. model - thread1
246 
// output   [1:0] tlu_pstate2_mmodel; // mem. model - thread2
247 
// output   [1:0] tlu_pstate3_mmodel; // mem. model - thread3
248 
// output   [3:0] tlu_pstate_tle;         // trap little endian
249 
// output [`TLU_THRD_NUM-1:0] tlu_pstate_cle;  // current little endian
250 
// output [`TLU_THRD_NUM-1:0] tlu_pstate_priv; // privilege mode
251 113 albert.wat 
output [`TLU_THRD_NUM-1:0] tlu_pstate_am;   // address mask
252 95 fafa1971 
//
253 
// removed for bug 2187
254 
// output [`TLU_THRD_NUM-1:0] tlu_sftint_lvl14;
255 113 albert.wat 
output [`TLU_THRD_NUM-1:0] tlu_hpstate_priv; // hypervisor privilege
256 
output [`TLU_THRD_NUM-1:0] tlu_hpstate_enb;  // hypervisor lite enb
257 
output [`TLU_THRD_NUM-1:0] tlu_hpstate_tlz;  // hypervisor tlz
258 
output [`TLU_THRD_NUM-1:0] tlu_hpstate_ibe;  // hypervisor instruction brkpt
259 
output [`TLU_THRD_NUM-1:0] local_hpstate_priv; // hypervisor privilege
260 
output [`TLU_THRD_NUM-1:0] tcl_hpstate_priv; // hypervisor privilege
261 
output [`TLU_THRD_NUM-1:0] local_pstate_priv;  // pstate privilege
262 
output [`TLU_THRD_NUM-1:0] local_hpstate_enb;  // hypervisor lite enb
263 
output [`TLU_THRD_NUM-1:0] tcl_hpstate_enb;  // hypervisor lite enb
264 95 fafa1971 
output [3:0] tlu_sftint_id;
265 
// output       tlu_tick_match; // tick to tick cmp match
266 
// output       tlu_stick_match;        // stick to tick cmp match
267 
// output       tlu_htick_match;        // htick to tick cmp match
268 
// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_tick_incr_din;
269 113 albert.wat 
output [`TLU_ASR_DATA_WIDTH-3:0] tlu_tick_incr_din;
270 95 fafa1971 
//
271 
// modified for hypervisor support
272 
// output       [2:0]   tlu_restore_globals; // restored global regs
273 
//
274 113 albert.wat 
output [`TSA_GLOBAL_WIDTH-1:0] tlu_dnrtry_global_g; // restored globals
275 
output [`TLU_THRD_NUM-1:0]     tlu_hintp;
276 95 fafa1971 
//
277 
// current asi state
278 113 albert.wat 
output [`TLU_ASI_STATE_WIDTH-1:0] tlu_asi_state_e;
279 95 fafa1971 
//
280 
// modified due to race key word limitation
281 
// output [62:0] tlu_sscan_test_data;
282 113 albert.wat 
output [`TDP_SSCAN_WIDTH-1:0] tlu_sscan_test_data;
283 95 fafa1971 
output            so; // scan-out;
284 
 
285 
/*AUTOWIRE*/
286 
// Beginning of automatic wires (for undeclared instantiated-module outputs)
287 
// End of automatics
288 
//
289 
// local reset was added to abide to the Niagara reset methodology
290 
wire        local_rst; // local reset
291 
wire        se_l; // testmode_l replacement
292 
//
293 
// rdpr muxe outputs
294 113 albert.wat 
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_rdpr_mx1_out;
295 95 fafa1971 
wire [3:0]  tlu_rdpr_mx2_out;
296 113 albert.wat 
wire [`SFTINT_WIDTH-1:0]  tlu_rdpr_mx3_out;
297 
wire [`RDSR_TSTATE_WIDTH-1:0]  tlu_rdpr_mx4_out;
298 95 fafa1971 
//
299 
// constructing one-hot selects
300 
wire rdpr_mx1_onehot_sel, rdpr_mx2_onehot_sel;
301 
wire rdpr_mx3_onehot_sel, rdpr_mx4_onehot_sel;
302 
wire rdpr_mx5_onehot_sel, rdpr_mx6_onehot_sel;
303 
//
304 
wire  [32:0] true_tba0,true_tba1,true_tba2,true_tba3;
305 
wire  [60:0] true_tick;
306 
// modified due to bug 3017
307 
wire  [48:0] true_pc0,true_pc1,true_pc2,true_pc3;
308 
// wire  [47:0] sscan_pc;
309 113 albert.wat 
wire  [`TDP_SSCAN_WIDTH-1:0] sscan_data_test0;
310 
wire  [`TDP_SSCAN_WIDTH-1:0] sscan_data_test1;
311 
wire  [`TDP_SSCAN_WIDTH-1:0] sscan_data_test2;
312 
wire  [`TDP_SSCAN_WIDTH-1:0] sscan_data_test3;
313 
wire  [`TDP_SSCAN_WIDTH-1:0] tdp_sscan_test_data;
314 
wire  [`TLU_THRD_NUM-1:0] sscan_tid_sel;
315 95 fafa1971 
wire  [48:0] true_npc0,true_npc1,true_npc2,true_npc3;
316 
// wire  [47:0] true_npc0,true_npc1,true_npc2,true_npc3;
317 
// wire  [47:0] true_pc0,true_pc1,true_pc2,true_pc3;
318 
// wire  [47:0] sscan_pc;
319 
// wire  [47:0] normal_trap_pc, normal_trap_npc;
320 
//
321 
// modified for hypervisor support
322 113 albert.wat 
wire [`TLU_TSA_WIDTH-1:0] trap_tsa_wdata;
323 
wire [`TLU_TSA_WIDTH-1:0] trap0_tsa_wdata,trap1_tsa_wdata;
324 
wire [`TLU_TSA_WIDTH-1:0] trap2_tsa_wdata,trap3_tsa_wdata;
325 
wire [`TLU_TSA_WIDTH-1:0] wrpr_tsa_wdata;
326 
wire [`TLU_TSA_WIDTH-1:0] tsa_wdata;
327 
wire [`RDSR_TSTATE_WIDTH-1:0]  tstate_rdata;
328 95 fafa1971 
wire [1:0]  tstate_dummy_zero;
329 113 albert.wat 
wire [`WSR_TSTATE_WIDTH-1:0]   compose_tstate;
330 
wire [`TSA_HTSTATE_WIDTH-1:0]  compose_htstate;
331 
wire [`TSA_GLOBAL_WIDTH-1:0]   global_rdata;
332 95 fafa1971 
// wire [`TLU_ASR_DATA_WIDTH-1:0] wsr_data_w;
333 113 albert.wat 
wire [`SFTINT_WIDTH-1:0] wsr_data_w;
334 95 fafa1971 
// reduced width to 48 due to lint violations
335 
wire [47:0] wsr_data_w2;
336 
//
337 
// modified for bug 3017
338 
// wire  [47:2] trap_pc0,trap_pc1,trap_pc2,trap_pc3;
339 
// wire  [47:2] trap_npc0,trap_npc1,trap_npc2,trap_npc3;
340 
wire  [48:2] trap_pc0,trap_pc1,trap_pc2,trap_pc3;
341 
wire  [48:2] trap_npc0,trap_npc1,trap_npc2,trap_npc3;
342 
wire   [7:0] trap_ccr0,trap_ccr1,trap_ccr2,trap_ccr3;
343 
wire   [7:0] trap_asi0,trap_asi1,trap_asi2,trap_asi3;
344 
wire   [2:0] trap_cwp0,trap_cwp1,trap_cwp2,trap_cwp3;
345 
wire   [2:0] tlu_cwp0,tlu_cwp1,tlu_cwp2,tlu_cwp3;
346 113 albert.wat 
wire   [`TLU_ASI_STATE_WIDTH-1:0] imm_asi_e;
347 
wire   [`TLU_ASI_STATE_WIDTH-1:0] asi_state_reg_e;
348 
wire   [`TLU_ASI_STATE_WIDTH-1:0] asi_state_final_e;
349 95 fafa1971 
wire   imm_asi_vld_e;
350 
//
351 
// modified due to tickcmp, stickcmp and sftint cleanup
352 
// wire  [15:0] sftint0, sftint1, sftint2, sftint3;
353 
// wire  [15:1] sftint_set_din, sftint_clr_din, sftint_wr_din;
354 113 albert.wat 
wire  [`SFTINT_WIDTH-1:0] sftint0, sftint1, sftint2, sftint3;
355 
wire  [`SFTINT_WIDTH-1:0] sftint_set_din, sftint_clr_din, sftint_wr_din;
356 
wire [`SFTINT_WIDTH-1:0] sftint_din;
357 
wire [`SFTINT_WIDTH-1:0] sftint;
358 
wire [`TLU_THRD_NUM-1:0] sftint_b0_din;
359 
wire [`TLU_THRD_NUM-1:0] sftint_b0_en;
360 
wire [`TLU_THRD_NUM-1:0] sftint_b15_din;
361 
wire [`TLU_THRD_NUM-1:0] sftint_b15_en;
362 
wire [`TLU_THRD_NUM-1:0] sftint_b16_din;
363 
wire [`TLU_THRD_NUM-1:0] sftint_b16_en;
364 
wire [`TLU_THRD_NUM-1:0] sftint_lvl14;
365 95 fafa1971 
wire [3:0] sftin_din_mxsel;
366 
// recoded for one-hot problem during reset
367 
// wire sftint_sel_onehot_g;
368 
//
369 
// added for PIB support
370 
wire         tcmp0_clk, tcmp1_clk;
371 
wire         tcmp2_clk, tcmp3_clk;
372 
wire [14:0]  sftint_penc_din;
373 
wire         sftint0_clk,sftint1_clk;
374 
wire         sftint2_clk,sftint3_clk;
375 
//
376 
wire [32:0] tba_data;
377 
wire [32:0] tba_rdata;
378 
wire [33:0] tlu_rstvaddr_base;
379 113 albert.wat 
wire [`TLU_HTBA_WIDTH-1:0] htba_data;
380 95 fafa1971 
wire        tba0_clk,tba1_clk,tba2_clk,tba3_clk;
381 
// modified for bug 3017
382 
// wire [46:0] tsa_pc_m,tsa_npc_m;
383 
// wire [48:0] dnrtry_pc,dnrtry_npc;
384 
wire [48:0] restore_pc_w2;
385 
wire [48:0] restore_npc_w2;
386 
// wire [48:0]  pc_new, npc_new;
387 
// wire [48:0]  pc_new_w, npc_new_w;
388 
wire [33:0] partial_trap_pc_w2;
389 
wire        pc0_clk,pc1_clk,pc2_clk,pc3_clk;
390 
// wire [`TLU_TSA_WIDTH-1:0] tsa_data_m;
391 113 albert.wat 
wire [`TLU_ASR_DATA_WIDTH-1:0] true_tickcmp0, true_tickcmp1;
392 
wire [`TLU_ASR_DATA_WIDTH-1:0] true_tickcmp2, true_tickcmp3;
393 
wire [`TLU_ASR_DATA_WIDTH-1:0] tickcmp_rdata;
394 
wire [`TLU_THRD_NUM-1:0] tickcmp_intdis_din;
395 
wire [`TLU_THRD_NUM-1:0] tickcmp_intdis_en;
396 
wire [`TLU_THRD_NUM-1:0] tickcmp_int;
397 
wire [`TLU_THRD_NUM-1:0] tlu_set_hintp_g;
398 
wire [`TLU_THRD_NUM-1:0] tlu_hintp_en_l_g;
399 95 fafa1971 
wire tlu_htick_match;   // htick to tick cmp match
400 
wire tick_match;
401 113 albert.wat 
wire [`TLU_ASR_DATA_WIDTH-4:0] tickcmp_data;
402 
wire [`TLU_ASR_DATA_WIDTH-2:2] tick_din;
403 95 fafa1971 
// reg   [`TLU_ASR_DATA_WIDTH-1:0] tlu_rsr_data_e;
404 113 albert.wat 
wire [`PSTATE_TRUE_WIDTH-1:0] true_pstate0,true_pstate1;
405 
wire [`PSTATE_TRUE_WIDTH-1:0] true_pstate2,true_pstate3;
406 95 fafa1971 
// wire [`TLU_THRD_NUM-1:0] tlu_pstate_priv; // privilege mode
407 
// added for hypervisor support
408 113 albert.wat 
wire [`TSA_PSTATE_WIDTH-1:0] trap_pstate0,trap_pstate1;
409 
wire [`TSA_PSTATE_WIDTH-1:0] trap_pstate2,trap_pstate3;
410 95 fafa1971 
//
411 
// wire [`PSTATE_TRUE_WIDTH-1:0] dnrtry_pstate;
412 
// wire [`PSTATE_TRUE_WIDTH-1:0] dnrtry_pstate_m;
413 
// wire [`PSTATE_TRUE_WIDTH-1:0] wsr_data_pstate_g;
414 113 albert.wat 
wire [`WSR_PSTATE_VR_WIDTH-1:0] dnrtry_pstate_m;
415 
wire [`WSR_PSTATE_VR_WIDTH-1:0] dnrtry_pstate_g;
416 
wire [`WSR_PSTATE_VR_WIDTH-1:0] dnrtry_pstate_w2;
417 95 fafa1971 
// removed for timing
418 
// wire [`WSR_PSTATE_VR_WIDTH-1:0] wsr_data_pstate_g;
419 113 albert.wat 
wire [`WSR_PSTATE_VR_WIDTH-1:0] wsr_data_pstate_w2;
420 95 fafa1971 
//
421 
// modified for bug 1767
422 
//wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate;
423 
// wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate0;
424 
// wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate1;
425 
// wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate2;
426 
// wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate3;
427 113 albert.wat 
wire [`WSR_PSTATE_VR_WIDTH-1:0] ntrap_pstate0;
428 
wire [`WSR_PSTATE_VR_WIDTH-1:0] ntrap_pstate1;
429 
wire [`WSR_PSTATE_VR_WIDTH-1:0] ntrap_pstate2;
430 
wire [`WSR_PSTATE_VR_WIDTH-1:0] ntrap_pstate3;
431 95 fafa1971 
// modified for bug 2161 and 2584
432 
wire pstate_priv_set, hpstate_priv_set;
433 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] pstate_priv_thrd_set;
434 95 fafa1971 
// wire [`TLU_THRD_NUM-1:0] pstate_priv_update_g;
435 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] pstate_priv_update_w2;
436 95 fafa1971 
// wire [`TLU_THRD_NUM-1:0] hpstate_dnrtry_priv_g;
437 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] hpstate_dnrtry_priv_w2;
438 
wire [`TLU_THRD_NUM-1:0] hpstate_enb_set;
439 
wire [`TLU_THRD_NUM-1:0] hpstate_ibe_set;
440 
wire [`TLU_THRD_NUM-1:0] hpstate_tlz_set;
441 95 fafa1971 
// wire [`TLU_THRD_NUM-1:0] hpstate_priv_update_g;
442 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] hpstate_priv_update_w2;
443 95 fafa1971 
//
444 
// removed for bug 2588
445 
// wire [1:0] tlu_select_mmodel0;
446 
// wire [1:0] tlu_select_mmodel1;
447 
// wire [1:0] tlu_select_mmodel2;
448 
// wire [1:0] tlu_select_mmodel3;
449 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] tlu_select_tle;
450 
wire [`TLU_THRD_NUM-1:0] tlu_select_cle;
451 95 fafa1971 
// wire [1:0] tlu_pstate0_mmodel;       // mem. model - thread0
452 
// wire [1:0] tlu_pstate1_mmodel;       // mem. model - thread1
453 
// wire [1:0] tlu_pstate2_mmodel;       // mem. model - thread2
454 
// wire [1:0] tlu_pstate3_mmodel;       // mem. model - thread3
455 113 albert.wat 
wire [`TLU_THRD_NUM-1:0] tlu_pstate_tle; // trap little endian
456 95 fafa1971 
//
457 
// modified for bug 1575
458 
// wire [`PSTATE_TRUE_WIDTH-1:0]        restore_pstate;
459 
// wire [`PSTATE_TRUE_WIDTH-1:0]        restore_pstate0;
460 
// wire [`PSTATE_TRUE_WIDTH-1:0]        restore_pstate1;
461 
// wire [`PSTATE_TRUE_WIDTH-1:0]        restore_pstate2;
462 
// wire [`PSTATE_TRUE_WIDTH-1:0]        restore_pstate3;
463 113 albert.wat 
wire [`WSR_PSTATE_VR_WIDTH-1:0]  restore_pstate0;
464 
wire [`WSR_PSTATE_VR_WIDTH-1:0]  restore_pstate1;
465 
wire [`WSR_PSTATE_VR_WIDTH-1:0]  restore_pstate2;
466 
wire [`WSR_PSTATE_VR_WIDTH-1:0]  restore_pstate3;
467 
wire [`WSR_PSTATE_VR_WIDTH-1:0]  restore_pstate0_w3;
468 
wire [`WSR_PSTATE_VR_WIDTH-1:0]  restore_pstate1_w3;
469 
wire [`WSR_PSTATE_VR_WIDTH-1:0]  restore_pstate2_w3;
470 
wire [`WSR_PSTATE_VR_WIDTH-1:0]  restore_pstate3_w3;
471 95 fafa1971 
wire tlu_pstate_nt_sel0, tlu_pstate_nt_sel1;
472 
wire tlu_pstate_nt_sel2, tlu_pstate_nt_sel3;
473 
wire tlu_pstate_wsr_sel0, tlu_pstate_wsr_sel1;
474 
wire tlu_pstate_wsr_sel2, tlu_pstate_wsr_sel3;
475 
wire hpstate_redmode;
476 
wire pstate0_clk,pstate1_clk,pstate2_clk,pstate3_clk;
477 
 
478 
//
479 
// added or modified for hypervisor support
480 
// wire [2:0]   global_sel;
481 
wire stcmp0_clk, stcmp1_clk, stcmp2_clk, stcmp3_clk;
482 
wire htcmp0_clk, htcmp1_clk, htcmp2_clk, htcmp3_clk;
483 
wire tlu_hpstate_hnt_sel0, tlu_hpstate_hnt_sel1;
484 
wire tlu_hpstate_hnt_sel2, tlu_hpstate_hnt_sel3;
485 
wire tlu_hpstate_wsr_sel0, tlu_hpstate_wsr_sel1;
486 
wire tlu_hpstate_wsr_sel2, tlu_hpstate_wsr_sel3;
487 
wire pc_bit15_sel;
488 
wire htba0_clk,htba1_clk,htba2_clk,htba3_clk;
489 
wire hpstate0_clk,hpstate1_clk,hpstate2_clk,hpstate3_clk;
490 
wire hintp0_clk,hintp1_clk,hintp2_clk,hintp3_clk;
491 
wire hintp_rdata;
492 113 albert.wat 
wire [`TLU_THRD_NUM-1:0]       hintp_din;
493 95 fafa1971 
// added or modified due to stickcmp clean-up
494 
// wire [`TLU_ASR_DATA_WIDTH-2:0] stickcmp_rdata;
495 
// wire [`TLU_ASR_DATA_WIDTH-2:0] true_stickcmp0, true_stickcmp1;
496 
// wire [`TLU_ASR_DATA_WIDTH-2:0] true_stickcmp2, true_stickcmp3;
497 113 albert.wat 
wire [`TLU_ASR_DATA_WIDTH-1:0] stickcmp_rdata;
498 
wire [`TLU_ASR_DATA_WIDTH-1:0] true_stickcmp0, true_stickcmp1;
499 
wire [`TLU_ASR_DATA_WIDTH-1:0] true_stickcmp2, true_stickcmp3;
500 
wire [`TLU_THRD_NUM-1:0] stickcmp_intdis_din;
501 
wire [`TLU_THRD_NUM-1:0] stickcmp_intdis_en;
502 
wire [`TLU_THRD_NUM-1:0] stickcmp_int;
503 95 fafa1971 
wire stick_match;
504 113 albert.wat 
wire [`TLU_ASR_DATA_WIDTH-4:0] stickcmp_data;
505 95 fafa1971 
//
506 113 albert.wat 
wire [`TLU_ASR_DATA_WIDTH-2:0] htickcmp_rdata;
507 
wire [`TLU_ASR_DATA_WIDTH-4:0] htickcmp_data;
508 
wire [`TLU_ASR_DATA_WIDTH-2:0] true_htickcmp0, true_htickcmp1;
509 
wire [`TLU_ASR_DATA_WIDTH-2:0] true_htickcmp2, true_htickcmp3;
510 
wire [`TLU_HPSTATE_WIDTH-1:0]  true_hpstate0,true_hpstate1;
511 
wire [`TLU_HPSTATE_WIDTH-1:0]  true_hpstate2,true_hpstate3;
512 
wire [`TLU_HPSTATE_WIDTH-1:0]  true_hpstate;
513 
wire [`TSA_HTSTATE_WIDTH-1:0]  tsa_dnrtry_hpstate_m;
514 
wire [`TSA_HTSTATE_WIDTH-1:0]  tsa_dnrtry_hpstate_g;
515 
wire [`TSA_HTSTATE_WIDTH-1:0]  tsa_dnrtry_hpstate_w2;
516 95 fafa1971 
// wire [`TLU_HPSTATE_WIDTH-1:0]  dnrtry_hpstate0_g, dnrtry_hpstate1_g;
517 113 albert.wat 
wire [`TLU_HPSTATE_WIDTH-1:0]  dnrtry_hpstate0_w2, dnrtry_hpstate1_w2;
518 95 fafa1971 
// wire [`TLU_HPSTATE_WIDTH-1:0]  dnrtry_hpstate2_g, dnrtry_hpstate3_g;
519 113 albert.wat 
wire [`TLU_HPSTATE_WIDTH-1:0]  dnrtry_hpstate2_w2, dnrtry_hpstate3_w2;
520 95 fafa1971 
// wire [`TLU_HPSTATE_WIDTH-1:0]  hntrap_hpstate0_g, hntrap_hpstate1_g;
521 113 albert.wat 
wire [`TLU_HPSTATE_WIDTH-1:0]  hntrap_hpstate0_w2, hntrap_hpstate1_w2;
522 95 fafa1971 
// wire [`TLU_HPSTATE_WIDTH-1:0]  hntrap_hpstate2_g, hntrap_hpstate3_g;
523 113 albert.wat 
wire [`TLU_HPSTATE_WIDTH-1:0]  hntrap_hpstate2_w2, hntrap_hpstate3_w2;
524 
wire [`TLU_HPSTATE_WIDTH-1:0]  wsr_data_hpstate_w2;
525 
wire [`TLU_HPSTATE_WIDTH-1:0]  restore_hpstate0, restore_hpstate1;
526 
wire [`TLU_HPSTATE_WIDTH-1:0]  restore_hpstate2, restore_hpstate3;
527 
wire [`TLU_HTBA_WIDTH-1:0]          true_htba0, true_htba1;
528 
wire [`TLU_HTBA_WIDTH-1:0]          true_htba2, true_htba3;
529 
wire [`TSA_GLOBAL_WIDTH-1:0]   dnrtry_global_m;
530 
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_rdpr_mx5_out;
531 
wire [`SFTINT_WIDTH-1:0]       tlu_rdpr_mx6_out;
532 
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_rdpr_mx7_out;
533 
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_e;
534 95 fafa1971 
wire clk;
535 
//
536 
//=========================================================================================
537 
// create local reset
538 
 
539 
assign local_rst = tlu_rst;
540 
assign se_l = ~se;
541 
 
542 
// clock rename
543 
assign clk = rclk;
544 
 
545 
//=========================================================================================
546 
// Design Notes :
547 
// HTSTATE-            4 (ENB from HPSTATE is not saved)
548 
// TPC-               47 (48-2)VA+(1)VA_HOLE
549 
// TNPC-                  47 (48-2)VA+(1)VA_HOLE
550 
// TSTATE.GL-      2 (Only two significant bits are saved)
551 
// TSTATE.CCR-     8
552 
// TSTATE.ASI-     8
553 
// TSTATE.PSTATE-  8 (RED, IG, MG and AG bits are not used)
554 
// TSTATE.CWP-     3
555 
// TRAPTYPE-       9
556 
//========================================================
557 
// Total         136
558 
 
559 
//=========================================================================================
560 
//      Timing Diagram
561 
//=========================================================================================
562 
 
563 
 
564 
// WRITE TO TSA and other trap related registers.
565 
//      |       |       |               |               |
566 
//      |E      |M      |       W       |       W2      | Integer
567 
//      |       |       | exceptions    | push tsa      |
568 
//      |       |       | reported      | xmit pc       |
569 
//      |       |       |               |               |
570 
//      |E      |M      |       G       |       W2      | Long-Latency
571 
//      |       |       | exceptions    |               |
572 
//      |       |       | reported      | push tsa      |
573 
//      |       |       |               | xmit pc       |
574 
 
575 
//=========================================================================================
576 
//      Generate TSA Control and Data
577 
//=========================================================================================
578 
 
579 
// modified for bug 3017
580 
assign  trap_pc0[48:2] =  true_pc0[48:2];
581 
assign  trap_pc1[48:2] =  true_pc1[48:2];
582 
assign  trap_pc2[48:2] =  true_pc2[48:2];
583 
assign  trap_pc3[48:2] =  true_pc3[48:2];
584 
 
585 
assign  trap_npc0[48:2] = true_npc0[48:2];
586 
assign  trap_npc1[48:2] = true_npc1[48:2];
587 
assign  trap_npc2[48:2] = true_npc2[48:2];
588 
assign  trap_npc3[48:2] = true_npc3[48:2];
589 
 
590 
assign  trap_ccr0[7:0] = exu_tlu_ccr0_w[7:0];
591 
assign  trap_ccr1[7:0] = exu_tlu_ccr1_w[7:0];
592 
assign  trap_ccr2[7:0] = exu_tlu_ccr2_w[7:0];
593 
assign  trap_ccr3[7:0] = exu_tlu_ccr3_w[7:0];
594 
 
595 
// assign       trap_cwp0[2:0] = exu_tlu_cwp0_w[2:0];
596 
// assign       trap_cwp1[2:0] = exu_tlu_cwp1_w[2:0];
597 
// assign       trap_cwp2[2:0] = exu_tlu_cwp2_w[2:0];
598 
// assign       trap_cwp3[2:0] = exu_tlu_cwp3_w[2:0];
599 
//
600 
// added for bug 3695
601 113 albert.wat 
dff_s #(3) dff_tlu_cwp0 (
602 95 fafa1971 
    .din (exu_tlu_cwp0[2:0]),
603 
    .q   (tlu_cwp0[2:0]),
604 
    .clk (clk),
605 
    .se  (se),
606 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
607 95 fafa1971 
    .so  ()
608 
);
609 
 
610 113 albert.wat 
dff_s #(3) dff_tlu_cwp1 (
611 95 fafa1971 
    .din (exu_tlu_cwp1[2:0]),
612 
    .q   (tlu_cwp1[2:0]),
613 
    .clk (clk),
614 
    .se  (se),
615 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
616 95 fafa1971 
    .so  ()
617 
);
618 
 
619 113 albert.wat 
dff_s #(3) dff_tlu_cwp2 (
620 95 fafa1971 
    .din (exu_tlu_cwp2[2:0]),
621 
    .q   (tlu_cwp2[2:0]),
622 
    .clk (clk),
623 
    .se  (se),
624 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
625 95 fafa1971 
    .so  ()
626 
);
627 
 
628 113 albert.wat 
dff_s #(3) dff_tlu_cwp3 (
629 95 fafa1971 
    .din (exu_tlu_cwp3[2:0]),
630 
    .q   (tlu_cwp3[2:0]),
631 
    .clk (clk),
632 
    .se  (se),
633 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
634 95 fafa1971 
    .so  ()
635 
);
636 
//
637 
// modified for bug 3499 and 3695
638 113 albert.wat 
dffe_s #(3) dffe_trap_cwp0 (
639 95 fafa1971 
    // .din (exu_tlu_cwp0[2:0]),
640 
    .din (tlu_cwp0[2:0]),
641 
    .q   (trap_cwp0[2:0]),
642 
    .en  (tlu_trap_cwp_en[0]),
643 
    .clk (clk),
644 
    .se  (se),
645 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
646 95 fafa1971 
    .so  ()
647 
);
648 
 
649 113 albert.wat 
dffe_s #(3) dffe_trap_cwp1 (
650 95 fafa1971 
    // .din (exu_tlu_cwp1[2:0]),
651 
    .din (tlu_cwp1[2:0]),
652 
    .q   (trap_cwp1[2:0]),
653 
    .en  (tlu_trap_cwp_en[1]),
654 
    .clk (clk),
655 
    .se  (se),
656 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
657 95 fafa1971 
    .so  ()
658 
);
659 
 
660 113 albert.wat 
dffe_s #(3) dffe_trap_cwp2 (
661 95 fafa1971 
    // .din (exu_tlu_cwp2[2:0]),
662 
    .din (tlu_cwp2[2:0]),
663 
    .q   (trap_cwp2[2:0]),
664 
    .en  (tlu_trap_cwp_en[2]),
665 
    .clk (clk),
666 
    .se  (se),
667 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
668 95 fafa1971 
    .so  ()
669 
);
670 
 
671 113 albert.wat 
dffe_s #(3) dffe_trap_cwp3 (
672 95 fafa1971 
    // .din (exu_tlu_cwp3[2:0]),
673 
    .din (tlu_cwp3[2:0]),
674 
    .q   (trap_cwp3[2:0]),
675 
    .en  (tlu_trap_cwp_en[3]),
676 
    .clk (clk),
677 
    .se  (se),
678 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
679 95 fafa1971 
    .so  ()
680 
);
681 
 
682 
assign  trap_asi0[7:0] = lsu_asi_reg0[7:0];
683 
assign  trap_asi1[7:0] = lsu_asi_reg1[7:0];
684 
assign  trap_asi2[7:0] = lsu_asi_reg2[7:0];
685 
assign  trap_asi3[7:0] = lsu_asi_reg3[7:0];
686 
//
687 
// staging the immediate asi
688 
 
689 113 albert.wat 
dff_s #(`TLU_ASI_STATE_WIDTH) dff_imm_asi_e (
690 
    .din (ifu_lsu_imm_asi_d[`TLU_ASI_STATE_WIDTH-1:0]),
691 
    .q   (imm_asi_e[`TLU_ASI_STATE_WIDTH-1:0]),
692 95 fafa1971 
    .clk (clk),
693 
    .se  (se),
694 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
695 95 fafa1971 
    .so  ()
696 
);
697 
 
698 113 albert.wat 
dffr_s dffr_imm_asi_vld_e (
699 95 fafa1971 
     .din (ifu_lsu_imm_asi_vld_d),
700 
     .q   (imm_asi_vld_e),
701 
     .clk (clk),
702 
         .rst (local_rst),
703 
     .se  (se),
704 113 albert.wat 
     `SIMPLY_RISC_SCANIN,
705 95 fafa1971 
     .so  ()
706 
);
707 
//
708 
// generating the current asi state
709 113 albert.wat 
mux4ds  #(`TLU_ASI_STATE_WIDTH) mx_tlu_asi_state_e (
710 
        .in0    (lsu_asi_reg0[`TLU_ASI_STATE_WIDTH-1:0]),
711 
        .in1    (lsu_asi_reg1[`TLU_ASI_STATE_WIDTH-1:0]),
712 
        .in2    (lsu_asi_reg2[`TLU_ASI_STATE_WIDTH-1:0]),
713 
        .in3    (lsu_asi_reg3[`TLU_ASI_STATE_WIDTH-1:0]),
714 95 fafa1971 
        .sel0   (tlu_thrd_rsel_e[0]),
715 
        .sel1   (tlu_thrd_rsel_e[1]),
716 
        .sel2   (tlu_thrd_rsel_e[2]),
717 
        .sel3   (tlu_thrd_rsel_e[3]),
718 
        // modified due to bug 2442
719 
        // .dout   (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0])
720 113 albert.wat 
        .dout   (asi_state_reg_e[`TLU_ASI_STATE_WIDTH-1:0])
721 95 fafa1971 
);
722 
//
723 
// added for bug 2442
724 
// generating the current asi state
725 113 albert.wat 
mux2ds #(`TLU_ASI_STATE_WIDTH) mx_asi_state_final_e (
726 
       .in0  (imm_asi_e[`TLU_ASI_STATE_WIDTH-1:0]),
727 
           .in1  (asi_state_reg_e[`TLU_ASI_STATE_WIDTH-1:0]),
728 95 fafa1971 
       .sel0 (imm_asi_vld_e),
729 
           .sel1 (~imm_asi_vld_e),
730 113 albert.wat 
       .dout (asi_state_final_e[`TLU_ASI_STATE_WIDTH-1:0])
731 95 fafa1971 
);
732 
 
733 113 albert.wat 
assign tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0] =
734 
           asi_state_final_e[`TLU_ASI_STATE_WIDTH-1:0];
735 95 fafa1971 
//
736 
// thread 0
737 
assign trap_pstate0 = {
738 113 albert.wat 
       true_pstate0[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
739 
       2'b0, true_pstate0[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
740 95 fafa1971 
//
741 
// modified due to hpstate.ibe addition
742 113 albert.wat 
assign trap0_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO] =
743 
       {true_hpstate0[`TLU_HPSTATE_WIDTH-1],
744 
        true_hpstate0[`TSA_HTSTATE_WIDTH-2:0]};
745 95 fafa1971 
//
746 
// modified for bug 3017
747 
//
748 113 albert.wat 
assign trap0_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO] =
749 95 fafa1971 
           trap_pc0[48:2];
750 
//
751 113 albert.wat 
assign trap0_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO] =
752 95 fafa1971 
           trap_npc0[48:2];
753 
//
754 113 albert.wat 
assign trap0_tsa_wdata[`TLU_GL_HI:`TLU_GL_LO] =
755 
       tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0];
756 95 fafa1971 
//
757 113 albert.wat 
assign trap0_tsa_wdata[`TLU_CCR_HI:`TLU_CCR_LO] =
758 
       trap_ccr0[`TSA_CCR_WIDTH-1:0];
759 95 fafa1971 
//
760 113 albert.wat 
assign trap0_tsa_wdata[`TLU_ASI_HI:`TLU_ASI_LO] =
761 
       trap_asi0[`TSA_ASI_WIDTH-1:0];
762 95 fafa1971 
//
763 113 albert.wat 
assign trap0_tsa_wdata[`TLU_PSTATE_HI:`TLU_PSTATE_LO] =
764 
       trap_pstate0[`TSA_PSTATE_WIDTH-1:0];
765 95 fafa1971 
//
766 113 albert.wat 
assign trap0_tsa_wdata[`TLU_CWP_HI:`TLU_CWP_LO] =
767 
       trap_cwp0[`TSA_CWP_WIDTH-1:0];
768 95 fafa1971 
//
769 113 albert.wat 
assign trap0_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO] =
770 
       tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
771 95 fafa1971 
//
772 
// thread 1
773 
assign trap_pstate1 = {
774 113 albert.wat 
       true_pstate1[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
775 
       2'b0, true_pstate1[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
776 95 fafa1971 
//
777 
// modified due to hpstate.ibe addition
778 113 albert.wat 
assign trap1_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO] =
779 
       {true_hpstate1[`TLU_HPSTATE_WIDTH-1],
780 
        true_hpstate1[`TSA_HTSTATE_WIDTH-2:0]};
781 95 fafa1971 
//
782 113 albert.wat 
assign trap1_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO] =
783 95 fafa1971 
           trap_pc1[48:2];
784 
//
785 113 albert.wat 
assign trap1_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO] =
786 95 fafa1971 
           trap_npc1[48:2];
787 
//
788 113 albert.wat 
assign trap1_tsa_wdata[`TLU_GL_HI:`TLU_GL_LO] =
789 
       tlu_gl_lvl1[`TSA_GLOBAL_WIDTH-1:0];
790 95 fafa1971 
//
791 113 albert.wat 
assign trap1_tsa_wdata[`TLU_CCR_HI:`TLU_CCR_LO] =
792 
       trap_ccr1[`TSA_CCR_WIDTH-1:0];
793 95 fafa1971 
//
794 113 albert.wat 
assign trap1_tsa_wdata[`TLU_ASI_HI:`TLU_ASI_LO] =
795 
       trap_asi1[`TSA_ASI_WIDTH-1:0];
796 95 fafa1971 
//
797 113 albert.wat 
assign trap1_tsa_wdata[`TLU_PSTATE_HI:`TLU_PSTATE_LO] =
798 
       trap_pstate1[`TSA_PSTATE_WIDTH-1:0];
799 95 fafa1971 
//
800 113 albert.wat 
assign trap1_tsa_wdata[`TLU_CWP_HI:`TLU_CWP_LO] =
801 
       trap_cwp1[`TSA_CWP_WIDTH-1:0];
802 95 fafa1971 
//
803 113 albert.wat 
assign trap1_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO] =
804 
       tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
805 95 fafa1971 
//
806 
// thread 2
807 
assign trap_pstate2 = {
808 113 albert.wat 
       true_pstate2[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
809 
       2'b0, true_pstate2[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
810 95 fafa1971 
//
811 
// modified due to hpstate.ibe addition
812 113 albert.wat 
assign trap2_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO] =
813 
       {true_hpstate2[`TLU_HPSTATE_WIDTH-1],
814 
        true_hpstate2[`TSA_HTSTATE_WIDTH-2:0]};
815 95 fafa1971 
//
816 113 albert.wat 
assign trap2_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO] =
817 95 fafa1971 
           trap_pc2[48:2];
818 
//
819 113 albert.wat 
assign trap2_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO] =
820 95 fafa1971 
           trap_npc2[48:2];
821 
//
822 113 albert.wat 
assign trap2_tsa_wdata[`TLU_GL_HI:`TLU_GL_LO] =
823 
       tlu_gl_lvl2[`TSA_GLOBAL_WIDTH-1:0];
824 95 fafa1971 
//
825 113 albert.wat 
assign trap2_tsa_wdata[`TLU_CCR_HI:`TLU_CCR_LO] =
826 
       trap_ccr2[`TSA_CCR_WIDTH-1:0];
827 95 fafa1971 
//
828 113 albert.wat 
assign trap2_tsa_wdata[`TLU_ASI_HI:`TLU_ASI_LO] =
829 
       trap_asi2[`TSA_ASI_WIDTH-1:0];
830 95 fafa1971 
//
831 113 albert.wat 
assign trap2_tsa_wdata[`TLU_PSTATE_HI:`TLU_PSTATE_LO] =
832 
       trap_pstate2[`TSA_PSTATE_WIDTH-1:0];
833 95 fafa1971 
//
834 113 albert.wat 
assign trap2_tsa_wdata[`TLU_CWP_HI:`TLU_CWP_LO] =
835 
       trap_cwp2[`TSA_CWP_WIDTH-1:0];
836 95 fafa1971 
//
837 113 albert.wat 
assign trap2_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO] =
838 
       tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
839 95 fafa1971 
//
840 
// thread 3
841 
assign trap_pstate3 = {
842 113 albert.wat 
       true_pstate3[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
843 
       2'b0, true_pstate3[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
844 95 fafa1971 
//
845 
// modified due to hpstate.ibe addition
846 113 albert.wat 
assign trap3_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO] =
847 
       {true_hpstate3[`TLU_HPSTATE_WIDTH-1],
848 
        true_hpstate3[`TSA_HTSTATE_WIDTH-2:0]};
849 95 fafa1971 
//
850 113 albert.wat 
assign trap3_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO] =
851 95 fafa1971 
           trap_pc3[48:2];
852 
//
853 113 albert.wat 
assign trap3_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO] =
854 95 fafa1971 
           trap_npc3[48:2];
855 
//
856 113 albert.wat 
assign trap3_tsa_wdata[`TLU_GL_HI:`TLU_GL_LO] =
857 
       tlu_gl_lvl3[`TSA_GLOBAL_WIDTH-1:0];
858 95 fafa1971 
//
859 113 albert.wat 
assign trap3_tsa_wdata[`TLU_CCR_HI:`TLU_CCR_LO] =
860 
       trap_ccr3[`TSA_CCR_WIDTH-1:0];
861 95 fafa1971 
//
862 113 albert.wat 
assign trap3_tsa_wdata[`TLU_ASI_HI:`TLU_ASI_LO] =
863 
       trap_asi3[`TSA_ASI_WIDTH-1:0];
864 95 fafa1971 
//
865 113 albert.wat 
assign trap3_tsa_wdata[`TLU_PSTATE_HI:`TLU_PSTATE_LO] =
866 
       trap_pstate3[`TSA_PSTATE_WIDTH-1:0];
867 95 fafa1971 
//
868 113 albert.wat 
assign trap3_tsa_wdata[`TLU_CWP_HI:`TLU_CWP_LO] =
869 
       trap_cwp3[`TSA_CWP_WIDTH-1:0];
870 95 fafa1971 
//
871 113 albert.wat 
assign trap3_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO] =
872 
       tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
873 95 fafa1971 
//
874 
// modified for timing: tlu_thrd_wsel_g -> tlu_thrd_wsel_w2
875 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
876 
   assign trap_tsa_wdata[`TLU_TSA_WIDTH-1:0] = trap0_tsa_wdata[`TLU_TSA_WIDTH-1:0];
877 
`else
878 95 fafa1971 
 
879 113 albert.wat 
mux4ds  #(`TLU_TSA_WIDTH) tsawdsel (
880 
        .in0    (trap0_tsa_wdata[`TLU_TSA_WIDTH-1:0]),
881 
        .in1    (trap1_tsa_wdata[`TLU_TSA_WIDTH-1:0]),
882 
        .in2    (trap2_tsa_wdata[`TLU_TSA_WIDTH-1:0]),
883 
        .in3    (trap3_tsa_wdata[`TLU_TSA_WIDTH-1:0]),
884 95 fafa1971 
        .sel0   (tlu_thrd_wsel_w2[0]),
885 
        .sel1   (tlu_thrd_wsel_w2[1]),
886 
        .sel2   (tlu_thrd_wsel_w2[2]),
887 
        .sel3   (tlu_thrd_wsel_w2[3]),
888 113 albert.wat 
        .dout   (trap_tsa_wdata[`TLU_TSA_WIDTH-1:0])
889 95 fafa1971 
);
890 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
891 95 fafa1971 
 
892 
//
893 
// modified for timing and lint violations
894 
// assign wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0] =
895 
//            tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0];
896 113 albert.wat 
assign wsr_data_w[`SFTINT_WIDTH-1:0] =
897 
           tlu_wsr_data_w[`SFTINT_WIDTH-1:0];
898 95 fafa1971 
//
899 
// added for timing
900 
// reduced width to 48 due to lint violations
901 113 albert.wat 
dff_s #(48) dff_wsr_data_w2 (
902 95 fafa1971 
    .din (tlu_wsr_data_w[47:0]),
903 
    .q   (wsr_data_w2[47:0]),
904 
    .clk (clk),
905 
    .se  (se),
906 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
907 95 fafa1971 
    .so  ()
908 
);
909 
//
910 
// extracting the relevant data for tstate from the WSR to be written
911 
// modified due to timing changes
912 113 albert.wat 
assign compose_tstate[`WSR_TSTATE_WIDTH-1:0] =
913 
          {wsr_data_w2[`WSR_TSTATE_GL_HI:`WSR_TSTATE_GL_LO],
914 
       wsr_data_w2[`WSR_TSTATE_CCR_HI:`WSR_TSTATE_CCR_LO],
915 
       wsr_data_w2[`WSR_TSTATE_ASI_HI:`WSR_TSTATE_ASI_LO],
916 
       wsr_data_w2[`WSR_TSTATE_PS2_HI:`WSR_TSTATE_PS2_LO],
917 95 fafa1971 
       2'b0,
918 113 albert.wat 
       wsr_data_w2[`WSR_TSTATE_PS1_HI:`WSR_TSTATE_PS1_LO],
919 
       wsr_data_w2[`WSR_TSTATE_CWP_HI:`WSR_TSTATE_CWP_LO]};
920 95 fafa1971 
//
921 
// extracting the relevant data from hstate from the WSR to be written
922 113 albert.wat 
assign compose_htstate[`TSA_HTSTATE_WIDTH-1:0] =
923 
          {wsr_data_w2[`WSR_HPSTATE_IBE],
924 
       wsr_data_w2[`WSR_HPSTATE_RED],
925 
           wsr_data_w2[`WSR_HPSTATE_PRIV],
926 
           wsr_data_w2[`WSR_HPSTATE_TLZ]};
927 95 fafa1971 
 
928 
// htstate
929 113 albert.wat 
assign  wrpr_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO]=
930 
        compose_htstate[`TSA_HTSTATE_WIDTH-1:0];
931 95 fafa1971 
//
932 
// modified for bug 3017
933 
// pc
934 113 albert.wat 
assign wrpr_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO]=
935 95 fafa1971 
       {1'b0, wsr_data_w2[47:2]};
936 
// npc
937 113 albert.wat 
assign wrpr_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO]=
938 95 fafa1971 
       {1'b0, wsr_data_w2[47:2]};
939 
// tstate data
940 113 albert.wat 
assign wrpr_tsa_wdata[`TLU_GL_HI:`TLU_CWP_LO]=
941 
       compose_tstate[`WSR_TSTATE_WIDTH-1:0];
942 95 fafa1971 
// ttype data
943 113 albert.wat 
assign wrpr_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO]=
944 
       wsr_data_w2[`TSA_TTYPE_WIDTH-1:0];
945 95 fafa1971 
 
946 113 albert.wat 
mux2ds #(`TLU_TSA_WIDTH) tsawdata_sel (
947 
       .in0    ({trap_tsa_wdata[`TLU_TSA_WIDTH-1:0]}),
948 
           .in1    ({wrpr_tsa_wdata[`TLU_TSA_WIDTH-1:0]}),
949 95 fafa1971 
       .sel0   (~tlu_wr_tsa_inst_w2),
950 
       .sel1    (tlu_wr_tsa_inst_w2),
951 113 albert.wat 
       .dout   ({tsa_wdata[`TLU_TSA_WIDTH-1:0]})
952 95 fafa1971 
);
953 
 
954 
//=========================================================================================
955 
//      SOFT INTERRUPT for Threads
956 
//=========================================================================================
957 
 
958 
// Assumption is that softint state is unknown after reset.
959 
// TICK_INT will be maintained separately. What is the relative order of
960 
// setting and clearing this bit ? What takes precedence ?
961 
//
962 
// modified for bug 2204
963 
// recoded due to one-hot problem during reset
964 
 
965 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
966 
   assign sftint[`SFTINT_WIDTH-1:0] = sftint0[`SFTINT_WIDTH-1:0];
967 
`else
968 95 fafa1971 
 
969 113 albert.wat 
mux4ds #(`SFTINT_WIDTH) mx_sftint (
970 
        .in0  (sftint0[`SFTINT_WIDTH-1:0]),
971 
        .in1  (sftint1[`SFTINT_WIDTH-1:0]),
972 
        .in2  (sftint2[`SFTINT_WIDTH-1:0]),
973 
        .in3  (sftint3[`SFTINT_WIDTH-1:0]),
974 95 fafa1971 
        .sel0 (tlu_sftint_mx_sel[0]),
975 
        .sel1 (tlu_sftint_mx_sel[1]),
976 
        .sel2 (tlu_sftint_mx_sel[2]),
977 
        .sel3 (tlu_sftint_mx_sel[3]),
978 113 albert.wat 
        .dout (sftint[`SFTINT_WIDTH-1:0])
979 95 fafa1971 
);
980 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
981 95 fafa1971 
 
982 
/*
983 
assign sftint_sel_onehot_g =
984 
           ~tlu_sftint_en_l_g[0] | (&tlu_sftint_en_l_g[3:1]);
985 
 
986 
mux4ds #(`SFTINT_WIDTH) mx_sftint (
987 
        .in0  (sftint0[`SFTINT_WIDTH-1:0]),
988 
        .in1  (sftint1[`SFTINT_WIDTH-1:0]),
989 
        .in2  (sftint2[`SFTINT_WIDTH-1:0]),
990 
        .in3  (sftint3[`SFTINT_WIDTH-1:0]),
991 
        .sel0 (sftint_sel_onehot_g),
992 
        .sel1 (~tlu_sftint_en_l_g[1]),
993 
        .sel2 (~tlu_sftint_en_l_g[2]),
994 
        .sel3 (~tlu_sftint_en_l_g[3]),
995 
        .dout (sftint[`SFTINT_WIDTH-1:0])
996 
);
997 
*/
998 
 
999 113 albert.wat 
assign  sftint_set_din[`SFTINT_WIDTH-1:0] =
1000 
            (wsr_data_w[`SFTINT_WIDTH-1:0] | sftint[`SFTINT_WIDTH-1:0]);
1001 
assign  sftint_clr_din[`SFTINT_WIDTH-1:0] =
1002 
            (~wsr_data_w[`SFTINT_WIDTH-1:0] & sftint[`SFTINT_WIDTH-1:0]);
1003 
assign  sftint_wr_din[`SFTINT_WIDTH-1:0]  =
1004 
            wsr_data_w[`SFTINT_WIDTH-1:0];
1005 95 fafa1971 
 
1006 
// consturcting the mux select for the sftin_din mux
1007 
 
1008 
assign sftin_din_mxsel[0] = ~tlu_set_sftint_l_g;
1009 
assign sftin_din_mxsel[1] = ~tlu_clr_sftint_l_g;
1010 
assign sftin_din_mxsel[2] = ~tlu_wr_sftint_l_g;
1011 
assign sftin_din_mxsel[3] =
1012 
           tlu_set_sftint_l_g & tlu_clr_sftint_l_g & tlu_wr_sftint_l_g;
1013 
 
1014 113 albert.wat 
mux4ds #(`SFTINT_WIDTH) mx_sftint_din (
1015 
        .in0  (sftint_set_din[`SFTINT_WIDTH-1:0]),
1016 
        .in1  (sftint_clr_din[`SFTINT_WIDTH-1:0]),
1017 
        .in2  (sftint_wr_din[`SFTINT_WIDTH-1:0]),
1018 
        .in3  (sftint[`SFTINT_WIDTH-1:0]),
1019 95 fafa1971 
        .sel0 (sftin_din_mxsel[0]),
1020 
        .sel1 (sftin_din_mxsel[1]),
1021 
        .sel2 (sftin_din_mxsel[2]),
1022 
        .sel3 (sftin_din_mxsel[3]),
1023 113 albert.wat 
        .dout (sftint_din[`SFTINT_WIDTH-1:0])
1024 95 fafa1971 
);
1025 
 
1026 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1027 
`else
1028 
clken_buf clkbf_st0 (
1029 
                .rclk   (clk),
1030 
                .enb_l  (tlu_sftint_en_l_g[0]),
1031 
                .tmb_l  (se_l),
1032 
                .clk    (sftint0_clk)
1033 
                );
1034 
`endif
1035 95 fafa1971 
 
1036 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1037 
`else
1038 
clken_buf clkbf_st1 (
1039 
                .rclk   (clk),
1040 
                .enb_l  (tlu_sftint_en_l_g[1]),
1041 
                .tmb_l  (se_l),
1042 
                .clk    (sftint1_clk)
1043 
                );
1044 
`endif
1045 95 fafa1971 
 
1046 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1047 
`else
1048 
clken_buf clkbf_st2 (
1049 
                .rclk   (clk),
1050 
                .enb_l  (tlu_sftint_en_l_g[2]),
1051 
                .tmb_l  (se_l),
1052 
                .clk    (sftint2_clk)
1053 
                );
1054 
`endif
1055 95 fafa1971 
 
1056 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1057 
`else
1058 
clken_buf clkbf_st3 (
1059 
                .rclk   (clk),
1060 
                .enb_l  (tlu_sftint_en_l_g[3]),
1061 
                .tmb_l  (se_l),
1062 
                .clk    (sftint3_clk)
1063 
                );
1064 
`endif
1065 95 fafa1971 
//
1066 
// added for PIB support - modified to make inst count precise
1067 
assign sftint_b15_din[0] =
1068 
           (pib_picl_wrap[0] | pib_pich_wrap[0] | sftint_din[15]);
1069 
assign sftint_b15_din[1] =
1070 
           (pib_picl_wrap[1] | pib_pich_wrap[1] | sftint_din[15]);
1071 
assign sftint_b15_din[2] =
1072 
           (pib_picl_wrap[2] | pib_pich_wrap[2] | sftint_din[15]);
1073 
assign sftint_b15_din[3] =
1074 
           (pib_picl_wrap[3] | pib_pich_wrap[3] | sftint_din[15]);
1075 
 
1076 
assign sftint_b15_en[0] =
1077 
           (pib_picl_wrap[0] | pib_pich_wrap[0] | ~tlu_sftint_en_l_g[0]);
1078 
assign sftint_b15_en[1] =
1079 
           (pib_picl_wrap[1] | pib_pich_wrap[1] | ~tlu_sftint_en_l_g[1]);
1080 
assign sftint_b15_en[2] =
1081 
           (pib_picl_wrap[2] | pib_pich_wrap[2] | ~tlu_sftint_en_l_g[2]);
1082 
assign sftint_b15_en[3] =
1083 
           (pib_picl_wrap[3] | pib_pich_wrap[3] | ~tlu_sftint_en_l_g[3]);
1084 
//
1085 
// added due to sftint spec change
1086 
// tickcmp interrupts
1087 
assign sftint_b0_din[0] = (tickcmp_int[0] | sftint_din[0]);
1088 
assign sftint_b0_din[1] = (tickcmp_int[1] | sftint_din[0]);
1089 
assign sftint_b0_din[2] = (tickcmp_int[2] | sftint_din[0]);
1090 
assign sftint_b0_din[3] = (tickcmp_int[3] | sftint_din[0]);
1091 
 
1092 
assign sftint_b0_en[0] = (tickcmp_int[0] | ~tlu_sftint_en_l_g[0]);
1093 
assign sftint_b0_en[1] = (tickcmp_int[1] | ~tlu_sftint_en_l_g[1]);
1094 
assign sftint_b0_en[2] = (tickcmp_int[2] | ~tlu_sftint_en_l_g[2]);
1095 
assign sftint_b0_en[3] = (tickcmp_int[3] | ~tlu_sftint_en_l_g[3]);
1096 
//
1097 
// stickcmp interrupts
1098 
assign sftint_b16_din[0] = (stickcmp_int[0] | sftint_din[16]);
1099 
assign sftint_b16_din[1] = (stickcmp_int[1] | sftint_din[16]);
1100 
assign sftint_b16_din[2] = (stickcmp_int[2] | sftint_din[16]);
1101 
assign sftint_b16_din[3] = (stickcmp_int[3] | sftint_din[16]);
1102 
 
1103 
assign sftint_b16_en[0] = (stickcmp_int[0] | ~tlu_sftint_en_l_g[0]);
1104 
assign sftint_b16_en[1] = (stickcmp_int[1] | ~tlu_sftint_en_l_g[1]);
1105 
assign sftint_b16_en[2] = (stickcmp_int[2] | ~tlu_sftint_en_l_g[2]);
1106 
assign sftint_b16_en[3] = (stickcmp_int[3] | ~tlu_sftint_en_l_g[3]);
1107 
 
1108 
// modified for sftint spec change - special treatments for bit 0, 15 and 16
1109 
//
1110 
// thread 0
1111 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1112 
dffre_s #(14) dffr_sftint0 (
1113 95 fafa1971 
    .din (sftint_din[14:1]),
1114 
    .q   (sftint0[14:1]),
1115 
    .en (~(tlu_sftint_en_l_g[0])), .clk(clk),
1116 
    .rst (local_rst),
1117 
    .se  (se),
1118 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1119 95 fafa1971 
    .so  ()
1120 
);
1121 113 albert.wat 
`else
1122 
dffr_s #(14) dffr_sftint0 (
1123 
    .din (sftint_din[14:1]),
1124 
    .q   (sftint0[14:1]),
1125 
    .clk (sftint0_clk),
1126 
    .rst (local_rst),
1127 
    .se  (se),
1128 
    `SIMPLY_RISC_SCANIN,
1129 
    .so  ()
1130 
);
1131 
`endif
1132 
dffre_s dffre_sftint0_b0 (
1133 95 fafa1971 
    .din (sftint_b0_din[0]),
1134 113 albert.wat 
    .q   (sftint0[`SFTINT_TICK_CMP]),
1135 95 fafa1971 
    .clk (clk),
1136 
    .rst (local_rst),
1137 
    .en  (sftint_b0_en[0]),
1138 
    .se  (se),
1139 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1140 95 fafa1971 
    .so  ()
1141 
);
1142 
 
1143 113 albert.wat 
dffre_s dffre_sftint0_b15 (
1144 95 fafa1971 
    .din (sftint_b15_din[0]),
1145 113 albert.wat 
    .q   (sftint0[`SFTINT_PIB_WRAP]),
1146 95 fafa1971 
    .clk (clk),
1147 
    .rst (local_rst),
1148 
    .en  (sftint_b15_en[0]),
1149 
    .se  (se),
1150 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1151 95 fafa1971 
    .so  ()
1152 
);
1153 
 
1154 113 albert.wat 
dffre_s dffre_sftint0_b16 (
1155 95 fafa1971 
    .din (sftint_b16_din[0]),
1156 113 albert.wat 
    .q   (sftint0[`SFTINT_STICK_CMP]),
1157 95 fafa1971 
    .clk (clk),
1158 
    .rst (local_rst),
1159 
    .en  (sftint_b16_en[0]),
1160 
    .se  (se),
1161 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1162 95 fafa1971 
    .so  ()
1163 
);
1164 
//
1165 
// thread 1
1166 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1167 
dffre_s #(14) sftint1ff (
1168 95 fafa1971 
    .din (sftint_din[14:1]),
1169 
    .q   (sftint1[14:1]),
1170 
    .en (~(tlu_sftint_en_l_g[1])), .clk(clk),
1171 
    .rst (local_rst),
1172 
    .se  (se),
1173 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1174 95 fafa1971 
    .so  ()
1175 
);
1176 113 albert.wat 
`else
1177 
dffr_s #(14) sftint1ff (
1178 
    .din (sftint_din[14:1]),
1179 
    .q   (sftint1[14:1]),
1180 
    .clk (sftint1_clk),
1181 
    .rst (local_rst),
1182 
    .se  (se),
1183 
    `SIMPLY_RISC_SCANIN,
1184 
    .so  ()
1185 
);
1186 
`endif
1187 95 fafa1971 
 
1188 113 albert.wat 
dffre_s dffre_sftint1_b0 (
1189 95 fafa1971 
    .din (sftint_b0_din[1]),
1190 113 albert.wat 
    .q   (sftint1[`SFTINT_TICK_CMP]),
1191 95 fafa1971 
    .clk (clk),
1192 
    .rst (local_rst),
1193 
    .en  (sftint_b0_en[1]),
1194 
    .se  (se),
1195 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1196 95 fafa1971 
    .so  ()
1197 
);
1198 
 
1199 113 albert.wat 
dffre_s dffre_sftint1_b15 (
1200 95 fafa1971 
    .din (sftint_b15_din[1]),
1201 113 albert.wat 
    .q   (sftint1[`SFTINT_PIB_WRAP]),
1202 95 fafa1971 
    .clk (clk),
1203 
    .rst (local_rst),
1204 
    .en  (sftint_b15_en[1]),
1205 
    .se  (se),
1206 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1207 95 fafa1971 
    .so  ()
1208 
);
1209 
 
1210 113 albert.wat 
dffre_s dffre_sftint1_b16 (
1211 95 fafa1971 
    .din (sftint_b16_din[1]),
1212 113 albert.wat 
    .q   (sftint1[`SFTINT_STICK_CMP]),
1213 95 fafa1971 
    .clk (clk),
1214 
    .rst (local_rst),
1215 
    .en  (sftint_b16_en[1]),
1216 
    .se  (se),
1217 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1218 95 fafa1971 
    .so  ()
1219 
);
1220 
//
1221 
// thread 2
1222 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1223 
dffre_s #(14) sftint2ff (
1224 95 fafa1971 
    .din (sftint_din[14:1]),
1225 
    .q   (sftint2[14:1]),
1226 
    .en (~(tlu_sftint_en_l_g[2])), .clk(clk),
1227 
    .rst (local_rst),
1228 
    .se  (se),
1229 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1230 95 fafa1971 
    .so  ()
1231 
);
1232 113 albert.wat 
`else
1233 
dffr_s #(14) sftint2ff (
1234 
    .din (sftint_din[14:1]),
1235 
    .q   (sftint2[14:1]),
1236 
    .clk (sftint2_clk),
1237 
    .rst (local_rst),
1238 
    .se  (se),
1239 
    `SIMPLY_RISC_SCANIN,
1240 
    .so  ()
1241 
);
1242 
`endif
1243 95 fafa1971 
 
1244 113 albert.wat 
dffre_s dffre_sftint2_b0 (
1245 95 fafa1971 
    .din (sftint_b0_din[2]),
1246 113 albert.wat 
    .q   (sftint2[`SFTINT_TICK_CMP]),
1247 95 fafa1971 
    .clk (clk),
1248 
    .rst (local_rst),
1249 
    .en  (sftint_b0_en[2]),
1250 
    .se  (se),
1251 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1252 95 fafa1971 
    .so  ()
1253 
);
1254 
 
1255 113 albert.wat 
dffre_s dffre_sftint2_b15 (
1256 95 fafa1971 
    .din (sftint_b15_din[2]),
1257 113 albert.wat 
    .q   (sftint2[`SFTINT_PIB_WRAP]),
1258 95 fafa1971 
    .clk (clk),
1259 
    .rst (local_rst),
1260 
    .en  (sftint_b15_en[2]),
1261 
    .se  (se),
1262 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1263 95 fafa1971 
    .so  ()
1264 
);
1265 
 
1266 113 albert.wat 
dffre_s dffre_sftint2_b16 (
1267 95 fafa1971 
    .din (sftint_b16_din[2]),
1268 113 albert.wat 
    .q   (sftint2[`SFTINT_STICK_CMP]),
1269 95 fafa1971 
    .clk (clk),
1270 
    .rst (local_rst),
1271 
    .en  (sftint_b16_en[2]),
1272 
    .se  (se),
1273 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1274 95 fafa1971 
    .so  ()
1275 
);
1276 
//
1277 
// thread 3
1278 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1279 
dffre_s #(14) sftint3ff (
1280 95 fafa1971 
    .din (sftint_din[14:1]),
1281 
    .q   (sftint3[14:1]),
1282 
    .en (~(tlu_sftint_en_l_g[3])), .clk(clk),
1283 
    .rst (local_rst),
1284 
    .se  (se),
1285 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1286 95 fafa1971 
    .so  ()
1287 
);
1288 113 albert.wat 
`else
1289 
dffr_s #(14) sftint3ff (
1290 
    .din (sftint_din[14:1]),
1291 
    .q   (sftint3[14:1]),
1292 
    .clk (sftint3_clk),
1293 
    .rst (local_rst),
1294 
    .se  (se),
1295 
    `SIMPLY_RISC_SCANIN,
1296 
    .so  ()
1297 
);
1298 
`endif
1299 95 fafa1971 
 
1300 113 albert.wat 
dffre_s dffre_sftint3_b0 (
1301 95 fafa1971 
    .din (sftint_b0_din[3]),
1302 113 albert.wat 
    .q   (sftint3[`SFTINT_TICK_CMP]),
1303 95 fafa1971 
    .clk (clk),
1304 
    .rst (local_rst),
1305 
    .en  (sftint_b0_en[3]),
1306 
    .se  (se),
1307 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1308 95 fafa1971 
    .so  ()
1309 
);
1310 
 
1311 113 albert.wat 
dffre_s dffre_sftint3_b15 (
1312 95 fafa1971 
    .din (sftint_b15_din[3]),
1313 113 albert.wat 
    .q   (sftint3[`SFTINT_PIB_WRAP]),
1314 95 fafa1971 
    .clk (clk),
1315 
    .rst (local_rst),
1316 
    .en  (sftint_b15_en[3]),
1317 
    .se  (se),
1318 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1319 95 fafa1971 
    .so  ()
1320 
);
1321 
 
1322 113 albert.wat 
dffre_s dffre_sftint3_b16 (
1323 95 fafa1971 
    .din (sftint_b16_din[3]),
1324 113 albert.wat 
    .q   (sftint3[`SFTINT_STICK_CMP]),
1325 95 fafa1971 
    .clk (clk),
1326 
    .rst (local_rst),
1327 
    .en  (sftint_b16_en[3]),
1328 
    .se  (se),
1329 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1330 95 fafa1971 
    .so  ()
1331 
);
1332 
//
1333 
// Datapath priority encoder.
1334 
assign sftint_lvl14[0] =
1335 113 albert.wat 
           sftint0[`SFTINT_TICK_CMP] | sftint0[`SFTINT_STICK_CMP] |
1336 95 fafa1971 
           sftint0[14];
1337 
assign sftint_lvl14[1] =
1338 113 albert.wat 
           sftint1[`SFTINT_TICK_CMP] | sftint1[`SFTINT_STICK_CMP] |
1339 95 fafa1971 
           sftint1[14];
1340 
assign sftint_lvl14[2] =
1341 113 albert.wat 
           sftint2[`SFTINT_TICK_CMP] | sftint2[`SFTINT_STICK_CMP] |
1342 95 fafa1971 
           sftint2[14];
1343 
assign sftint_lvl14[3] =
1344 113 albert.wat 
           sftint3[`SFTINT_TICK_CMP] | sftint3[`SFTINT_STICK_CMP] |
1345 95 fafa1971 
           sftint3[14];
1346 
//
1347 
// modified to ensure one-hot mux check
1348 
 
1349 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
1350 
   assign sftint_penc_din[14:0] = ({sftint0[15],sftint_lvl14[0],sftint0[13:1]});
1351 
`else
1352 95 fafa1971 
 
1353 113 albert.wat 
mux4ds #(`SFTINT_WIDTH-2) mx_sftint_penc_din (
1354 95 fafa1971 
    .in0  ({sftint0[15],sftint_lvl14[0],sftint0[13:1]}),
1355 
    .in1  ({sftint1[15],sftint_lvl14[1],sftint1[13:1]}),
1356 
    .in2  ({sftint2[15],sftint_lvl14[2],sftint2[13:1]}),
1357 
    .in3  ({sftint3[15],sftint_lvl14[3],sftint3[13:1]}),
1358 
    .sel0 (tlu_sftint_penc_sel[0]),
1359 
    .sel1 (tlu_sftint_penc_sel[1]),
1360 
    .sel2 (tlu_sftint_penc_sel[2]),
1361 
    .sel3 (tlu_sftint_penc_sel[3]),
1362 
    .dout (sftint_penc_din[14:0])
1363 
);
1364 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
1365 95 fafa1971 
 
1366 
tlu_prencoder16 prencoder16 (
1367 
                        .din    (sftint_penc_din[14:0]),
1368 
                        .dout   (tlu_sftint_id[3:0])
1369 
                );
1370 
 
1371 
//wire  [15:0]  sftint_rdata;
1372 
//
1373 
// modified for hypervisor support
1374 
// adding the SM bit
1375 113 albert.wat 
wire [`SFTINT_WIDTH-1:0] sftint_rdata;
1376 95 fafa1971 
// modified due to spec change
1377 
/*
1378 
mux4ds #(`SFTINT_WIDTH) sftint_mx_rsel (
1379 
    .in0  ({tlu_stick_int[0],sftint0[15:1],tlu_tick_int[0]}),
1380 
    .in1  ({tlu_stick_int[1],sftint1[15:1],tlu_tick_int[1]}),
1381 
    .in2  ({tlu_stick_int[2],sftint2[15:1],tlu_tick_int[2]}),
1382 
    .in3  ({tlu_stick_int[3],sftint3[15:1],tlu_tick_int[3]}),
1383 
    .sel0 (tlu_thrd_rsel_e[0]),
1384 
    .sel1 (tlu_thrd_rsel_e[1]),
1385 
    .sel2 (tlu_thrd_rsel_e[2]),
1386 
    .sel3 (tlu_thrd_rsel_e[3]),
1387 
    .dout (sftint_rdata[16:0])
1388 
);
1389 
*/
1390 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
1391 
   assign      sftint_rdata[16:0] = sftint0[`SFTINT_WIDTH-1:0];
1392 
`else
1393 95 fafa1971 
 
1394 113 albert.wat 
mux4ds #(`SFTINT_WIDTH) sftint_mx_rsel (
1395 
    .in0  (sftint0[`SFTINT_WIDTH-1:0]),
1396 
    .in1  (sftint1[`SFTINT_WIDTH-1:0]),
1397 
    .in2  (sftint2[`SFTINT_WIDTH-1:0]),
1398 
    .in3  (sftint3[`SFTINT_WIDTH-1:0]),
1399 95 fafa1971 
    .sel0 (tlu_thrd_rsel_e[0]),
1400 
    .sel1 (tlu_thrd_rsel_e[1]),
1401 
    .sel2 (tlu_thrd_rsel_e[2]),
1402 
    .sel3 (tlu_thrd_rsel_e[3]),
1403 
    .dout (sftint_rdata[16:0])
1404 
);
1405 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
1406 95 fafa1971 
 
1407 
//=========================================================================================
1408 
//      TBA for Threads
1409 
//=========================================================================================
1410 
 
1411 
// Lower 15 bits are read as zero and ignored when written.
1412 
 
1413 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1414 
`else
1415 
clken_buf clkbf_tba0 (
1416 
                .rclk   (clk),
1417 
                .enb_l  (tlu_tba_en_l[0]),
1418 
                .tmb_l  (se_l),
1419 
                .clk    (tba0_clk)
1420 
                );
1421 
`endif
1422 95 fafa1971 
 
1423 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1424 
`else
1425 
clken_buf clkbf_tba1 (
1426 
                .rclk   (clk),
1427 
                .enb_l  (tlu_tba_en_l[1]),
1428 
                .tmb_l  (se_l),
1429 
                .clk    (tba1_clk)
1430 
                );
1431 
`endif
1432 95 fafa1971 
 
1433 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1434 
`else
1435 
clken_buf clkbf_tba2 (
1436 
                .rclk   (clk),
1437 
                .enb_l  (tlu_tba_en_l[2]),
1438 
                .tmb_l  (se_l),
1439 
                .clk    (tba2_clk)
1440 
                );
1441 
`endif
1442 95 fafa1971 
 
1443 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1444 
`else
1445 
clken_buf clkbf_tba3 (
1446 
                .rclk   (clk),
1447 
                .enb_l  (tlu_tba_en_l[3]),
1448 
                .tmb_l  (se_l),
1449 
                .clk    (tba3_clk)
1450 
                );
1451 
`endif
1452 95 fafa1971 
 
1453 
// THREAD0
1454 
 
1455 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1456 
dffe_s #(33) tba0 (
1457 95 fafa1971 
    .din (tlu_wsr_data_w[47:15]),
1458 
    .q   (true_tba0[32:0]),
1459 
    .en (~(tlu_tba_en_l[0])), .clk(clk),
1460 
    .se  (se),
1461 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1462 95 fafa1971 
    .so  ()
1463 
);
1464 113 albert.wat 
`else
1465 
dff_s #(33) tba0 (
1466 
    .din (tlu_wsr_data_w[47:15]),
1467 
    .q   (true_tba0[32:0]),
1468 
    .clk (tba0_clk),
1469 
    .se  (se),
1470 
    `SIMPLY_RISC_SCANIN,
1471 
    .so  ()
1472 
);
1473 
`endif
1474 95 fafa1971 
 
1475 
// THREAD1
1476 
 
1477 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1478 
dffe_s #(33) tba1 (
1479 95 fafa1971 
    .din (tlu_wsr_data_w[47:15]),
1480 
    .q  (true_tba1[32:0]),
1481 
    .en (~(tlu_tba_en_l[1])), .clk(clk),
1482 
    .se  (se),
1483 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1484 95 fafa1971 
    .so  ()
1485 
);
1486 113 albert.wat 
`else
1487 
dff_s #(33) tba1 (
1488 
    .din (tlu_wsr_data_w[47:15]),
1489 
    .q  (true_tba1[32:0]),
1490 
    .clk (tba1_clk),
1491 
    .se  (se),
1492 
    `SIMPLY_RISC_SCANIN,
1493 
    .so  ()
1494 
);
1495 
`endif
1496 95 fafa1971 
 
1497 
// THREAD2
1498 
 
1499 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1500 
dffe_s #(33) tba2 (
1501 95 fafa1971 
    .din (tlu_wsr_data_w[47:15]),
1502 
    .q   (true_tba2[32:0]),
1503 
    .en (~(tlu_tba_en_l[2])), .clk(clk),
1504 
    .se  (se),
1505 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1506 95 fafa1971 
    .so  ()
1507 
);
1508 113 albert.wat 
`else
1509 
dff_s #(33) tba2 (
1510 
    .din (tlu_wsr_data_w[47:15]),
1511 
    .q   (true_tba2[32:0]),
1512 
    .clk (tba2_clk),
1513 
    .se  (se),
1514 
    `SIMPLY_RISC_SCANIN,
1515 
    .so  ()
1516 
);
1517 
`endif
1518 95 fafa1971 
 
1519 
// THREAD3
1520 
 
1521 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1522 
dffe_s #(33) tba3 (
1523 95 fafa1971 
    .din (tlu_wsr_data_w[47:15]),
1524 
    .q  (true_tba3[32:0]),
1525 
    .en (~(tlu_tba_en_l[3])), .clk(clk),
1526 
    .se  (se),
1527 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1528 95 fafa1971 
    .so  ()
1529 
);
1530 113 albert.wat 
`else
1531 
dff_s #(33) tba3 (
1532 
    .din (tlu_wsr_data_w[47:15]),
1533 
    .q  (true_tba3[32:0]),
1534 
    .clk (tba3_clk),
1535 
    .se  (se),
1536 
    `SIMPLY_RISC_SCANIN,
1537 
    .so  ()
1538 
);
1539 
`endif
1540 95 fafa1971 
 
1541 
// tba_data is for traps specifically
1542 
// modified for timing
1543 
 
1544 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
1545 
   assign      tba_data[32:0] = true_tba0[32:0];
1546 
   assign      tba_rdata[32:0] = true_tba0[32:0];
1547 95 fafa1971 
 
1548 113 albert.wat 
`else
1549 
 
1550 95 fafa1971 
mux4ds #(33) mux_tba_data (
1551 
       .in0  (true_tba0[32:0]),
1552 
       .in1  (true_tba1[32:0]),
1553 
       .in2  (true_tba2[32:0]),
1554 
       .in3  (true_tba3[32:0]),
1555 
       .sel0 (tlu_thrd_wsel_w2[0]),
1556 
       .sel1 (tlu_thrd_wsel_w2[1]),
1557 
       .sel2 (tlu_thrd_wsel_w2[2]),
1558 
       .sel3 (tlu_thrd_wsel_w2[3]),
1559 
       .dout (tba_data[32:0])
1560 
);
1561 
 
1562 
/*
1563 
mux4ds #(33) tba_mx (
1564 
       .in0  (true_tba0[32:0]),
1565 
       .in1  (true_tba1[32:0]),
1566 
       .in2  (true_tba2[32:0]),
1567 
       .in3  (true_tba3[32:0]),
1568 
       .sel0 (tlu_thrd_rsel_g[0]),
1569 
       .sel1 (tlu_thrd_rsel_g[1]),
1570 
       .sel2 (tlu_thrd_rsel_g[2]),
1571 
       .sel3 (tlu_thrd_rsel_g[3]),
1572 
       .dout (tba_data[32:0])
1573 
);
1574 
*/
1575 
// tba_rdata is for read of tba regs specifically.
1576 
mux4ds #(33) tba_mx_rsel (
1577 
       .in0  (true_tba0[32:0]),
1578 
       .in1  (true_tba1[32:0]),
1579 
       .in2  (true_tba2[32:0]),
1580 
       .in3  (true_tba3[32:0]),
1581 
       .sel0 (tlu_thrd_rsel_e[0]),
1582 
       .sel1 (tlu_thrd_rsel_e[1]),
1583 
       .sel2 (tlu_thrd_rsel_e[2]),
1584 
       .sel3 (tlu_thrd_rsel_e[3]),
1585 
       .dout (tba_rdata[32:0])
1586 
);
1587 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
1588 95 fafa1971 
 
1589 
// added for hypervisor support
1590 
//
1591 
// HTBA write - constructing clocks
1592 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1593 
`else
1594 
clken_buf clkbf_htba0 (
1595 
    .rclk  (clk),
1596 
        .enb_l (tlu_htba_en_l[0]),
1597 
        .tmb_l (se_l),
1598 
        .clk   (htba0_clk)
1599 
);
1600 
`endif
1601 95 fafa1971 
 
1602 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1603 
`else
1604 
clken_buf clkbf_htba1 (
1605 
    .rclk  (clk),
1606 
        .enb_l (tlu_htba_en_l[1]),
1607 
        .tmb_l (se_l),
1608 
        .clk   (htba1_clk)
1609 
);
1610 
`endif
1611 95 fafa1971 
 
1612 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1613 
`else
1614 
clken_buf clkbf_htba2 (
1615 
    .rclk  (clk),
1616 
        .enb_l (tlu_htba_en_l[2]),
1617 
        .tmb_l (se_l),
1618 
        .clk   (htba2_clk)
1619 
);
1620 
`endif
1621 95 fafa1971 
 
1622 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1623 
`else
1624 
clken_buf clkbf_htba3 (
1625 
    .rclk  (clk),
1626 
        .enb_l (tlu_htba_en_l[3]),
1627 
        .tmb_l (se_l),
1628 
        .clk   (htba3_clk)
1629 
);
1630 
`endif
1631 95 fafa1971 
//
1632 
// HTBA write - writing the registers
1633 
// lower 14 bits of HTBA are reserved, therefore, not stored
1634 
//
1635 
// Thread 0
1636 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1637 
dffe_s #(`TLU_HTBA_WIDTH) dff_true_htba0 (
1638 
    .din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
1639 
    .q   (true_htba0[`TLU_HTBA_WIDTH-1:0]),
1640 95 fafa1971 
    .en (~(tlu_htba_en_l[0])), .clk(clk),
1641 
    .se  (se),
1642 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1643 95 fafa1971 
    .so  ()
1644 
);
1645 113 albert.wat 
`else
1646 
dff_s #(`TLU_HTBA_WIDTH) dff_true_htba0 (
1647 
    .din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
1648 
    .q   (true_htba0[`TLU_HTBA_WIDTH-1:0]),
1649 
    .clk (htba0_clk),
1650 
    .se  (se),
1651 
    `SIMPLY_RISC_SCANIN,
1652 
    .so  ()
1653 
);
1654 
`endif
1655 95 fafa1971 
//
1656 
// Thread 1
1657 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1658 
dffe_s #(`TLU_HTBA_WIDTH) dff_true_htba1 (
1659 
    .din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
1660 
    .q   (true_htba1[`TLU_HTBA_WIDTH-1:0]),
1661 95 fafa1971 
    .en (~(tlu_htba_en_l[1])), .clk(clk),
1662 
    .se  (se),
1663 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1664 95 fafa1971 
    .so  ()
1665 
);
1666 113 albert.wat 
`else
1667 
dff_s #(`TLU_HTBA_WIDTH) dff_true_htba1 (
1668 
    .din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
1669 
    .q   (true_htba1[`TLU_HTBA_WIDTH-1:0]),
1670 
    .clk (htba1_clk),
1671 
    .se  (se),
1672 
    `SIMPLY_RISC_SCANIN,
1673 
    .so  ()
1674 
);
1675 
`endif
1676 95 fafa1971 
//
1677 
// Thread 2
1678 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1679 
dffe_s #(`TLU_HTBA_WIDTH) dff_true_htba2 (
1680 
    .din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
1681 
    .q   (true_htba2[`TLU_HTBA_WIDTH-1:0]),
1682 95 fafa1971 
    .en (~(tlu_htba_en_l[2])), .clk(clk),
1683 
    .se  (se),
1684 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1685 95 fafa1971 
    .so  ()
1686 
);
1687 113 albert.wat 
`else
1688 
dff_s #(`TLU_HTBA_WIDTH) dff_true_htba2 (
1689 
    .din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
1690 
    .q   (true_htba2[`TLU_HTBA_WIDTH-1:0]),
1691 
    .clk (htba2_clk),
1692 
    .se  (se),
1693 
    `SIMPLY_RISC_SCANIN,
1694 
    .so  ()
1695 
);
1696 
`endif
1697 95 fafa1971 
//
1698 
// Thread 3
1699 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1700 
dffe_s #(`TLU_HTBA_WIDTH) dff_true_htba3 (
1701 
    .din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
1702 
    .q   (true_htba3[`TLU_HTBA_WIDTH-1:0]),
1703 95 fafa1971 
    .en (~(tlu_htba_en_l[3])), .clk(clk),
1704 
    .se  (se),
1705 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1706 95 fafa1971 
    .so  ()
1707 
);
1708 113 albert.wat 
`else
1709 
dff_s #(`TLU_HTBA_WIDTH) dff_true_htba3 (
1710 
    .din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
1711 
    .q   (true_htba3[`TLU_HTBA_WIDTH-1:0]),
1712 
    .clk (htba3_clk),
1713 
    .se  (se),
1714 
    `SIMPLY_RISC_SCANIN,
1715 
    .so  ()
1716 
);
1717 
`endif
1718 95 fafa1971 
//
1719 
// constructing the rdata for HTBA
1720 113 albert.wat 
wire [`TLU_HTBA_WIDTH-1:0] htba_rdata;
1721 95 fafa1971 
 
1722 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
1723 
   assign                  htba_rdata[`TLU_HTBA_WIDTH-1:0] = true_htba0[`TLU_HTBA_WIDTH-1:0];
1724 
   assign                  htba_data[`TLU_HTBA_WIDTH-1:0] = true_htba0[`TLU_HTBA_WIDTH-1:0];
1725 
`else
1726 95 fafa1971 
 
1727 113 albert.wat 
mux4ds #(`TLU_HTBA_WIDTH) mux_htba_rdata (
1728 
       .in0  (true_htba0[`TLU_HTBA_WIDTH-1:0]),
1729 
       .in1  (true_htba1[`TLU_HTBA_WIDTH-1:0]),
1730 
       .in2  (true_htba2[`TLU_HTBA_WIDTH-1:0]),
1731 
       .in3  (true_htba3[`TLU_HTBA_WIDTH-1:0]),
1732 95 fafa1971 
       .sel0 (tlu_thrd_rsel_e[0]),
1733 
       .sel1 (tlu_thrd_rsel_e[1]),
1734 
       .sel2 (tlu_thrd_rsel_e[2]),
1735 
       .sel3 (tlu_thrd_rsel_e[3]),
1736 113 albert.wat 
       .dout (htba_rdata[`TLU_HTBA_WIDTH-1:0])
1737 95 fafa1971 
);
1738 
//
1739 
// selecting the htba base address to use
1740 
// modified for timing
1741 113 albert.wat 
mux4ds #(`TLU_HTBA_WIDTH) mux_htba_data (
1742 
       .in0  (true_htba0[`TLU_HTBA_WIDTH-1:0]),
1743 
       .in1  (true_htba1[`TLU_HTBA_WIDTH-1:0]),
1744 
       .in2  (true_htba2[`TLU_HTBA_WIDTH-1:0]),
1745 
       .in3  (true_htba3[`TLU_HTBA_WIDTH-1:0]),
1746 95 fafa1971 
       .sel0 (tlu_thrd_wsel_w2[0]),
1747 
       .sel1 (tlu_thrd_wsel_w2[1]),
1748 
       .sel2 (tlu_thrd_wsel_w2[2]),
1749 
       .sel3 (tlu_thrd_wsel_w2[3]),
1750 113 albert.wat 
       .dout (htba_data[`TLU_HTBA_WIDTH-1:0])
1751 95 fafa1971 
);
1752 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
1753 95 fafa1971 
 
1754 
/*
1755 
mux4ds #(`TLU_HTBA_WIDTH) mux_htba_data (
1756 
       .in0  (true_htba0[`TLU_HTBA_WIDTH-1:0]),
1757 
       .in1  (true_htba1[`TLU_HTBA_WIDTH-1:0]),
1758 
       .in2  (true_htba2[`TLU_HTBA_WIDTH-1:0]),
1759 
       .in3  (true_htba3[`TLU_HTBA_WIDTH-1:0]),
1760 
       .sel0 (tlu_thrd_rsel_g[0]),
1761 
       .sel1 (tlu_thrd_rsel_g[1]),
1762 
       .sel2 (tlu_thrd_rsel_g[2]),
1763 
       .sel3 (tlu_thrd_rsel_g[3]),
1764 
       .dout (htba_data[`TLU_HTBA_WIDTH-1:0])
1765 
);
1766 
*/
1767 
//=========================================================================================
1768 
//      TICKS for Threads
1769 
//=========================================================================================
1770 
 
1771 
// npt needs to be muxed into read !!!
1772 
 
1773 
 
1774 
// THREAD0,1,2,3
1775 
 
1776 
mux2ds #(61) tick_sel (
1777 
       .in0  (tlu_wsr_data_w[62:2]),
1778 
           .in1  (tlu_tick_incr_dout[60:0]),
1779 
       .sel0 (~tlu_tick_en_l),
1780 
           .sel1 ( tlu_tick_en_l),
1781 
       .dout (tick_din[62:2])
1782 
);
1783 
//
1784 
// modified due to the switch to the soft macro
1785 
// assign       tlu_tick_incr_din[`TLU_ASR_DATA_WIDTH-1:0] =
1786 
//         {3'b000,true_tick[60:0]};
1787 113 albert.wat 
assign  tlu_tick_incr_din[`TLU_ASR_DATA_WIDTH-3:0] =
1788 95 fafa1971 
         {1'b0,true_tick[60:0]};
1789 
 
1790 
// Does not need enable as either in increment or update state
1791 113 albert.wat 
dff_s #(61) tick0123 (
1792 95 fafa1971 
    .din (tick_din[62:2]),
1793 
    .q  (true_tick[60:0]),
1794 
    .clk (clk),
1795 
    .se  (se),
1796 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1797 95 fafa1971 
    .so ()
1798 
);
1799 
 
1800 
//=========================================================================================
1801 
//      TICK COMPARE  for Threads
1802 
//=========================================================================================
1803 
 
1804 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1805 
`else
1806 
clken_buf clkbf_tcmp0 (
1807 
    .rclk  (clk),
1808 
        .enb_l (tlu_tickcmp_en_l[0]),
1809 
        .tmb_l (se_l),
1810 
        .clk   (tcmp0_clk)
1811 
);
1812 
`endif
1813 95 fafa1971 
 
1814 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1815 
`else
1816 
clken_buf clkbf_tcmp1 (
1817 
    .rclk  (clk),
1818 
        .enb_l (tlu_tickcmp_en_l[1]),
1819 
        .tmb_l (se_l),
1820 
        .clk   (tcmp1_clk)
1821 
);
1822 
`endif
1823 95 fafa1971 
 
1824 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1825 
`else
1826 
clken_buf clkbf_tcmp2 (
1827 
    .rclk  (clk),
1828 
        .enb_l (tlu_tickcmp_en_l[2]),
1829 
        .tmb_l (se_l),
1830 
        .clk   (tcmp2_clk)
1831 
);
1832 
`endif
1833 95 fafa1971 
 
1834 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1835 
`else
1836 
clken_buf clkbf_tcmp3 (
1837 
    .rclk  (clk),
1838 
        .enb_l (tlu_tickcmp_en_l[3]),
1839 
        .tmb_l (se_l),
1840 
        .clk   (tcmp3_clk)
1841 
);
1842 
`endif
1843 95 fafa1971 
 
1844 
// thread 0
1845 
// added or modified due to tickcmp clean-up
1846 
assign tickcmp_intdis_din[0] =
1847 113 albert.wat 
           tlu_wsr_data_w[`TICKCMP_INTDIS] | local_rst |
1848 95 fafa1971 
           tlu_por_rstint_g[0];
1849 
// added and modified for bug 4763
1850 
assign tickcmp_intdis_en[0] =
1851 
           ~tlu_tickcmp_en_l[0] | local_rst | tlu_por_rstint_g[0];
1852 
 
1853 113 albert.wat 
dffe_s dffe_tickcmp_intdis0 (
1854 95 fafa1971 
    .din (tickcmp_intdis_din[0]),
1855 113 albert.wat 
        .q   (true_tickcmp0[`TICKCMP_INTDIS]),
1856 95 fafa1971 
    .en  (tickcmp_intdis_en[0]),
1857 
    .clk (clk),
1858 
    .se  (se),
1859 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1860 95 fafa1971 
    .so  ()
1861 
);
1862 
 
1863 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1864 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp0 (
1865 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
1866 
        .q   (true_tickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
1867 95 fafa1971 
    .en (~(tlu_tickcmp_en_l[0])), .clk(clk),
1868 
    .se  (se),
1869 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1870 95 fafa1971 
    .so  ()
1871 
);
1872 113 albert.wat 
`else
1873 
dff_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp0 (
1874 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
1875 
        .q   (true_tickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
1876 
    .clk (tcmp0_clk),
1877 
    .se  (se),
1878 
    `SIMPLY_RISC_SCANIN,
1879 
    .so  ()
1880 
);
1881 
`endif
1882 95 fafa1971 
 
1883 
// thread 1
1884 
// added or modified due to tickcmp clean-up
1885 
assign tickcmp_intdis_din[1] =
1886 113 albert.wat 
           tlu_wsr_data_w[`TICKCMP_INTDIS] | local_rst |
1887 95 fafa1971 
           tlu_por_rstint_g[1];
1888 
// added and modified for bug 4763
1889 
assign tickcmp_intdis_en[1] =
1890 
           ~tlu_tickcmp_en_l[1] | local_rst | tlu_por_rstint_g[1];
1891 
 
1892 113 albert.wat 
dffe_s dffe_tickcmp_intdis1 (
1893 95 fafa1971 
    .din (tickcmp_intdis_din[1]),
1894 113 albert.wat 
        .q   (true_tickcmp1[`TICKCMP_INTDIS]),
1895 95 fafa1971 
    .en  (tickcmp_intdis_en[1]),
1896 
    .clk (clk),
1897 
    .se  (se),
1898 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1899 95 fafa1971 
    .so  ()
1900 
);
1901 
 
1902 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1903 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp1 (
1904 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
1905 
        .q   (true_tickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
1906 95 fafa1971 
    .en (~(tlu_tickcmp_en_l[1])), .clk(clk),
1907 
    .se  (se),
1908 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1909 95 fafa1971 
    .so  ()
1910 
);
1911 113 albert.wat 
`else
1912 
dff_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp1 (
1913 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
1914 
        .q   (true_tickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
1915 
    .clk (tcmp1_clk),
1916 
    .se  (se),
1917 
    `SIMPLY_RISC_SCANIN,
1918 
    .so  ()
1919 
);
1920 
`endif
1921 95 fafa1971 
 
1922 
// thread 2
1923 
// added or modified due to tickcmp clean-up
1924 
assign tickcmp_intdis_din[2] =
1925 113 albert.wat 
           tlu_wsr_data_w[`TICKCMP_INTDIS] | local_rst |
1926 95 fafa1971 
           tlu_por_rstint_g[2];
1927 
// added and modified for bug 4763
1928 
assign tickcmp_intdis_en[2] =
1929 
           ~tlu_tickcmp_en_l[2] | local_rst | tlu_por_rstint_g[2];
1930 
 
1931 113 albert.wat 
dffe_s dffe_tickcmp_intdis2 (
1932 95 fafa1971 
    .din (tickcmp_intdis_din[2]),
1933 113 albert.wat 
        .q   (true_tickcmp2[`TICKCMP_INTDIS]),
1934 95 fafa1971 
    .en  (tickcmp_intdis_en[2]),
1935 
    .clk (clk),
1936 
    .se  (se),
1937 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1938 95 fafa1971 
    .so  ()
1939 
);
1940 
 
1941 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1942 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp2 (
1943 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
1944 
        .q   (true_tickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
1945 95 fafa1971 
    .en (~(tlu_tickcmp_en_l[2])), .clk(clk),
1946 
    .se  (se),
1947 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1948 95 fafa1971 
    .so  ()
1949 
);
1950 113 albert.wat 
`else
1951 
dff_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp2 (
1952 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
1953 
        .q   (true_tickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
1954 
    .clk (tcmp2_clk),
1955 
    .se  (se),
1956 
    `SIMPLY_RISC_SCANIN,
1957 
    .so  ()
1958 
);
1959 
`endif
1960 95 fafa1971 
 
1961 
// thread 3
1962 
// added or modified due to tickcmp clean-up
1963 
assign tickcmp_intdis_din[3] =
1964 113 albert.wat 
           tlu_wsr_data_w[`TICKCMP_INTDIS] | local_rst |
1965 95 fafa1971 
           tlu_por_rstint_g[3];
1966 
// added and modified for bug 4763
1967 
assign tickcmp_intdis_en[3] =
1968 
           ~tlu_tickcmp_en_l[3] | local_rst | tlu_por_rstint_g[3];
1969 
 
1970 113 albert.wat 
dffe_s dffe_tickcmp_intdis3 (
1971 95 fafa1971 
    .din (tickcmp_intdis_din[3]),
1972 113 albert.wat 
        .q   (true_tickcmp3[`TICKCMP_INTDIS]),
1973 95 fafa1971 
    .en  (tickcmp_intdis_en[3]),
1974 
    .clk (clk),
1975 
    .se  (se),
1976 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1977 95 fafa1971 
    .so  ()
1978 
);
1979 
 
1980 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1981 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp3 (
1982 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
1983 
        .q   (true_tickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
1984 95 fafa1971 
    .en (~(tlu_tickcmp_en_l[3])), .clk(clk),
1985 
    .se  (se),
1986 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
1987 95 fafa1971 
    .so  ()
1988 
);
1989 113 albert.wat 
`else
1990 
dff_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp3 (
1991 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
1992 
        .q   (true_tickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
1993 
    .clk (tcmp3_clk),
1994 
    .se  (se),
1995 
    `SIMPLY_RISC_SCANIN,
1996 
    .so  ()
1997 
);
1998 
`endif
1999 95 fafa1971 
 
2000 
// Select 1/4 sources. Assume compare is independent of read
2001 
// and thus needs separate mux
2002 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
2003 
   assign tickcmp_data[`TLU_ASR_DATA_WIDTH-4:0] = true_tickcmp0[`TLU_ASR_DATA_WIDTH-2:2];
2004 
   assign tickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0] = true_tickcmp0[`TLU_ASR_DATA_WIDTH-1:0];
2005 
`else
2006 95 fafa1971 
 
2007 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH-3) tcmp_mx_sel (
2008 
       .in0  (true_tickcmp0[`TLU_ASR_DATA_WIDTH-2:2]),
2009 
       .in1  (true_tickcmp1[`TLU_ASR_DATA_WIDTH-2:2]),
2010 
       .in2  (true_tickcmp2[`TLU_ASR_DATA_WIDTH-2:2]),
2011 
       .in3  (true_tickcmp3[`TLU_ASR_DATA_WIDTH-2:2]),
2012 95 fafa1971 
       .sel0 (tlu_tickcmp_sel[0]),
2013 
       .sel1 (tlu_tickcmp_sel[1]),
2014 
       .sel2 (tlu_tickcmp_sel[2]),
2015 
       .sel3 (tlu_tickcmp_sel[3]),
2016 113 albert.wat 
       .dout (tickcmp_data[`TLU_ASR_DATA_WIDTH-4:0])
2017 95 fafa1971 
);
2018 
 
2019 
// mux for read
2020 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH) tcmp_mx_rsel (
2021 
       .in0  (true_tickcmp0[`TLU_ASR_DATA_WIDTH-1:0]),
2022 
       .in1  (true_tickcmp1[`TLU_ASR_DATA_WIDTH-1:0]),
2023 
       .in2  (true_tickcmp2[`TLU_ASR_DATA_WIDTH-1:0]),
2024 
       .in3  (true_tickcmp3[`TLU_ASR_DATA_WIDTH-1:0]),
2025 95 fafa1971 
       .sel0 (tlu_thrd_rsel_e[0]),
2026 
       .sel1 (tlu_thrd_rsel_e[1]),
2027 
       .sel2 (tlu_thrd_rsel_e[2]),
2028 
       .sel3 (tlu_thrd_rsel_e[3]),
2029 113 albert.wat 
       .dout (tickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0])
2030 95 fafa1971 
);
2031 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
2032 95 fafa1971 
 
2033 
//
2034 
// evaluate for tickcmp match
2035 
assign tick_match =
2036 113 albert.wat 
           (tickcmp_data[`TICKCMP_RANGE_HI:`TICKCMP_RANGE_LO] ==
2037 95 fafa1971 
            true_tick[60:0]);
2038 
//
2039 
// moved from tlu_tcl
2040 
assign  tickcmp_int[0] =
2041 113 albert.wat 
            tick_match & ~true_tickcmp0[`TICKCMP_INTDIS] & tlu_tickcmp_sel[0];
2042 95 fafa1971 
assign  tickcmp_int[1] =
2043 113 albert.wat 
            tick_match & ~true_tickcmp1[`TICKCMP_INTDIS] & tlu_tickcmp_sel[1];
2044 95 fafa1971 
assign  tickcmp_int[2] =
2045 113 albert.wat 
            tick_match & ~true_tickcmp2[`TICKCMP_INTDIS] & tlu_tickcmp_sel[2];
2046 95 fafa1971 
assign  tickcmp_int[3] =
2047 113 albert.wat 
            tick_match & ~true_tickcmp3[`TICKCMP_INTDIS] & tlu_tickcmp_sel[3];
2048 95 fafa1971 
 
2049 
//=========================================================================================
2050 
//      STICK COMPARE  for Threads
2051 
//=========================================================================================
2052 
// added for hypervisor support
2053 
 
2054 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2055 
`else
2056 
clken_buf clkbf_stcmp0 (
2057 
    .rclk  (clk),
2058 
        .enb_l (tlu_stickcmp_en_l[0]),
2059 
        .tmb_l (se_l),
2060 
        .clk   (stcmp0_clk)
2061 
);
2062 
`endif
2063 95 fafa1971 
 
2064 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2065 
`else
2066 
clken_buf clkbf_stcmp1 (
2067 
    .rclk  (clk),
2068 
        .enb_l (tlu_stickcmp_en_l[1]),
2069 
        .tmb_l (se_l),
2070 
        .clk   (stcmp1_clk)
2071 
);
2072 
`endif
2073 95 fafa1971 
 
2074 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2075 
`else
2076 
clken_buf clkbf_stcmp2 (
2077 
    .rclk  (clk),
2078 
        .enb_l (tlu_stickcmp_en_l[2]),
2079 
        .tmb_l (se_l),
2080 
        .clk   (stcmp2_clk)
2081 
);
2082 
`endif
2083 95 fafa1971 
 
2084 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2085 
`else
2086 
clken_buf clkbf_stcmp3 (
2087 
    .rclk  (clk),
2088 
        .enb_l (tlu_stickcmp_en_l[3]),
2089 
        .tmb_l (se_l),
2090 
        .clk   (stcmp3_clk)
2091 
);
2092 
`endif
2093 95 fafa1971 
 
2094 
// thread 0
2095 
// added or modified due to stickcmp clean-up
2096 
assign stickcmp_intdis_din[0] = tickcmp_intdis_din[0];
2097 
// added and modified for bug 4763
2098 
assign stickcmp_intdis_en[0] =
2099 
           ~tlu_stickcmp_en_l[0] | local_rst | tlu_por_rstint_g[0];
2100 
 
2101 113 albert.wat 
dffe_s dffe_stickcmp_intdis0 (
2102 95 fafa1971 
    .din (stickcmp_intdis_din[0]),
2103 113 albert.wat 
        .q   (true_stickcmp0[`TICKCMP_INTDIS]),
2104 95 fafa1971 
    .en  (stickcmp_intdis_en[0]),
2105 
    .clk (clk),
2106 
    .se  (se),
2107 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2108 95 fafa1971 
    .so  ()
2109 
);
2110 
 
2111 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2112 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp0 (
2113 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2114 
        .q   (true_stickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
2115 95 fafa1971 
    .en (~(tlu_stickcmp_en_l[0])), .clk(clk),
2116 
    .se  (se),
2117 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2118 95 fafa1971 
    .so  ()
2119 
);
2120 113 albert.wat 
`else
2121 
dff_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp0 (
2122 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2123 
        .q   (true_stickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
2124 
    .clk (stcmp0_clk),
2125 
    .se  (se),
2126 
    `SIMPLY_RISC_SCANIN,
2127 
    .so  ()
2128 
);
2129 
`endif
2130 95 fafa1971 
 
2131 
// thread 1
2132 
// added or modified due to stickcmp clean-up
2133 
assign stickcmp_intdis_din[1] = tickcmp_intdis_din[1];
2134 
// added and modified for bug 4763
2135 
assign stickcmp_intdis_en[1] =
2136 
           ~tlu_stickcmp_en_l[1] | local_rst | tlu_por_rstint_g[1];
2137 
 
2138 113 albert.wat 
dffe_s dffe_stickcmp_intdis1 (
2139 95 fafa1971 
    .din (stickcmp_intdis_din[1]),
2140 113 albert.wat 
        .q   (true_stickcmp1[`TICKCMP_INTDIS]),
2141 95 fafa1971 
    .en  (stickcmp_intdis_en[1]),
2142 
    .clk (clk),
2143 
    .se  (se),
2144 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2145 95 fafa1971 
    .so  ()
2146 
);
2147 
 
2148 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2149 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp1 (
2150 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2151 
        .q   (true_stickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
2152 95 fafa1971 
    .en (~(tlu_stickcmp_en_l[1])), .clk(clk),
2153 
    .se  (se),
2154 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2155 95 fafa1971 
    .so  ()
2156 
);
2157 113 albert.wat 
`else
2158 
dff_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp1 (
2159 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2160 
        .q   (true_stickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
2161 
    .clk (stcmp1_clk),
2162 
    .se  (se),
2163 
    `SIMPLY_RISC_SCANIN,
2164 
    .so  ()
2165 
);
2166 
`endif
2167 95 fafa1971 
 
2168 
// thread 2
2169 
// added or modified due to stickcmp clean-up
2170 
assign stickcmp_intdis_din[2] = tickcmp_intdis_din[2];
2171 
// added for bug 4763
2172 
assign stickcmp_intdis_en[2] =
2173 
           ~tlu_stickcmp_en_l[2] | local_rst | tlu_por_rstint_g[2];
2174 
 
2175 113 albert.wat 
dffe_s dffe_stickcmp_intdis2 (
2176 95 fafa1971 
    .din (stickcmp_intdis_din[2]),
2177 113 albert.wat 
        .q   (true_stickcmp2[`TICKCMP_INTDIS]),
2178 95 fafa1971 
    .en  (stickcmp_intdis_en[2]),
2179 
    .clk (clk),
2180 
    .se  (se),
2181 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2182 95 fafa1971 
    .so  ()
2183 
);
2184 
 
2185 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2186 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp2 (
2187 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2188 
        .q   (true_stickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
2189 95 fafa1971 
    .en (~(tlu_stickcmp_en_l[2])), .clk(clk),
2190 
    .se  (se),
2191 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2192 95 fafa1971 
    .so  ()
2193 
);
2194 113 albert.wat 
`else
2195 
dff_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp2 (
2196 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2197 
        .q   (true_stickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
2198 
    .clk (stcmp2_clk),
2199 
    .se  (se),
2200 
    `SIMPLY_RISC_SCANIN,
2201 
    .so  ()
2202 
);
2203 
`endif
2204 95 fafa1971 
 
2205 
// thread 3
2206 
// added or modified due to stickcmp clean-up
2207 
assign stickcmp_intdis_din[3] = tickcmp_intdis_din[3];
2208 
// added and modified for bug 4763
2209 
assign stickcmp_intdis_en[3] =
2210 
           ~tlu_stickcmp_en_l[3] | local_rst | tlu_por_rstint_g[3];
2211 
 
2212 113 albert.wat 
dffe_s dffe_stickcmp_intdis3 (
2213 95 fafa1971 
    .din (stickcmp_intdis_din[3]),
2214 113 albert.wat 
        .q   (true_stickcmp3[`TICKCMP_INTDIS]),
2215 95 fafa1971 
    .en  (stickcmp_intdis_en[3]),
2216 
    .clk (clk),
2217 
    .se  (se),
2218 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2219 95 fafa1971 
    .so  ()
2220 
);
2221 
 
2222 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2223 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp3 (
2224 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2225 
        .q   (true_stickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
2226 95 fafa1971 
    .en (~(tlu_stickcmp_en_l[3])), .clk(clk),
2227 
    .se  (se),
2228 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2229 95 fafa1971 
    .so  ()
2230 
);
2231 113 albert.wat 
`else
2232 
dff_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp3 (
2233 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2234 
        .q   (true_stickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
2235 
    .clk (stcmp3_clk),
2236 
    .se  (se),
2237 
    `SIMPLY_RISC_SCANIN,
2238 
    .so  ()
2239 
);
2240 
`endif // !`ifdef FPGA_SYN_CLK_DFF
2241 95 fafa1971 
 
2242 
// Select 1/4 sources. Assume compare is independent of read
2243 
// and thus needs separate mux
2244 
 
2245 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
2246 
   assign stickcmp_data[`TLU_ASR_DATA_WIDTH-4:0] = true_stickcmp0[`TLU_ASR_DATA_WIDTH-2:2];
2247 
   assign stickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0] = true_stickcmp0[`TLU_ASR_DATA_WIDTH-1:0];
2248 
`else
2249 95 fafa1971 
 
2250 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH-3) mux_stickcmp_data (
2251 
       .in0  (true_stickcmp0[`TLU_ASR_DATA_WIDTH-2:2]),
2252 
       .in1  (true_stickcmp1[`TLU_ASR_DATA_WIDTH-2:2]),
2253 
       .in2  (true_stickcmp2[`TLU_ASR_DATA_WIDTH-2:2]),
2254 
       .in3  (true_stickcmp3[`TLU_ASR_DATA_WIDTH-2:2]),
2255 95 fafa1971 
       .sel0 (tlu_tickcmp_sel[0]),
2256 
       .sel1 (tlu_tickcmp_sel[1]),
2257 
       .sel2 (tlu_tickcmp_sel[2]),
2258 
       .sel3 (tlu_tickcmp_sel[3]),
2259 113 albert.wat 
       .dout (stickcmp_data[`TLU_ASR_DATA_WIDTH-4:0])
2260 95 fafa1971 
);
2261 
//
2262 
// mux for read
2263 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH) mux_stickcmp_rdata (
2264 
       .in0  (true_stickcmp0[`TLU_ASR_DATA_WIDTH-1:0]),
2265 
       .in1  (true_stickcmp1[`TLU_ASR_DATA_WIDTH-1:0]),
2266 
       .in2  (true_stickcmp2[`TLU_ASR_DATA_WIDTH-1:0]),
2267 
       .in3  (true_stickcmp3[`TLU_ASR_DATA_WIDTH-1:0]),
2268 95 fafa1971 
       .sel0 (tlu_thrd_rsel_e[0]),
2269 
       .sel1 (tlu_thrd_rsel_e[1]),
2270 
       .sel2 (tlu_thrd_rsel_e[2]),
2271 
       .sel3 (tlu_thrd_rsel_e[3]),
2272 113 albert.wat 
       .dout (stickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0])
2273 95 fafa1971 
);
2274 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
2275 95 fafa1971 
 
2276 
//
2277 
// evaluate for stickcmp match
2278 
assign stick_match =
2279 113 albert.wat 
           (stickcmp_data[`TICKCMP_RANGE_HI:`TICKCMP_RANGE_LO] ==
2280 95 fafa1971 
            true_tick[60:0]);
2281 
//
2282 
// moved from tlu_tcl
2283 
assign  stickcmp_int[0] =
2284 113 albert.wat 
            stick_match & ~true_stickcmp0[`TICKCMP_INTDIS] & tlu_tickcmp_sel[0];
2285 95 fafa1971 
assign  stickcmp_int[1] =
2286 113 albert.wat 
            stick_match & ~true_stickcmp1[`TICKCMP_INTDIS] & tlu_tickcmp_sel[1];
2287 95 fafa1971 
assign  stickcmp_int[2] =
2288 113 albert.wat 
            stick_match & ~true_stickcmp2[`TICKCMP_INTDIS] & tlu_tickcmp_sel[2];
2289 95 fafa1971 
assign  stickcmp_int[3] =
2290 113 albert.wat 
            stick_match & ~true_stickcmp3[`TICKCMP_INTDIS] & tlu_tickcmp_sel[3];
2291 95 fafa1971 
 
2292 
//=========================================================================================
2293 
//      HTICK COMPARE  for Threads
2294 
//=========================================================================================
2295 
// added for hypervisor support
2296 
 
2297 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2298 
`else
2299 
clken_buf clkbf_htcmp0 (
2300 
    .rclk  (clk),
2301 
        .enb_l (tlu_htickcmp_en_l[0]),
2302 
        .tmb_l (se_l),
2303 
        .clk   (htcmp0_clk)
2304 
);
2305 
`endif
2306 95 fafa1971 
 
2307 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2308 
`else
2309 
clken_buf clkbf_htcmp1 (
2310 
    .rclk  (clk),
2311 
        .enb_l (tlu_htickcmp_en_l[1]),
2312 
        .tmb_l (se_l),
2313 
        .clk   (htcmp1_clk)
2314 
);
2315 
`endif
2316 95 fafa1971 
 
2317 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2318 
`else
2319 
clken_buf clkbf_htcmp2 (
2320 
    .rclk  (clk),
2321 
        .enb_l (tlu_htickcmp_en_l[2]),
2322 
        .tmb_l (se_l),
2323 
        .clk   (htcmp2_clk)
2324 
);
2325 
`endif
2326 95 fafa1971 
 
2327 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2328 
`else
2329 
clken_buf clkbf_htcmp3 (
2330 
    .rclk  (clk),
2331 
        .enb_l (tlu_htickcmp_en_l[3]),
2332 
        .tmb_l (se_l),
2333 
        .clk   (htcmp3_clk)
2334 
);
2335 
`endif
2336 95 fafa1971 
 
2337 
// THREAD0
2338 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2339 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp0 (
2340 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2341 
        .q   (true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
2342 95 fafa1971 
    .en (~(tlu_htickcmp_en_l[0])), .clk(clk),
2343 
    .se  (se),
2344 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2345 95 fafa1971 
    .so  ()
2346 
);
2347 113 albert.wat 
`else
2348 
dff_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp0 (
2349 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2350 
        .q   (true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
2351 
    .clk (htcmp0_clk),
2352 
    .se  (se),
2353 
    `SIMPLY_RISC_SCANIN,
2354 
    .so  ()
2355 
);
2356 
`endif
2357 95 fafa1971 
 
2358 
// THREAD1
2359 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2360 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp1 (
2361 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2362 
        .q   (true_htickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
2363 95 fafa1971 
    .en (~(tlu_htickcmp_en_l[1])), .clk(clk),
2364 
    .se  (se),
2365 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2366 95 fafa1971 
    .so  ()
2367 
);
2368 113 albert.wat 
`else
2369 
dff_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp1 (
2370 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2371 
        .q   (true_htickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
2372 
    .clk (htcmp1_clk),
2373 
    .se  (se),
2374 
    `SIMPLY_RISC_SCANIN,
2375 
    .so  ()
2376 
);
2377 
`endif
2378 95 fafa1971 
 
2379 
// THREAD2
2380 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2381 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp2 (
2382 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2383 
        .q   (true_htickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
2384 95 fafa1971 
    .en (~(tlu_htickcmp_en_l[2])), .clk(clk),
2385 
    .se  (se),
2386 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2387 95 fafa1971 
    .so  ()
2388 
);
2389 113 albert.wat 
`else
2390 
dff_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp2 (
2391 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2392 
        .q   (true_htickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
2393 
    .clk (htcmp2_clk),
2394 
    .se  (se),
2395 
    `SIMPLY_RISC_SCANIN,
2396 
    .so  ()
2397 
);
2398 
`endif
2399 95 fafa1971 
 
2400 
// THREAD3
2401 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2402 
dffe_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp3 (
2403 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2404 
        .q   (true_htickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
2405 95 fafa1971 
    .en (~(tlu_htickcmp_en_l[3])), .clk(clk),
2406 
    .se  (se),
2407 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2408 95 fafa1971 
    .so  ()
2409 
);
2410 113 albert.wat 
`else
2411 
dff_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp3 (
2412 
    .din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
2413 
        .q   (true_htickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
2414 
    .clk (htcmp3_clk),
2415 
    .se  (se),
2416 
    `SIMPLY_RISC_SCANIN,
2417 
    .so  ()
2418 
);
2419 
`endif
2420 95 fafa1971 
 
2421 
 
2422 
// Select 1/4 sources. Assume compare is independent of read
2423 
// and thus needs separate mux
2424 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
2425 
   assign htickcmp_data[`TLU_ASR_DATA_WIDTH-4:0] = true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:2];
2426 
   assign htickcmp_rdata[`TLU_ASR_DATA_WIDTH-2:0] = true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:0];
2427 
`else
2428 95 fafa1971 
 
2429 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH-3) mux_htickcmp_data (
2430 
       .in0  (true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:2]),
2431 
       .in1  (true_htickcmp1[`TLU_ASR_DATA_WIDTH-2:2]),
2432 
       .in2  (true_htickcmp2[`TLU_ASR_DATA_WIDTH-2:2]),
2433 
       .in3  (true_htickcmp3[`TLU_ASR_DATA_WIDTH-2:2]),
2434 95 fafa1971 
       .sel0 (tlu_tickcmp_sel[0]),
2435 
       .sel1 (tlu_tickcmp_sel[1]),
2436 
       .sel2 (tlu_tickcmp_sel[2]),
2437 
       .sel3 (tlu_tickcmp_sel[3]),
2438 113 albert.wat 
       .dout (htickcmp_data[`TLU_ASR_DATA_WIDTH-4:0])
2439 95 fafa1971 
);
2440 
//
2441 
// mux for read
2442 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH-1) mux_htickcmp_rdata (
2443 
       .in0  (true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
2444 
       .in1  (true_htickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
2445 
       .in2  (true_htickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
2446 
       .in3  (true_htickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
2447 95 fafa1971 
       .sel0 (tlu_thrd_rsel_e[0]),
2448 
       .sel1 (tlu_thrd_rsel_e[1]),
2449 
       .sel2 (tlu_thrd_rsel_e[2]),
2450 
       .sel3 (tlu_thrd_rsel_e[3]),
2451 113 albert.wat 
       .dout (htickcmp_rdata[`TLU_ASR_DATA_WIDTH-2:0])
2452 95 fafa1971 
);
2453 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
2454 95 fafa1971 
 
2455 
//
2456 
// evaluate for htickcmp match
2457 
assign tlu_htick_match =
2458 113 albert.wat 
           (htickcmp_data[`TICKCMP_RANGE_HI:`TICKCMP_RANGE_LO] ==
2459 95 fafa1971 
            true_tick[60:0]);
2460 
//
2461 
//=========================================================================================
2462 
// HINTP REG for Threads
2463 
//=========================================================================================
2464 
// added for hypervisor support
2465 
// modified for timing
2466 
// creating clocks for accessing the hintp regs
2467 
assign tlu_hintp_en_l_g[0] =
2468 
           ~(tlu_set_hintp_g[0] | tlu_wr_hintp_g[0]);
2469 
assign tlu_hintp_en_l_g[1] =
2470 
           ~(tlu_set_hintp_g[1] | tlu_wr_hintp_g[1]);
2471 
assign tlu_hintp_en_l_g[2] =
2472 
           ~(tlu_set_hintp_g[2] | tlu_wr_hintp_g[2]);
2473 
assign tlu_hintp_en_l_g[3] =
2474 
           ~(tlu_set_hintp_g[3] | tlu_wr_hintp_g[3]);
2475 
 
2476 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2477 
`else
2478 
clken_buf clkbf_hintp0 (
2479 
                .rclk   (clk),
2480 
                .enb_l  (tlu_hintp_en_l_g[0]),
2481 
                .tmb_l  (se_l),
2482 
                .clk    (hintp0_clk)
2483 
);
2484 
`endif
2485 95 fafa1971 
 
2486 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2487 
`else
2488 
clken_buf clkbf_hintp1 (
2489 
                .rclk   (clk),
2490 
                .enb_l  (tlu_hintp_en_l_g[1]),
2491 
                .tmb_l  (se_l),
2492 
                .clk    (hintp1_clk)
2493 
);
2494 
`endif
2495 95 fafa1971 
 
2496 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2497 
`else
2498 
clken_buf clkbf_hintp2 (
2499 
                .rclk   (clk),
2500 
                .enb_l  (tlu_hintp_en_l_g[2]),
2501 
                .tmb_l  (se_l),
2502 
                .clk    (hintp2_clk)
2503 
);
2504 
`endif
2505 95 fafa1971 
 
2506 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2507 
`else
2508 
clken_buf clkbf_hintp3 (
2509 
                .rclk   (clk),
2510 
                .enb_l  (tlu_hintp_en_l_g[3]),
2511 
                .tmb_l  (se_l),
2512 
                .clk    (hintp3_clk)
2513 
);
2514 
`endif
2515 95 fafa1971 
//
2516 
// setting the value of hintp registers
2517 
//
2518 
// Thread 0
2519 
// added for timing
2520 
assign tlu_set_hintp_g[0] =
2521 
           tlu_set_hintp_sel_g[0] & tlu_htick_match;
2522 
 
2523 
// modified to reflect the physical implementation
2524 
// assign hintp_din[0] =
2525 
//            (tlu_set_hintp_g[0])? tlu_set_hintp_g[0]: wsr_data_w[0];
2526 
 
2527 
mux2ds mx_hintp_din_0 (
2528 
       .in0  (tlu_set_hintp_g[0]),
2529 
           .in1  (wsr_data_w[0]),
2530 
       .sel0 (tlu_set_hintp_g[0]),
2531 
           .sel1 (~tlu_set_hintp_g[0]),
2532 
       .dout (hintp_din[0])
2533 
);
2534 
 
2535 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2536 
dffre_s dffr_hintp0 (
2537 95 fafa1971 
     .din (hintp_din[0]),
2538 
     .q   (tlu_hintp[0]),
2539 
     .en (~(tlu_hintp_en_l_g[0])), .clk(clk),
2540 
         .rst (local_rst),
2541 
     .se  (se),
2542 113 albert.wat 
     `SIMPLY_RISC_SCANIN,
2543 95 fafa1971 
     .so  ()
2544 
);
2545 113 albert.wat 
`else
2546 
dffr_s dffr_hintp0 (
2547 
     .din (hintp_din[0]),
2548 
     .q   (tlu_hintp[0]),
2549 
     .clk (hintp0_clk),
2550 
         .rst (local_rst),
2551 
     .se  (se),
2552 
     `SIMPLY_RISC_SCANIN,
2553 
     .so  ()
2554 
);
2555 
`endif
2556 95 fafa1971 
 
2557 
// Thread 1
2558 
// added for timing
2559 
assign tlu_set_hintp_g[1] =
2560 
           tlu_set_hintp_sel_g[1] & tlu_htick_match;
2561 
 
2562 
// modified to reflect the physical implementation
2563 
// assign hintp_din[1] =
2564 
//            (tlu_set_hintp_g[1])? tlu_set_hintp_g[1]: wsr_data_w[0];
2565 
 
2566 
mux2ds mx_hintp_din_1 (
2567 
       .in0  (tlu_set_hintp_g[1]),
2568 
           .in1  (wsr_data_w[0]),
2569 
       .sel0 (tlu_set_hintp_g[1]),
2570 
           .sel1 (~tlu_set_hintp_g[1]),
2571 
       .dout (hintp_din[1])
2572 
);
2573 
 
2574 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2575 
dffre_s dffr_hintp1 (
2576 95 fafa1971 
     .din (hintp_din[1]),
2577 
     .q   (tlu_hintp[1]),
2578 
     .en (~(tlu_hintp_en_l_g[1])), .clk(clk),
2579 
         .rst (local_rst),
2580 
     .se  (se),
2581 113 albert.wat 
     `SIMPLY_RISC_SCANIN,
2582 95 fafa1971 
     .so  ()
2583 
);
2584 113 albert.wat 
`else
2585 
dffr_s dffr_hintp1 (
2586 
     .din (hintp_din[1]),
2587 
     .q   (tlu_hintp[1]),
2588 
     .clk (hintp1_clk),
2589 
         .rst (local_rst),
2590 
     .se  (se),
2591 
     `SIMPLY_RISC_SCANIN,
2592 
     .so  ()
2593 
);
2594 
`endif
2595 95 fafa1971 
 
2596 
// Thread 2
2597 
// added for timing
2598 
assign tlu_set_hintp_g[2] =
2599 
           tlu_set_hintp_sel_g[2] & tlu_htick_match;
2600 
 
2601 
// modified to reflect the physical implementation
2602 
// assign hintp_din[2] =
2603 
//            (tlu_set_hintp_g[2])? tlu_set_hintp_g[2]: wsr_data_w[0];
2604 
 
2605 
mux2ds mx_hintp_din_2 (
2606 
       .in0  (tlu_set_hintp_g[2]),
2607 
           .in1  (wsr_data_w[0]),
2608 
       .sel0 (tlu_set_hintp_g[2]),
2609 
           .sel1 (~tlu_set_hintp_g[2]),
2610 
       .dout (hintp_din[2])
2611 
);
2612 
 
2613 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2614 
dffre_s dffr_hintp2 (
2615 95 fafa1971 
     .din (hintp_din[2]),
2616 
     .q   (tlu_hintp[2]),
2617 
     .en (~(tlu_hintp_en_l_g[2])), .clk(clk),
2618 
         .rst (local_rst),
2619 
     .se  (se),
2620 113 albert.wat 
     `SIMPLY_RISC_SCANIN,
2621 95 fafa1971 
     .so  ()
2622 
);
2623 113 albert.wat 
`else
2624 
dffr_s dffr_hintp2 (
2625 
     .din (hintp_din[2]),
2626 
     .q   (tlu_hintp[2]),
2627 
     .clk (hintp2_clk),
2628 
         .rst (local_rst),
2629 
     .se  (se),
2630 
     `SIMPLY_RISC_SCANIN,
2631 
     .so  ()
2632 
);
2633 
`endif
2634 95 fafa1971 
 
2635 
// Thread 3
2636 
// added for timing
2637 
assign tlu_set_hintp_g[3] =
2638 
           tlu_set_hintp_sel_g[3] & tlu_htick_match;
2639 
 
2640 
// modified to reflect the physical implementation
2641 
// assign hintp_din[3] =
2642 
//            (tlu_set_hintp_g[3])? tlu_set_hintp_g[3]: wsr_data_w[0];
2643 
 
2644 
mux2ds mx_hintp_din_3 (
2645 
       .in0  (tlu_set_hintp_g[3]),
2646 
           .in1  (wsr_data_w[0]),
2647 
       .sel0 (tlu_set_hintp_g[3]),
2648 
           .sel1 (~tlu_set_hintp_g[3]),
2649 
       .dout (hintp_din[3])
2650 
);
2651 
 
2652 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2653 
dffre_s dffr_hintp3 (
2654 95 fafa1971 
     .din (hintp_din[3]),
2655 
     .q   (tlu_hintp[3]),
2656 
     .en (~(tlu_hintp_en_l_g[3])), .clk(clk),
2657 
         .rst (local_rst),
2658 
     .se  (se),
2659 113 albert.wat 
     `SIMPLY_RISC_SCANIN,
2660 95 fafa1971 
     .so  ()
2661 
);
2662 113 albert.wat 
`else
2663 
dffr_s dffr_hintp3 (
2664 
     .din (hintp_din[3]),
2665 
     .q   (tlu_hintp[3]),
2666 
     .clk (hintp3_clk),
2667 
         .rst (local_rst),
2668 
     .se  (se),
2669 
     `SIMPLY_RISC_SCANIN,
2670 
     .so  ()
2671 
);
2672 
`endif
2673 95 fafa1971 
 
2674 
//=========================================================================================
2675 
//      DONE/RETRY
2676 
//=========================================================================================
2677 
 
2678 
// PC/nPC will be updated by pc/npc from IFU,
2679 
// OR, Done/Retry which reads TSA in E stage. Execution of Done/Retry will
2680 
// put pc/npc temporarily in bypass flop which will then update actual pc/npc
2681 
// in g. Update of pc/npc by inst_in_w or done/retry thus becomes aligned.
2682 
// recoded due to lint violations - individualized the components
2683 
/*
2684 113 albert.wat 
dff_s #(`TLU_TSA_WIDTH) poptsa_m (
2685 95 fafa1971 
    .din (tsa_rdata[`TLU_TSA_WIDTH-1:0]),
2686 
        .q   (tsa_data_m[`TLU_TSA_WIDTH-1:0]),
2687 
    .clk (clk),
2688 
    .se  (se),
2689 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2690 95 fafa1971 
    .so  ()
2691 
);
2692 
//
2693 
// added, modified for hypervisor and timing
2694 
assign dnrtry_pstate_m =
2695 
       {2'b0,  // old IG, MG - replaced by global register
2696 
        tsa_data_m[`TSA_PSTATE_VRANGE2_HI:`TSA_PSTATE_VRANGE2_LO],
2697 
        2'b0,  // memory model has been change to TSO only - bug 2588
2698 
        1'b0,  // old RED - replaced by hpstate.red
2699 
        tsa_data_m[`TSA_PSTATE_VRANGE1_HI:`TSA_PSTATE_VRANGE1_LO],
2700 
        1'b0}; // old AG - replaced by global register
2701 
 
2702 113 albert.wat 
dff_s #(12) dff_pstate_g (
2703 95 fafa1971 
    .din (dnrtry_pstate_m[`PSTATE_TRUE_WIDTH-1:0]),
2704 
        .q   (dnrtry_pstate[`PSTATE_TRUE_WIDTH-1:0]),
2705 
    .clk (clk),
2706 
    .se  (se),
2707 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2708 95 fafa1971 
    .so  ()
2709 
    );
2710 
*/
2711 
// recoded due to lint violation
2712 
 
2713 113 albert.wat 
dff_s #(`WSR_PSTATE_VR_WIDTH) dff_dnrtry_pstate_m (
2714 
    .din ({tsa_rdata[`TSA_PSTATE_VRANGE2_HI:`TSA_PSTATE_VRANGE2_LO],
2715 
           tsa_rdata[`TSA_PSTATE_VRANGE1_HI:`TSA_PSTATE_VRANGE1_LO]}),
2716 
        .q   (dnrtry_pstate_m[`WSR_PSTATE_VR_WIDTH-1:0]),
2717 95 fafa1971 
    .clk (clk),
2718 
    .se  (se),
2719 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2720 95 fafa1971 
    .so  ()
2721 
);
2722 
 
2723 113 albert.wat 
dff_s #(`WSR_PSTATE_VR_WIDTH) dff_pstate_g (
2724 
    .din (dnrtry_pstate_m[`WSR_PSTATE_VR_WIDTH-1:0]),
2725 
        .q   (dnrtry_pstate_g[`WSR_PSTATE_VR_WIDTH-1:0]),
2726 95 fafa1971 
    .clk (clk),
2727 
    .se  (se),
2728 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2729 95 fafa1971 
    .so  ()
2730 
);
2731 
 
2732 113 albert.wat 
dff_s #(`WSR_PSTATE_VR_WIDTH) dff_pstate_w2 (
2733 
    .din (dnrtry_pstate_g[`WSR_PSTATE_VR_WIDTH-1:0]),
2734 
        .q   (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
2735 95 fafa1971 
    .clk (clk),
2736 
    .se  (se),
2737 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2738 95 fafa1971 
    .so  ()
2739 
);
2740 
// assign dnrtry_pstate_m[`WSR_PSTATE_VR_WIDTH-1:0] =
2741 
//        {tsa_data_m[`TSA_PSTATE_VRANGE2_HI:`TSA_PSTATE_VRANGE2_LO],
2742 
//         tsa_data_m[`TSA_PSTATE_VRANGE1_HI:`TSA_PSTATE_VRANGE1_LO]};
2743 
//
2744 
// reading hpstate from tsa for recovery
2745 
// recoded due to lint violations
2746 
 
2747 113 albert.wat 
dff_s #(`TSA_HTSTATE_WIDTH) dff_tsa_dnrtry_hpstate_m (
2748 95 fafa1971 
    // .din (tsa_rdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO]),
2749 113 albert.wat 
    .din (tsa_rdata[`TLU_RD_HTSTATE_HI:`TLU_RD_HTSTATE_LO]),
2750 
        .q   (tsa_dnrtry_hpstate_m[`TSA_HTSTATE_WIDTH-1:0]),
2751 95 fafa1971 
    .clk (clk),
2752 
    .se  (se),
2753 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2754 95 fafa1971 
    .so  ()
2755 
);
2756 
 
2757 113 albert.wat 
dff_s #(`TSA_HTSTATE_WIDTH) dff_tsa_dnrtry_hpstate_g (
2758 95 fafa1971 
//     .din (tsa_data_m[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO]),
2759 113 albert.wat 
    .din (tsa_dnrtry_hpstate_m[`TSA_HTSTATE_WIDTH-1:0]),
2760 
        .q   (tsa_dnrtry_hpstate_g[`TSA_HTSTATE_WIDTH-1:0]),
2761 95 fafa1971 
    .clk (clk),
2762 
    .se  (se),
2763 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2764 95 fafa1971 
    .so  ()
2765 
);
2766 
//
2767 
// added for timing
2768 113 albert.wat 
dff_s #(`TSA_HTSTATE_WIDTH) dff_tsa_dnrtry_hpstate_w2 (
2769 
    .din (tsa_dnrtry_hpstate_g[`TSA_HTSTATE_WIDTH-1:0]),
2770 
        .q   (tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1:0]),
2771 95 fafa1971 
    .clk (clk),
2772 
    .se  (se),
2773 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2774 95 fafa1971 
    .so  ()
2775 
);
2776 
 
2777 
// reading value of original global registers from tsa for recovery
2778 
// recoded due to lint cleanup
2779 
// assign dnrtry_global_m = tsa_data_m[`TLU_GL_HI:`TLU_GL_LO];
2780 
 
2781 113 albert.wat 
dff_s #(`TSA_GLOBAL_WIDTH) dff_dnrtry_global_m (
2782 
    .din (tsa_rdata[`TLU_GL_HI:`TLU_GL_LO]),
2783 
        .q   (dnrtry_global_m[`TSA_GLOBAL_WIDTH-1:0]),
2784 95 fafa1971 
    .clk (clk),
2785 
    .se  (se),
2786 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2787 95 fafa1971 
    .so  ()
2788 
);
2789 
 
2790 113 albert.wat 
dff_s #(`TSA_GLOBAL_WIDTH) dff_global_g (
2791 
    .din (dnrtry_global_m[`TSA_GLOBAL_WIDTH-1:0]),
2792 
        .q   (tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]),
2793 95 fafa1971 
    .clk (clk),
2794 
    .se  (se),
2795 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2796 95 fafa1971 
    .so  ()
2797 
);
2798 
//
2799 
/* logic moved to tlu_misctl
2800 
// added due to lint violations
2801 113 albert.wat 
dff_s #(47) dff_tsa_pc_m (
2802 95 fafa1971 
    .din (tsa_rdata[`TLU_PC_HI:`TLU_PC_LO]),
2803 
        .q   (tsa_pc_m[46:0]),
2804 
    .clk (clk),
2805 
    .se  (se),
2806 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2807 95 fafa1971 
    .so  ()
2808 
);
2809 
 
2810 113 albert.wat 
dff_s #(47) dff_tsa_npc_m (
2811 95 fafa1971 
    .din (tsa_rdata[`TLU_NPC_HI:`TLU_NPC_LO]),
2812 
        .q   (tsa_npc_m[46:0]),
2813 
    .clk (clk),
2814 
    .se  (se),
2815 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2816 95 fafa1971 
    .so  ()
2817 
);
2818 
 
2819 
// pstate may have to be staged by an additional cycle.
2820 
assign dnrtry_pc[48:0]  = {tsa_pc_m[46:0],2'b00};
2821 
assign dnrtry_npc[48:0] = {tsa_npc_m[46:0],2'b00};
2822 
*/
2823 
 
2824 
//=========================================================================================
2825 
//      PC/nPC
2826 
//=========================================================================================
2827 
 
2828 
// TRUE PC/NPC. AN INSTRUCTION'S PC/NPC IS VISIBLE IN W2.
2829 
// F:S:D:E:M:G:W2
2830 
// Modified by Done/Retry and inst
2831 
 
2832 
/* logic moved to tlu_misctl
2833 
// On done, npc will become pc.
2834 
// modified due to bug 3017
2835 
// pc width increase from 48 -> 49 bits
2836 
mux3ds #(49) finalpc_sel_m (
2837 
       .in0  (dnrtry_pc[48:0]),
2838 
           .in1  (dnrtry_npc[48:0]),
2839 
           .in2  (ifu_tlu_pc_m[48:0]),
2840 
       .sel0 (tlu_retry_inst_m),
2841 
           .sel1 (tlu_done_inst_m),
2842 
           .sel2 (tlu_dnrtry_inst_m_l),
2843 
       .dout (pc_new[48:0])
2844 
);
2845 
// On done, npc will stay npc. The valid to the IFU will
2846 
// not be signaled along with npc for a done.
2847 
// modified due to bug 3017
2848 
// pc width increase from 48 -> 49 bits
2849 
mux2ds #(49) finalnpc_sel_m (
2850 
       .in0  (dnrtry_npc[48:0]),
2851 
       .in1  (ifu_tlu_npc_m[48:0]),
2852 
       .sel0 (~tlu_dnrtry_inst_m_l),
2853 
       .sel1 (tlu_dnrtry_inst_m_l),
2854 
       .dout (npc_new[48:0])
2855 
);
2856 
 
2857 113 albert.wat 
dff_s #(49) dff_pc_new_w (
2858 95 fafa1971 
    .din (pc_new[48:0]),
2859 
    .q   (pc_new_w[48:0]),
2860 
    .clk (clk),
2861 
    .se  (se),
2862 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2863 95 fafa1971 
    .so  ()
2864 
);
2865 
 
2866 113 albert.wat 
dff_s #(49) dff_npc_new_w (
2867 95 fafa1971 
    .din (npc_new[48:0]),
2868 
    .q   (npc_new_w[48:0]),
2869 
    .clk (clk),
2870 
    .se  (se),
2871 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2872 95 fafa1971 
    .so  ()
2873 
);
2874 
*/
2875 
//
2876 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2877 
`else
2878 
clken_buf clkbf_pc0 (
2879 
    .rclk  (clk),
2880 
    .enb_l (tlu_update_pc_l_w[0]),
2881 
        .tmb_l (se_l),
2882 
        .clk   (pc0_clk)
2883 
);
2884 
`endif
2885 95 fafa1971 
 
2886 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2887 
`else
2888 
clken_buf clkbf_pc1 (
2889 
    .rclk  (clk),
2890 
    .enb_l (tlu_update_pc_l_w[1]),
2891 
        .tmb_l (se_l),
2892 
        .clk   (pc1_clk)
2893 
);
2894 
`endif
2895 95 fafa1971 
 
2896 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2897 
`else
2898 
clken_buf clkbf_pc2 (
2899 
    .rclk  (clk),
2900 
    .enb_l (tlu_update_pc_l_w[2]),
2901 
        .tmb_l (se_l),
2902 
        .clk   (pc2_clk)
2903 
);
2904 
`endif
2905 95 fafa1971 
 
2906 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
2907 
`else
2908 
clken_buf clkbf_pc3 (
2909 
    .rclk  (clk),
2910 
    .enb_l (tlu_update_pc_l_w[3]),
2911 
        .tmb_l (se_l),
2912 
        .clk   (pc3_clk)
2913 
);
2914 
`endif
2915 95 fafa1971 
//
2916 
// modified for bug 3017
2917 
// all pc width has been increased from 48 -> 49 bits
2918 
// Thread 0
2919 
//
2920 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2921 
dffe_s #(49) pc0_true (
2922 95 fafa1971 
    .din (tlu_pc_new_w[48:0]),
2923 
    .q   (true_pc0[48:0]),
2924 
    .en (~(tlu_update_pc_l_w[0])), .clk(clk),
2925 
    .se  (se),
2926 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2927 95 fafa1971 
    .so  ()
2928 
);
2929 113 albert.wat 
`else
2930 
dff_s #(49) pc0_true (
2931 
    .din (tlu_pc_new_w[48:0]),
2932 
    .q   (true_pc0[48:0]),
2933 
    .clk (pc0_clk),
2934 
    .se  (se),
2935 
    `SIMPLY_RISC_SCANIN,
2936 
    .so  ()
2937 
);
2938 
`endif
2939 95 fafa1971 
 
2940 
// update_pc will be used for both pc and npc - in this case
2941 
// npc will contain gibberish but it's okay.
2942 
// modified to avert area growth
2943 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2944 
dffe_s #(49) npc0_true (
2945 95 fafa1971 
    .din (tlu_npc_new_w[48:0]),
2946 
    .q  (true_npc0[48:0]),
2947 
    .en (~(tlu_update_pc_l_w[0])), .clk(clk),
2948 
    .se  (se),
2949 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2950 95 fafa1971 
    .so  ()
2951 
);
2952 113 albert.wat 
`else
2953 
dff_s #(49) npc0_true (
2954 
    .din (tlu_npc_new_w[48:0]),
2955 
    .q  (true_npc0[48:0]),
2956 
    .clk (pc0_clk),
2957 
    .se  (se),
2958 
    `SIMPLY_RISC_SCANIN,
2959 
    .so  ()
2960 
);
2961 
`endif
2962 95 fafa1971 
//
2963 
// THREAD1
2964 
//
2965 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2966 
dffe_s #(49) pc1_true (
2967 95 fafa1971 
    .din (tlu_pc_new_w[48:0]),
2968 
    .q   (true_pc1[48:0]),
2969 
    .en (~(tlu_update_pc_l_w[1])), .clk(clk),
2970 
    .se  (se),
2971 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2972 95 fafa1971 
    .so  ()
2973 
);
2974 113 albert.wat 
`else
2975 
dff_s #(49) pc1_true (
2976 
    .din (tlu_pc_new_w[48:0]),
2977 
    .q   (true_pc1[48:0]),
2978 
    .clk (pc1_clk),
2979 
    .se  (se),
2980 
    `SIMPLY_RISC_SCANIN,
2981 
    .so  ()
2982 
);
2983 
`endif
2984 95 fafa1971 
 
2985 
// update_pc will be used for both pc and npc - in this case
2986 
// npc will contain gibberish but it's okay.
2987 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
2988 
dffe_s #(49) npc1_true (
2989 95 fafa1971 
    .din (tlu_npc_new_w[48:0]),
2990 
    .q   (true_npc1[48:0]),
2991 
    .en (~(tlu_update_pc_l_w[1])), .clk(clk),
2992 
    .se  (se),
2993 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
2994 95 fafa1971 
    .so  ()
2995 
);
2996 113 albert.wat 
`else
2997 
dff_s #(49) npc1_true (
2998 
    .din (tlu_npc_new_w[48:0]),
2999 
    .q   (true_npc1[48:0]),
3000 
    .clk (pc1_clk),
3001 
    .se  (se),
3002 
    `SIMPLY_RISC_SCANIN,
3003 
    .so  ()
3004 
);
3005 
`endif
3006 95 fafa1971 
//
3007 
// THREAD2
3008 
//
3009 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3010 
dffe_s #(49) pc2_true (
3011 95 fafa1971 
    .din (tlu_pc_new_w[48:0]),
3012 
    .q   (true_pc2[48:0]),
3013 
    .en (~(tlu_update_pc_l_w[2])), .clk(clk),
3014 
    .se  (se),
3015 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3016 95 fafa1971 
    .so  ()
3017 
);
3018 113 albert.wat 
`else
3019 
dff_s #(49) pc2_true (
3020 
    .din (tlu_pc_new_w[48:0]),
3021 
    .q   (true_pc2[48:0]),
3022 
    .clk (pc2_clk),
3023 
    .se  (se),
3024 
    `SIMPLY_RISC_SCANIN,
3025 
    .so  ()
3026 
);
3027 
`endif
3028 95 fafa1971 
 
3029 
// update_pc will be used for both pc and npc - in this case
3030 
// npc will contain gibberish but it's okay.
3031 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3032 
dffe_s #(49) npc2_true (
3033 95 fafa1971 
    .din (tlu_npc_new_w[48:0]),
3034 
    .q   (true_npc2[48:0]),
3035 
    .en (~(tlu_update_pc_l_w[2])), .clk(clk),
3036 
    .se  (se),
3037 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3038 95 fafa1971 
    .so  ()
3039 
);
3040 113 albert.wat 
`else
3041 
dff_s #(49) npc2_true (
3042 
    .din (tlu_npc_new_w[48:0]),
3043 
    .q   (true_npc2[48:0]),
3044 
    .clk (pc2_clk),
3045 
    .se  (se),
3046 
    `SIMPLY_RISC_SCANIN,
3047 
    .so  ()
3048 
);
3049 
`endif
3050 95 fafa1971 
//
3051 
// THREAD3
3052 
//
3053 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3054 
dffe_s #(49) pc3_true (
3055 95 fafa1971 
    .din (tlu_pc_new_w[48:0]),
3056 
    .q   (true_pc3[48:0]),
3057 
    .en (~(tlu_update_pc_l_w[3])), .clk(clk),
3058 
    .se  (se),
3059 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3060 95 fafa1971 
    .so  ()
3061 
);
3062 113 albert.wat 
`else
3063 
dff_s #(49) pc3_true (
3064 
    .din (tlu_pc_new_w[48:0]),
3065 
    .q   (true_pc3[48:0]),
3066 
    .clk (pc3_clk),
3067 
    .se  (se),
3068 
    `SIMPLY_RISC_SCANIN,
3069 
    .so  ()
3070 
);
3071 
`endif
3072 95 fafa1971 
 
3073 
// update_pc will be used for both pc and npc - in this case
3074 
// npc will contain gibberish but it's okay.
3075 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3076 
dffe_s #(49) npc3_true (
3077 95 fafa1971 
    .din (tlu_npc_new_w[48:0]),
3078 
    .q   (true_npc3[48:0]),
3079 
    .en (~(tlu_update_pc_l_w[3])), .clk(clk),
3080 
    .se  (se),
3081 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3082 95 fafa1971 
    .so  ()
3083 
);
3084 113 albert.wat 
`else
3085 
dff_s #(49) npc3_true (
3086 
    .din (tlu_npc_new_w[48:0]),
3087 
    .q   (true_npc3[48:0]),
3088 
    .clk (pc3_clk),
3089 
    .se  (se),
3090 
    `SIMPLY_RISC_SCANIN,
3091 
    .so  ()
3092 
);
3093 
`endif
3094 95 fafa1971 
 
3095 
//=========================================================================================
3096 
//      Generating Trap Vector
3097 
//=========================================================================================
3098 
//
3099 
// Normal Trap Processing.
3100 
mux2ds mux_pc_bit15_sel (
3101 
    .in0  (tlu_tl_gt_0_w2),
3102 
    .in1  (htba_data[0]),
3103 
    .sel0  (~tlu_trap_hpstate_enb),
3104 
    .sel1  (tlu_trap_hpstate_enb),
3105 
    .dout (pc_bit15_sel)
3106 
);
3107 
//
3108 
// modified to help speed up simulation time
3109 
//
3110 113 albert.wat 
assign tlu_rstvaddr_base[33:0] = `RSTVADDR_BASE;
3111 95 fafa1971 
mux3ds #(34) nrmlpc_sel_w2 (
3112 
       .in0  (tlu_rstvaddr_base[33:0]),
3113 
           .in1  ({tba_data[32:0], tlu_tl_gt_0_w2}),
3114 
           .in2  ({htba_data[33:1], pc_bit15_sel}),
3115 
       .sel0 (tlu_pc_mxsel_w2[0]),
3116 
           .sel1 (tlu_pc_mxsel_w2[1]),
3117 
           .sel2 (tlu_pc_mxsel_w2[2]),
3118 
       .dout (partial_trap_pc_w2[33:0])
3119 
);
3120 
 
3121 
assign tlu_partial_trap_pc_w1[33:0] = partial_trap_pc_w2[33:0];
3122 
 
3123 
// restore pc/npc select
3124 
// true pc muxed into restore pc; previously restore_pcx was muxed in.
3125 
// modified due to bug 3017
3126 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
3127 
   assign restore_pc_w2[48:0] = true_pc0[48:0];
3128 
   assign restore_npc_w2[48:0] = true_npc0[48:0];
3129 
`else
3130 95 fafa1971 
 
3131 
mux4ds  #(98) trprsel (
3132 
        .in0    ({true_pc0[48:0],true_npc0[48:0]}),
3133 
        .in1    ({true_pc1[48:0],true_npc1[48:0]}),
3134 
        .in2    ({true_pc2[48:0],true_npc2[48:0]}),
3135 
        .in3    ({true_pc3[48:0],true_npc3[48:0]}),
3136 
        .sel0   (tlu_thrd_wsel_w2[0]),
3137 
        .sel1   (tlu_thrd_wsel_w2[1]),
3138 
        .sel2   (tlu_thrd_wsel_w2[2]),
3139 
        .sel3   (tlu_thrd_wsel_w2[3]),
3140 
        .dout   ({restore_pc_w2[48:0],restore_npc_w2[48:0]})
3141 
);
3142 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
3143 95 fafa1971 
 
3144 
//
3145 
// the matching of the w1 and w2 is intentional
3146 
assign tlu_restore_pc_w1[48:0]  = restore_pc_w2[48:0];
3147 
assign tlu_restore_npc_w1[48:0] = restore_npc_w2[48:0];
3148 
 
3149 
//=========================================================================================
3150 
//      TAP PC OBSERVABILITY
3151 
//=========================================================================================
3152 
//
3153 
// modified due to spec change
3154 
// shadow scan
3155 
// thread 0 data
3156 113 albert.wat 
assign sscan_data_test0[`TDP_SSCAN_WIDTH-1:0] =
3157 95 fafa1971 
           {true_hpstate0[2:0],
3158 113 albert.wat 
            true_pstate0[`PSTATE_PRIV],
3159 
            true_pstate0[`PSTATE_IE],
3160 95 fafa1971 
            true_pc0[47:2]};
3161 
//
3162 
// thread 1 data
3163 113 albert.wat 
assign sscan_data_test1[`TDP_SSCAN_WIDTH-1:0] =
3164 95 fafa1971 
           {true_hpstate1[2:0],
3165 113 albert.wat 
            true_pstate1[`PSTATE_PRIV],
3166 
            true_pstate1[`PSTATE_IE],
3167 95 fafa1971 
            true_pc1[47:2]};
3168 
//
3169 
// thread 2 data
3170 113 albert.wat 
assign sscan_data_test2[`TDP_SSCAN_WIDTH-1:0] =
3171 95 fafa1971 
           {true_hpstate2[2:0],
3172 113 albert.wat 
            true_pstate2[`PSTATE_PRIV],
3173 
            true_pstate2[`PSTATE_IE],
3174 95 fafa1971 
            true_pc2[47:2]};
3175 
//
3176 
// thread 3 data
3177 113 albert.wat 
assign sscan_data_test3[`TDP_SSCAN_WIDTH-1:0] =
3178 95 fafa1971 
           {true_hpstate3[2:0],
3179 113 albert.wat 
            true_pstate3[`PSTATE_PRIV],
3180 
            true_pstate3[`PSTATE_IE],
3181 95 fafa1971 
            true_pc3[47:2]};
3182 
//
3183 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
3184 
   assign tdp_sscan_test_data[`TDP_SSCAN_WIDTH-1:0] = sscan_data_test0[`TDP_SSCAN_WIDTH-1:0];
3185 
`else
3186 95 fafa1971 
 
3187 113 albert.wat 
mux4ds #(`TDP_SSCAN_WIDTH) mx_sscan_test_data (
3188 
       .in0  (sscan_data_test0[`TDP_SSCAN_WIDTH-1:0]),
3189 
       .in1  (sscan_data_test1[`TDP_SSCAN_WIDTH-1:0]),
3190 
       .in2  (sscan_data_test2[`TDP_SSCAN_WIDTH-1:0]),
3191 
       .in3  (sscan_data_test3[`TDP_SSCAN_WIDTH-1:0]),
3192 95 fafa1971 
       .sel0 (sscan_tid_sel[0]),
3193 
       .sel1 (sscan_tid_sel[1]),
3194 
       .sel2 (sscan_tid_sel[2]),
3195 
       .sel3 (sscan_tid_sel[3]),
3196 113 albert.wat 
       .dout (tdp_sscan_test_data[`TDP_SSCAN_WIDTH-1:0])
3197 95 fafa1971 
);
3198 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
3199 95 fafa1971 
 
3200 113 albert.wat 
assign sscan_tid_sel[`TLU_THRD_NUM-1:0] = ctu_sscan_tid[`TLU_THRD_NUM-1:0];
3201 95 fafa1971 
 
3202 113 albert.wat 
assign tlu_sscan_test_data[`TDP_SSCAN_WIDTH-1:0] =
3203 
          tdp_sscan_test_data[`TDP_SSCAN_WIDTH-1:0];
3204 95 fafa1971 
 
3205 
//=========================================================================================
3206 
//      PSTATE for Threads
3207 
//=========================================================================================
3208 
 
3209 
// pstate needs to be updated on a trap. Assume for now that only non-RED state instruction
3210 
// related traps are handled.
3211 
 
3212 
// Normal traps, non-red mode.
3213 
assign pstate_priv_set = tlu_select_tba_w2 | local_rst | tlu_select_redmode;
3214 
//
3215 113 albert.wat 
assign pstate_priv_thrd_set[0] = pstate_priv_set | ~true_hpstate0[`HPSTATE_ENB];
3216 
assign pstate_priv_thrd_set[1] = pstate_priv_set | ~true_hpstate1[`HPSTATE_ENB];
3217 
assign pstate_priv_thrd_set[2] = pstate_priv_set | ~true_hpstate2[`HPSTATE_ENB];
3218 
assign pstate_priv_thrd_set[3] = pstate_priv_set | ~true_hpstate3[`HPSTATE_ENB];
3219 95 fafa1971 
//
3220 
// modified for bug 3349
3221 
assign pstate_priv_update_w2[0] =
3222 
       ~(tlu_update_pstate_l_w2[0] &
3223 113 albert.wat 
        (true_hpstate0[`HPSTATE_ENB] | tlu_update_hpstate_l_w2[0])) |
3224 
        (~wsr_data_w2[`WSR_HPSTATE_ENB] & tlu_hpstate_din_sel0[1]);
3225 95 fafa1971 
assign pstate_priv_update_w2[1] =
3226 
       ~(tlu_update_pstate_l_w2[1] &
3227 113 albert.wat 
        (true_hpstate1[`HPSTATE_ENB] | tlu_update_hpstate_l_w2[1])) |
3228 
        (~wsr_data_w2[`WSR_HPSTATE_ENB] & tlu_hpstate_din_sel1[1]);
3229 95 fafa1971 
assign pstate_priv_update_w2[2] =
3230 
       ~(tlu_update_pstate_l_w2[2] &
3231 113 albert.wat 
        (true_hpstate2[`HPSTATE_ENB] | tlu_update_hpstate_l_w2[2])) |
3232 
        (~wsr_data_w2[`WSR_HPSTATE_ENB] & tlu_hpstate_din_sel2[1]);
3233 95 fafa1971 
assign pstate_priv_update_w2[3] =
3234 
       ~(tlu_update_pstate_l_w2[3] &
3235 113 albert.wat 
        (true_hpstate3[`HPSTATE_ENB] | tlu_update_hpstate_l_w2[3])) |
3236 
        (~wsr_data_w2[`WSR_HPSTATE_ENB] & tlu_hpstate_din_sel3[1]);
3237 95 fafa1971 
//
3238 
assign hpstate_priv_update_w2[0] =
3239 
       ~(tlu_update_hpstate_l_w2[0] &
3240 113 albert.wat 
        (true_hpstate0[`HPSTATE_ENB] | tlu_update_pstate_l_w2[0]));
3241 95 fafa1971 
assign hpstate_priv_update_w2[1] =
3242 
       ~(tlu_update_hpstate_l_w2[1] &
3243 113 albert.wat 
        (true_hpstate1[`HPSTATE_ENB] | tlu_update_pstate_l_w2[1]));
3244 95 fafa1971 
assign hpstate_priv_update_w2[2] =
3245 
       ~(tlu_update_hpstate_l_w2[2] &
3246 113 albert.wat 
        (true_hpstate2[`HPSTATE_ENB] | tlu_update_pstate_l_w2[2]));
3247 95 fafa1971 
assign hpstate_priv_update_w2[3] =
3248 
       ~(tlu_update_hpstate_l_w2[3] &
3249 113 albert.wat 
        (true_hpstate3[`HPSTATE_ENB] | tlu_update_pstate_l_w2[3]));
3250 95 fafa1971 
//
3251 
// added for bug 2161 and modified for bug 2161
3252 113 albert.wat 
assign hpstate_enb_set[0] = true_hpstate0[`HPSTATE_ENB] & ~(local_rst | tlu_select_redmode);
3253 
assign hpstate_enb_set[1] = true_hpstate1[`HPSTATE_ENB] & ~(local_rst | tlu_select_redmode);
3254 
assign hpstate_enb_set[2] = true_hpstate2[`HPSTATE_ENB] & ~(local_rst | tlu_select_redmode);
3255 
assign hpstate_enb_set[3] = true_hpstate3[`HPSTATE_ENB] & ~(local_rst | tlu_select_redmode);
3256 95 fafa1971 
 
3257 
// added for hpstate.ibe ECO
3258 
// modified due to timing - tlu_ibrkpt_trap_g has been delayed one stage to tlu_ibrkpt_trap_w2
3259 
assign hpstate_ibe_set[0] =
3260 113 albert.wat 
           true_hpstate0[`HPSTATE_IBE] & ~(local_rst | tlu_select_redmode | tlu_ibrkpt_trap_w2);
3261 95 fafa1971 
assign hpstate_ibe_set[1] =
3262 113 albert.wat 
           true_hpstate1[`HPSTATE_IBE] & ~(local_rst | tlu_select_redmode | tlu_ibrkpt_trap_w2);
3263 95 fafa1971 
assign hpstate_ibe_set[2] =
3264 113 albert.wat 
           true_hpstate2[`HPSTATE_IBE] & ~(local_rst | tlu_select_redmode | tlu_ibrkpt_trap_w2);
3265 95 fafa1971 
assign hpstate_ibe_set[3] =
3266 113 albert.wat 
           true_hpstate3[`HPSTATE_IBE] & ~(local_rst | tlu_select_redmode | tlu_ibrkpt_trap_w2);
3267 95 fafa1971 
//
3268 
// added due to TLZ spec change
3269 
// modified for bug 3505
3270 113 albert.wat 
assign hpstate_tlz_set[0] = true_hpstate0[`HPSTATE_TLZ] & ~(local_rst | tlu_select_redmode);
3271 
assign hpstate_tlz_set[1] = true_hpstate1[`HPSTATE_TLZ] & ~(local_rst | tlu_select_redmode);
3272 
assign hpstate_tlz_set[2] = true_hpstate2[`HPSTATE_TLZ] & ~(local_rst | tlu_select_redmode);
3273 
assign hpstate_tlz_set[3] = true_hpstate3[`HPSTATE_TLZ] & ~(local_rst | tlu_select_redmode);
3274 95 fafa1971 
//
3275 
// thread 0
3276 
assign tlu_select_tle[0] =
3277 
           tlu_pstate_tle[0] & ~(tlu_select_redmode);
3278 
// modified for timing and bug 3417
3279 
assign tlu_select_cle[0] =
3280 
           tlu_select_tle[0] &
3281 113 albert.wat 
          (tlu_select_tba_w2 | ~true_hpstate0[`HPSTATE_ENB]);
3282 95 fafa1971 
//         tlu_select_tle[0] & tlu_select_tba_w2;
3283 
//
3284 
// modified for timing and width cleanup
3285 
/*
3286 
assign  ntrap_pstate0[`PSTATE_TRUE_WIDTH-1:0] =
3287 
    {2'b0,  // tlu_select_int_global - replaced by gl register
3288 
                // tlu_select_mmu_global - replaced by gl register
3289 
         tlu_select_cle[0], // cle<-tle, or 0
3290 
         tlu_select_tle[0], // keep old tle, or 0
3291 
     2'b0,
3292 
     1'b0,  // tlu_select_redmode - replaced by hpstate.red
3293 
         1'b1,  // fp turned on
3294 
         1'b0,  // address masking turned off
3295 
         pstate_priv_thrd_set[0], // enter priv mode for priv traps
3296 
         1'b0,  // interrupts disabled
3297 
         1'b0}; // tlu_select_alt_global - replaced by gl register
3298 
*/
3299 113 albert.wat 
assign  ntrap_pstate0[`WSR_PSTATE_VR_WIDTH-1:0] =
3300 95 fafa1971 
    {tlu_select_cle[0], // cle<-tle, or 0
3301 
         tlu_select_tle[0], // keep old tle, or 0
3302 
         1'b1,  // fp turned on
3303 
         1'b0,  // address masking turned off
3304 
         pstate_priv_thrd_set[0], // enter priv mode for priv traps
3305 
         1'b0}; // interrupts disabled
3306 
//
3307 
// thread 1
3308 
assign tlu_select_tle[1] =
3309 
           tlu_pstate_tle[1] & ~(tlu_select_redmode);
3310 
// modified for timing and bug 3417
3311 
assign tlu_select_cle[1] =
3312 
           tlu_select_tle[1] &
3313 113 albert.wat 
          (tlu_select_tba_w2 | ~true_hpstate1[`HPSTATE_ENB]);
3314 95 fafa1971 
//           tlu_select_tle[1] & tlu_select_tba_w2;
3315 
//
3316 
// modified due to timing
3317 
/*
3318 
assign  ntrap_pstate1[`PSTATE_TRUE_WIDTH-1:0] =
3319 
    {2'b0,  // tlu_select_int_global - replaced by gl register
3320 
                // tlu_select_mmu_global - replaced by gl register
3321 
         tlu_select_cle[1], // cle<-tle, or 0
3322 
         tlu_select_tle[1], // keep old tle, or 0
3323 
     2'b0,
3324 
     1'b0,  // tlu_select_redmode - replaced by hpstate.red
3325 
         1'b1,  // fp turned on
3326 
         1'b0,  // address masking turned off
3327 
         pstate_priv_thrd_set[1], // enter priv mode for priv traps
3328 
         1'b0,  // interrupts disabled
3329 
         1'b0}; // tlu_select_alt_global - replaced by gl register
3330 
*/
3331 113 albert.wat 
assign  ntrap_pstate1[`WSR_PSTATE_VR_WIDTH-1:0] =
3332 95 fafa1971 
    {tlu_select_cle[1], // cle<-tle, or 0
3333 
         tlu_select_tle[1], // keep old tle, or 0
3334 
         1'b1,  // fp turned on
3335 
         1'b0,  // address masking turned off
3336 
         pstate_priv_thrd_set[1], // enter priv mode for priv traps
3337 
         1'b0}; // interrupts disabled//
3338 
//
3339 
// thread 2
3340 
assign tlu_select_tle[2] =
3341 
           tlu_pstate_tle[2] & ~(tlu_select_redmode);
3342 
// modified for timing and bug 3417
3343 
assign tlu_select_cle[2] =
3344 
           tlu_select_tle[2] &
3345 113 albert.wat 
          (tlu_select_tba_w2 | ~true_hpstate2[`HPSTATE_ENB]);
3346 95 fafa1971 
//           tlu_select_tle[2] & tlu_select_tba_w2;
3347 
//
3348 
// modified for timing and width cleanup
3349 
/*
3350 
assign  ntrap_pstate2[`PSTATE_TRUE_WIDTH-1:0] =
3351 
    {2'b0,  // tlu_select_int_global - replaced by gl register
3352 
                // tlu_select_mmu_global - replaced by gl register
3353 
         tlu_select_cle[2], // cle<-tle, or 0
3354 
         tlu_select_tle[2], // keep old tle, or 0
3355 
     2'b0,
3356 
     1'b0,  // tlu_select_redmode - replaced by hpstate.red
3357 
         1'b1,  // fp turned on
3358 
         1'b0,  // address masking turned off
3359 
         pstate_priv_thrd_set[2], // enter priv mode for priv traps
3360 
         1'b0,  // interrupts disabled
3361 
         1'b0}; // tlu_select_alt_global - replaced by gl register
3362 
*/
3363 113 albert.wat 
assign  ntrap_pstate2[`WSR_PSTATE_VR_WIDTH-1:0] =
3364 95 fafa1971 
    {tlu_select_cle[2], // cle<-tle, or 0
3365 
         tlu_select_tle[2], // keep old tle, or 0
3366 
         1'b1,  // fp turned on
3367 
         1'b0,  // address masking turned off
3368 
         pstate_priv_thrd_set[2], // enter priv mode for priv traps
3369 
         1'b0}; // interrupts disabled//
3370 
//
3371 
// thread 3
3372 
assign tlu_select_tle[3] =
3373 
           tlu_pstate_tle[3] & ~(tlu_select_redmode);
3374 
// modified for timing and bug 3417
3375 
assign tlu_select_cle[3] =
3376 
           tlu_select_tle[3] &
3377 113 albert.wat 
          (tlu_select_tba_w2 | ~true_hpstate3[`HPSTATE_ENB]);
3378 95 fafa1971 
//           tlu_select_tle[3] & tlu_select_tba_w2;
3379 
//
3380 
// modified for timing
3381 
/*
3382 
assign  ntrap_pstate3[`PSTATE_TRUE_WIDTH-1:0] =
3383 
    {2'b0,  // tlu_select_int_global - replaced by gl register
3384 
                // tlu_select_mmu_global - replaced by gl register
3385 
         tlu_select_cle[3], // cle<-tle, or 0
3386 
         tlu_select_tle[3], // keep old tle, or 0
3387 
     2'b0,
3388 
     1'b0,  // tlu_select_redmode - replaced by hpstate.red
3389 
         1'b1,  // fp turned on
3390 
         1'b0,  // address masking turned off
3391 
         pstate_priv_thrd_set[3], // enter priv mode for priv traps
3392 
         1'b0,  // interrupts disabled
3393 
         1'b0}; // tlu_select_alt_global - replaced by gl register
3394 
*/
3395 113 albert.wat 
assign  ntrap_pstate3[`WSR_PSTATE_VR_WIDTH-1:0] =
3396 95 fafa1971 
    {tlu_select_cle[3], // cle<-tle, or 0
3397 
         tlu_select_tle[3], // keep old tle, or 0
3398 
         1'b1,  // fp turned on
3399 
         1'b0,  // address masking turned off
3400 
         pstate_priv_thrd_set[3], // enter priv mode for priv traps
3401 
         1'b0}; // interrupts disabled//
3402 
 
3403 
// Clock Enable Buffers
3404 
//
3405 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
3406 
`else
3407 
clken_buf clkbf_ps0 (
3408 
    .rclk  (clk),
3409 
        .enb_l (tlu_update_pstate_l_w2[0]),
3410 
        .tmb_l (se_l),
3411 
        .clk   (pstate0_clk)
3412 
);
3413 
`endif
3414 95 fafa1971 
 
3415 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
3416 
`else
3417 
clken_buf clkbf_ps1 (
3418 
    .rclk  (clk),
3419 
        .enb_l (tlu_update_pstate_l_w2[1]),
3420 
        .tmb_l (se_l),
3421 
        .clk   (pstate1_clk)
3422 
);
3423 
`endif
3424 95 fafa1971 
 
3425 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
3426 
`else
3427 
clken_buf clkbf_ps2 (
3428 
    .rclk  (clk),
3429 
        .enb_l (tlu_update_pstate_l_w2[2]),
3430 
        .tmb_l (se_l),
3431 
        .clk   (pstate2_clk)
3432 
);
3433 
`endif
3434 95 fafa1971 
 
3435 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
3436 
`else
3437 
clken_buf clkbf_ps3 (
3438 
    .rclk  (clk),
3439 
        .enb_l (tlu_update_pstate_l_w2[3]),
3440 
        .tmb_l (se_l),
3441 
        .clk   (pstate3_clk)
3442 
);
3443 
`endif
3444 95 fafa1971 
//
3445 
// added for hypervisor support
3446 
// clock enable buffers for updating the hpstate registers
3447 
//
3448 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
3449 
`else
3450 
clken_buf clkbf_hps0 (
3451 
    .rclk  (clk),
3452 
        .enb_l (tlu_update_hpstate_l_w2[0]),
3453 
        .tmb_l (se_l),
3454 
        .clk   (hpstate0_clk)
3455 
);
3456 
`endif
3457 95 fafa1971 
 
3458 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
3459 
`else
3460 
clken_buf clkbf_hps1 (
3461 
    .rclk  (clk),
3462 
        .enb_l (tlu_update_hpstate_l_w2[1]),
3463 
        .tmb_l (se_l),
3464 
        .clk   (hpstate1_clk)
3465 
);
3466 
`endif
3467 95 fafa1971 
 
3468 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
3469 
`else
3470 
clken_buf clkbf_hps2 (
3471 
    .rclk  (clk),
3472 
        .enb_l (tlu_update_hpstate_l_w2[2]),
3473 
        .tmb_l (se_l),
3474 
        .clk   (hpstate2_clk)
3475 
);
3476 
`endif
3477 95 fafa1971 
 
3478 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
3479 
`else
3480 
clken_buf clkbf_hps3 (
3481 
    .rclk  (clk),
3482 
        .enb_l (tlu_update_hpstate_l_w2[3]),
3483 
        .tmb_l (se_l),
3484 
        .clk   (hpstate3_clk)
3485 
);
3486 
`endif
3487 95 fafa1971 
// assign the initial value of hpstate.red mode
3488 
//
3489 
// modified for bug 1893
3490 
// assign hpstate_redmode =
3491 
//            (local_rst)? 1'b1: tlu_select_redmode;
3492 
assign hpstate_redmode =
3493 
           local_rst | (~local_rst & tlu_select_redmode);
3494 
//
3495 
// extracting hpstate from wsr_data
3496 
//
3497 
// modified for timing tlu_wsr_data_w -> wsr_data_w2
3498 113 albert.wat 
assign wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0] =
3499 
     {wsr_data_w2[`WSR_HPSTATE_IBE],
3500 
      wsr_data_w2[`WSR_HPSTATE_ENB],
3501 
      wsr_data_w2[`WSR_HPSTATE_RED],
3502 
      wsr_data_w2[`WSR_HPSTATE_PRIV],
3503 
      wsr_data_w2[`WSR_HPSTATE_TLZ]
3504 95 fafa1971 
     };
3505 
//
3506 
// added or modified for hypervisor support
3507 
// modified due to timing
3508 
/*
3509 
assign wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-1:0] =
3510 
    {2'b0,  // old IG, MG - replaced by global register
3511 
     tlu_wsr_data_w[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
3512 
     2'b0,  // memory model has been change to TSO only - bug 2588
3513 
     1'b0,  // old red, - replaced by hpstate.red
3514 
     tlu_wsr_data_w[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO],
3515 
     1'b0};  // old AG - replaced by global register
3516 
 
3517 
assign wsr_data_pstate_g[`WSR_PSTATE_VR_WIDTH-1:0] =
3518 
       {tlu_wsr_data_w[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
3519 
        tlu_wsr_data_w[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
3520 
*/
3521 113 albert.wat 
assign wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0] =
3522 
       {wsr_data_w2[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
3523 
        wsr_data_w2[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
3524 95 fafa1971 
//
3525 
// THREAD0
3526 
// added for bug 1575
3527 
// modified for bug 2584
3528 
// assign tlu_pstate_nt_sel0 = ~|(tlu_pstate_din_sel0[1:0]);
3529 
assign tlu_pstate_nt_sel0 =
3530 
          ~(tlu_pstate_din_sel0[0] | tlu_pstate_wsr_sel0);
3531 
//
3532 
// modified for bug 3349
3533 
assign tlu_pstate_wsr_sel0 =
3534 
           tlu_pstate_din_sel0[1] |
3535 113 albert.wat 
           (~(true_hpstate0[`HPSTATE_ENB] & wsr_data_w2[`WSR_HPSTATE_ENB]) &
3536 95 fafa1971 
              tlu_hpstate_din_sel0[1]);
3537 
//            (~true_hpstate0[`HPSTATE_ENB] & tlu_hpstate_din_sel0[1]);
3538 
 
3539 113 albert.wat 
mux3ds #(`WSR_PSTATE_VR_WIDTH) mux_restore_pstate0(
3540 
       .in0  (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
3541 
           .in1  (wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
3542 
           .in2  (ntrap_pstate0[`WSR_PSTATE_VR_WIDTH-1:0]),
3543 95 fafa1971 
       .sel0 (tlu_pstate_din_sel0[0]),
3544 
           .sel1 (tlu_pstate_wsr_sel0),
3545 
           .sel2 (tlu_pstate_nt_sel0),
3546 113 albert.wat 
       .dout (restore_pstate0[`WSR_PSTATE_VR_WIDTH-1:0])
3547 95 fafa1971 
);
3548 
 
3549 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3550 
dffe_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate0_w3 (
3551 
    .din ({restore_pstate0[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
3552 
           restore_pstate0[`WSR_PSTATE_VRANGE1_LO]}),
3553 
    .q   ({restore_pstate0_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
3554 
           restore_pstate0_w3[`WSR_PSTATE_VRANGE1_LO]}),
3555 95 fafa1971 
    .en (~(tlu_update_pstate_l_w2[0])), .clk(clk),
3556 
    .se  (se),
3557 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3558 95 fafa1971 
    .so  ()
3559 
);
3560 113 albert.wat 
`else
3561 
dff_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate0_w3 (
3562 
    .din ({restore_pstate0[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
3563 
           restore_pstate0[`WSR_PSTATE_VRANGE1_LO]}),
3564 
    .q   ({restore_pstate0_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
3565 
           restore_pstate0_w3[`WSR_PSTATE_VRANGE1_LO]}),
3566 
    .clk (pstate0_clk),
3567 
    .se  (se),
3568 
    `SIMPLY_RISC_SCANIN,
3569 
    .so  ()
3570 
);
3571 
`endif
3572 95 fafa1971 
//
3573 113 albert.wat 
dffe_s dffe_pstate0_priv (
3574 
    .din (restore_pstate0[`WSR_PSTATE_VR_PRIV]),
3575 
    .q   (restore_pstate0_w3[`WSR_PSTATE_VR_PRIV]),
3576 95 fafa1971 
    .en  (pstate_priv_update_w2[0]),
3577 
    .clk (clk),
3578 
    .se  (se),
3579 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3580 95 fafa1971 
    .so  ()
3581 
);
3582 
//
3583 
// true_pstate0 assignments
3584 113 albert.wat 
assign true_pstate0[`PSTATE_TRUE_WIDTH-1:0] =
3585 95 fafa1971 
           {2'b0, // tlu_select_int_global - replaced by gl register
3586 
                  // tlu_select_mmu_global - replaced by gl register
3587 113 albert.wat 
            restore_pstate0_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE2_LO],
3588 95 fafa1971 
            2'b0, // fixed mmodel - TSO
3589 
            1'b0, // redmode - replaced by hpstate.red
3590 113 albert.wat 
            restore_pstate0_w3[`WSR_PSTATE_VRANGE1_HI:`WSR_PSTATE_VRANGE1_LO],
3591 95 fafa1971 
            1'b0}; // tlu_select_alt_global - replaced by gl register
3592 
//
3593 
// modified for timing
3594 
/*
3595 
mux3ds #(9) mux_restore_pstate0(
3596 
       .in0  (dnrtry_pstate[`PSTATE_TRUE_WIDTH-3:1]),
3597 
           .in1  (wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-3:1]),
3598 
           .in2  (ntrap_pstate0[`PSTATE_TRUE_WIDTH-3:1]),
3599 
       .sel0 (tlu_pstate_din_sel0[0]),
3600 
       // modified for bug 2584
3601 
           // .sel1 (tlu_pstate_din_sel0[1]),
3602 
           .sel1 (tlu_pstate_wsr_sel0),
3603 
           .sel2 (tlu_pstate_nt_sel0),
3604 
       .dout (restore_pstate0[`PSTATE_TRUE_WIDTH-3:1])
3605 
);
3606 
 
3607 113 albert.wat 
dff_s #(`PSTATE_TRUE_WIDTH) pstate0_1 (
3608 95 fafa1971 
    .din (restore_pstate0[`PSTATE_TRUE_WIDTH-1:0]),
3609 
        .q   (true_pstate0[`PSTATE_TRUE_WIDTH-1:0]),
3610 
    .clk (pstate0_clk),
3611 
    .se  (se),
3612 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3613 95 fafa1971 
    .so  ()
3614 
 );
3615 
//
3616 113 albert.wat 
dff_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate0 (
3617 95 fafa1971 
    .din ({restore_pstate0[`PSTATE_TRUE_WIDTH-1:3],
3618 
           restore_pstate0[1:0]}),
3619 
    .q   ({true_pstate0[`PSTATE_TRUE_WIDTH-1:3],
3620 
           true_pstate0[1:0]}),
3621 
    .clk (pstate0_clk),
3622 
    .se  (se),
3623 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3624 95 fafa1971 
    .so  ()
3625 
);
3626 
//
3627 113 albert.wat 
dffe_s dffe_pstate0_priv (
3628 95 fafa1971 
    .din (restore_pstate0[`PSTATE_PRIV]),
3629 
    .q   (true_pstate0[`PSTATE_PRIV]),
3630 
    .en  (pstate_priv_update_g[0]),
3631 
    .clk (clk),
3632 
    .se  (se),
3633 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3634 95 fafa1971 
    .so  ()
3635 
);
3636 
// modified for hypervisor support
3637 
assign restore_pstate0[11:10] = 2'b0;
3638 
assign restore_pstate0[0]     = 1'b0;
3639 
//
3640 
// modified to reflect the physical implementation
3641 
// assign hpstate_dnrtry_priv_w2[0] =
3642 
           (true_hpstate0[`HPSTATE_ENB])?
3643 
            tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV] :
3644 
            dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV];
3645 
*/
3646 
mux2ds mx_hpstate_dnrtry_priv_w2_0 (
3647 113 albert.wat 
       .in0  (tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV]),
3648 
           .in1  (dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV]),
3649 
       .sel0 (true_hpstate0[`HPSTATE_ENB]),
3650 
           .sel1 (~true_hpstate0[`HPSTATE_ENB]),
3651 95 fafa1971 
       .dout (hpstate_dnrtry_priv_w2[0])
3652 
);
3653 
//
3654 113 albert.wat 
assign dnrtry_hpstate0_w2[`TLU_HPSTATE_WIDTH-1:0] =
3655 
       {tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1],
3656 
        true_hpstate0[`HPSTATE_ENB],
3657 
        tsa_dnrtry_hpstate_w2[`HPSTATE_RED],
3658 95 fafa1971 
        hpstate_dnrtry_priv_w2[0],
3659 113 albert.wat 
        tsa_dnrtry_hpstate_w2[`HPSTATE_TLZ]};
3660 95 fafa1971 
 
3661 
// added for bug 3747
3662 
assign hpstate_priv_set = ~(tlu_select_tba_w2) | tlu_select_redmode;
3663 
//
3664 
// constructing the hpstate for hyper-privileged traps
3665 
//
3666 113 albert.wat 
assign hntrap_hpstate0_w2[`TLU_HPSTATE_WIDTH-1:0] =
3667 95 fafa1971 
       {hpstate_ibe_set[0],
3668 
        hpstate_enb_set[0],
3669 
        hpstate_redmode, // Redmode bit
3670 
        // modified for bug 3747
3671 
        hpstate_priv_set, // hyper-privileged bit
3672 
        hpstate_tlz_set[0]}; // TLZ interrupt bit
3673 
 
3674 
assign tlu_hpstate_hnt_sel0 =
3675 
       ~(tlu_hpstate_din_sel0[0] | tlu_hpstate_wsr_sel0);
3676 
//
3677 
assign tlu_hpstate_wsr_sel0 =
3678 
           tlu_hpstate_din_sel0[1] |
3679 113 albert.wat 
           (~true_hpstate0[`HPSTATE_ENB] & tlu_pstate_din_sel0[1]);
3680 95 fafa1971 
 
3681 113 albert.wat 
mux3ds #(`TLU_HPSTATE_WIDTH) mux_restore_hpstate0(
3682 
       .in0  (dnrtry_hpstate0_w2[`TLU_HPSTATE_WIDTH-1:0]),
3683 
           .in1  (wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0]),
3684 
           .in2  (hntrap_hpstate0_w2[`TLU_HPSTATE_WIDTH-1:0]),
3685 95 fafa1971 
       .sel0 (tlu_hpstate_din_sel0[0]),
3686 
       .sel1 (tlu_hpstate_wsr_sel0),
3687 
           .sel2 (tlu_hpstate_hnt_sel0),
3688 113 albert.wat 
       .dout (restore_hpstate0[`TLU_HPSTATE_WIDTH-1:0])
3689 95 fafa1971 
);
3690 
//
3691 
// need to initialize hpstate.enb = 0
3692 
// need to initialize hpstate.ibe = 0
3693 
// modified due to the addition of hpstate.ibe
3694 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3695 
dffre_s #(2) dffr_true_hpst0_enb_ibe (
3696 
    .din (restore_hpstate0[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
3697 
        .q   (true_hpstate0[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
3698 95 fafa1971 
    .rst (local_rst),
3699 
    .en (~(tlu_update_hpstate_l_w2[0])), .clk(clk),
3700 
    .se  (se),
3701 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3702 95 fafa1971 
    .so  ()
3703 
 );
3704 113 albert.wat 
`else
3705 
dffr_s #(2) dffr_true_hpst0_enb_ibe (
3706 
    .din (restore_hpstate0[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
3707 
        .q   (true_hpstate0[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
3708 
    .rst (local_rst),
3709 
    .clk (hpstate0_clk),
3710 
    .se  (se),
3711 
    `SIMPLY_RISC_SCANIN,
3712 
    .so  ()
3713 
 );
3714 
`endif
3715 95 fafa1971 
//
3716 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3717 
dffe_s #(2) dff_true_hpstate0 (
3718 
    .din ({restore_hpstate0[`HPSTATE_RED],
3719 
           restore_hpstate0[`HPSTATE_TLZ]}),
3720 
    .q   ({true_hpstate0[`HPSTATE_RED],
3721 
           true_hpstate0[`HPSTATE_TLZ]}),
3722 95 fafa1971 
    .en (~(tlu_update_hpstate_l_w2[0])), .clk(clk),
3723 
    .se  (se),
3724 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3725 95 fafa1971 
    .so  ()
3726 
);
3727 113 albert.wat 
`else
3728 
dff_s #(2) dff_true_hpstate0 (
3729 
    .din ({restore_hpstate0[`HPSTATE_RED],
3730 
           restore_hpstate0[`HPSTATE_TLZ]}),
3731 
    .q   ({true_hpstate0[`HPSTATE_RED],
3732 
           true_hpstate0[`HPSTATE_TLZ]}),
3733 
    .clk (hpstate0_clk),
3734 
    .se  (se),
3735 
    `SIMPLY_RISC_SCANIN,
3736 
    .so  ()
3737 
);
3738 
`endif
3739 95 fafa1971 
//
3740 113 albert.wat 
dffe_s dffe_hpstate0_priv (
3741 
    .din (restore_hpstate0[`HPSTATE_PRIV]),
3742 
    .q   (true_hpstate0[`HPSTATE_PRIV]),
3743 95 fafa1971 
    .en  (hpstate_priv_update_w2[0]),
3744 
    .clk (clk),
3745 
    .se  (se),
3746 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3747 95 fafa1971 
    .so  ()
3748 
);
3749 
 
3750 113 albert.wat 
assign tlu_ifu_pstate_pef[0]   = true_pstate0[`PSTATE_PEF];
3751 
assign tlu_lsu_pstate_cle[0]   = true_pstate0[`PSTATE_CLE];
3752 
assign tlu_lsu_pstate_priv[0]  = true_pstate0[`PSTATE_PRIV];
3753 
assign tlu_int_pstate_ie[0]    = true_pstate0[`PSTATE_IE];
3754 
assign local_pstate_ie[0]      = true_pstate0[`PSTATE_IE];
3755 95 fafa1971 
// assign tlu_pstate_cle[0]        = true_pstate0[`PSTATE_CLE];
3756 113 albert.wat 
assign tlu_pstate_tle[0]            = true_pstate0[`PSTATE_TLE];
3757 95 fafa1971 
// assign tlu_pstate_priv[0]       = true_pstate0[`PSTATE_PRIV];
3758 113 albert.wat 
assign local_pstate_priv[0]    = true_pstate0[`PSTATE_PRIV];
3759 
assign tlu_pstate_am[0]     = true_pstate0[`PSTATE_AM];
3760 
assign tlu_int_redmode[0] = true_hpstate0[`HPSTATE_RED];
3761 
assign tlu_lsu_redmode[0] = true_hpstate0[`HPSTATE_RED];
3762 95 fafa1971 
//
3763 
// hypervisor privilege indicator
3764 113 albert.wat 
assign tlu_hpstate_priv[0]   = true_hpstate0[`HPSTATE_PRIV];
3765 
assign local_hpstate_priv[0] = true_hpstate0[`HPSTATE_PRIV];
3766 
assign tcl_hpstate_priv[0]   = true_hpstate0[`HPSTATE_PRIV];
3767 95 fafa1971 
//
3768 
// hypervisor lite mode selector
3769 113 albert.wat 
assign tlu_hpstate_enb[0]   = true_hpstate0[`HPSTATE_ENB];
3770 
assign local_hpstate_enb[0] = true_hpstate0[`HPSTATE_ENB];
3771 
assign tcl_hpstate_enb[0]   = true_hpstate0[`HPSTATE_ENB];
3772 95 fafa1971 
 
3773 
// hypervisor tlz indicator
3774 113 albert.wat 
assign tlu_hpstate_tlz[0] = true_hpstate0[`HPSTATE_TLZ];
3775 95 fafa1971 
 
3776 
// hypervisor instruction breakpt enable
3777 113 albert.wat 
assign tlu_hpstate_ibe[0] = true_hpstate0[`HPSTATE_IBE];
3778 95 fafa1971 
 
3779 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
3780 
   assign tlu_ifu_pstate_pef[3:1] = 3'b000;
3781 
   assign tlu_lsu_pstate_cle[3:1] = 3'b000;
3782 
   assign tlu_lsu_pstate_priv[3:1] = 3'b000;
3783 
   assign tlu_int_pstate_ie[3:1] = 3'b000;
3784 
   assign local_pstate_ie[3:1] = 3'b000;
3785 
   assign tlu_pstate_tle[3:1] = 3'b000;
3786 
   assign local_pstate_priv[3:1] = 3'b000;
3787 
   assign tlu_pstate_am[3:1] = 3'b000;
3788 
   assign tlu_int_redmode[3:1] = 3'b000;
3789 
   assign tlu_lsu_redmode[3:1] = 3'b000;
3790 
   assign tlu_hpstate_priv[3:1] = 3'b000;
3791 
   assign local_hpstate_priv[3:1] = 3'b000;
3792 
   assign tcl_hpstate_priv[3:1] = 3'b000;
3793 
   assign tlu_hpstate_enb[3:1] = 3'b000;
3794 
   assign local_hpstate_enb[3:1] = 3'b000;
3795 
   assign tcl_hpstate_enb[3:1] = 3'b000;
3796 
   assign tlu_hpstate_tlz[3:1] = 3'b000;
3797 
   assign tlu_hpstate_ibe[3:1] = 3'b000;
3798 95 fafa1971 
 
3799 113 albert.wat 
`else
3800 
 
3801 95 fafa1971 
// THREAD 1
3802 
assign tlu_pstate_nt_sel1 =
3803 
          ~(tlu_pstate_din_sel1[0] | tlu_pstate_wsr_sel1);
3804 
//
3805 
// modified for bug 3349
3806 
assign tlu_pstate_wsr_sel1 =
3807 
              tlu_pstate_din_sel1[1] |
3808 113 albert.wat 
           (~(true_hpstate1[`HPSTATE_ENB] & wsr_data_w2[`WSR_HPSTATE_ENB]) &
3809 95 fafa1971 
              tlu_hpstate_din_sel1[1]);
3810 
//            (~true_hpstate1[`HPSTATE_ENB] & tlu_hpstate_din_sel1[1]);
3811 
 
3812 113 albert.wat 
mux3ds #(`WSR_PSTATE_VR_WIDTH) mux_restore_pstate1(
3813 
       .in0  (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
3814 
           .in1  (wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
3815 
           .in2  (ntrap_pstate1[`WSR_PSTATE_VR_WIDTH-1:0]),
3816 95 fafa1971 
       .sel0 (tlu_pstate_din_sel1[0]),
3817 
           .sel1 (tlu_pstate_wsr_sel1),
3818 
           .sel2 (tlu_pstate_nt_sel1),
3819 113 albert.wat 
       .dout (restore_pstate1[`WSR_PSTATE_VR_WIDTH-1:0])
3820 95 fafa1971 
);
3821 
 
3822 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3823 
dffe_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate1_w3 (
3824 
    .din ({restore_pstate1[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
3825 
           restore_pstate1[`WSR_PSTATE_VRANGE1_LO]}),
3826 
    .q   ({restore_pstate1_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
3827 
           restore_pstate1_w3[`WSR_PSTATE_VRANGE1_LO]}),
3828 95 fafa1971 
    .en (~(tlu_update_pstate_l_w2[1])), .clk(clk),
3829 
    .se  (se),
3830 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3831 95 fafa1971 
    .so  ()
3832 
);
3833 113 albert.wat 
`else
3834 
dff_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate1_w3 (
3835 
    .din ({restore_pstate1[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
3836 
           restore_pstate1[`WSR_PSTATE_VRANGE1_LO]}),
3837 
    .q   ({restore_pstate1_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
3838 
           restore_pstate1_w3[`WSR_PSTATE_VRANGE1_LO]}),
3839 
    .clk (pstate1_clk),
3840 
    .se  (se),
3841 
    `SIMPLY_RISC_SCANIN,
3842 
    .so  ()
3843 
);
3844 
`endif
3845 95 fafa1971 
//
3846 113 albert.wat 
dffe_s dffe_pstate1_priv (
3847 
    .din (restore_pstate1[`WSR_PSTATE_VR_PRIV]),
3848 
    .q   (restore_pstate1_w3[`WSR_PSTATE_VR_PRIV]),
3849 95 fafa1971 
    .en  (pstate_priv_update_w2[1]),
3850 
    .clk (clk),
3851 
    .se  (se),
3852 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3853 95 fafa1971 
    .so  ()
3854 
);
3855 
//
3856 
// modified to reflect the physical implementation
3857 
/*
3858 
assign hpstate_dnrtry_priv_w2[1] =
3859 
           (true_hpstate1[`HPSTATE_ENB])?
3860 
            tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV] :
3861 
            dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV];
3862 
*/
3863 
mux2ds mx_hpstate_dnrtry_priv_w2_1 (
3864 113 albert.wat 
       .in0  (tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV]),
3865 
           .in1  (dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV]),
3866 
       .sel0 (true_hpstate1[`HPSTATE_ENB]),
3867 
           .sel1 (~true_hpstate1[`HPSTATE_ENB]),
3868 95 fafa1971 
       .dout (hpstate_dnrtry_priv_w2[1])
3869 
);
3870 
//
3871 113 albert.wat 
assign dnrtry_hpstate1_w2[`TLU_HPSTATE_WIDTH-1:0] =
3872 
       {tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1],
3873 
        true_hpstate1[`HPSTATE_ENB],
3874 
        tsa_dnrtry_hpstate_w2[`HPSTATE_RED],
3875 95 fafa1971 
        hpstate_dnrtry_priv_w2[1],
3876 113 albert.wat 
        tsa_dnrtry_hpstate_w2[`HPSTATE_TLZ]};
3877 95 fafa1971 
//
3878 
// true_pstate1 assignments
3879 113 albert.wat 
assign true_pstate1[`PSTATE_TRUE_WIDTH-1:0] =
3880 95 fafa1971 
           {2'b0, // tlu_select_int_global - replaced by gl register
3881 
                  // tlu_select_mmu_global - replaced by gl register
3882 113 albert.wat 
            restore_pstate1_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE2_LO],
3883 95 fafa1971 
            2'b0, // fixed mmodel - TSO
3884 
            1'b0, // redmode - replaced by hpstate.red
3885 113 albert.wat 
            restore_pstate1_w3[`WSR_PSTATE_VRANGE1_HI:`WSR_PSTATE_VRANGE1_LO],
3886 95 fafa1971 
            1'b0}; // tlu_select_alt_global - replaced by gl register
3887 
//
3888 
// modified for timing
3889 
/*
3890 
mux3ds #(9) mux_restore_pstate1(
3891 
       .in0  (dnrtry_pstate[`PSTATE_TRUE_WIDTH-3:1]),
3892 
           .in1  (wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-3:1]),
3893 
           .in2  (ntrap_pstate1[`PSTATE_TRUE_WIDTH-3:1]),
3894 
       .sel0 (tlu_pstate_din_sel1[0]),
3895 
       // modified for bug 2584
3896 
           // .sel1 (tlu_pstate_din_sel1[1]),
3897 
           .sel1 (tlu_pstate_wsr_sel1),
3898 
           .sel2 (tlu_pstate_nt_sel1),
3899 
       .dout (restore_pstate1[`PSTATE_TRUE_WIDTH-3:1])
3900 
);
3901 
 
3902 
`ifdef FPGA_SYN_CLK_DFF
3903 113 albert.wat 
dffe_s #(`PSTATE_TRUE_WIDTH) pstate1_1 (
3904 95 fafa1971 
    .din (restore_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
3905 
        .q   (true_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
3906 
    .en (~(tlu_update_pstate_l_w2[1])), .clk(clk),
3907 
    .se  (se),
3908 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3909 95 fafa1971 
    .so  ()
3910 
    );
3911 
`else
3912 113 albert.wat 
dff_s #(`PSTATE_TRUE_WIDTH) pstate1_1 (
3913 95 fafa1971 
    .din (restore_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
3914 
        .q   (true_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
3915 
    .clk (pstate1_clk),
3916 
    .se  (se),
3917 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3918 95 fafa1971 
    .so  ()
3919 
    );
3920 
`endif
3921 
//
3922 
`ifdef FPGA_SYN_CLK_DFF
3923 113 albert.wat 
dffe_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate1 (
3924 95 fafa1971 
    .din ({restore_pstate1[`PSTATE_TRUE_WIDTH-1:3],
3925 
           restore_pstate1[1:0]}),
3926 
    .q   ({true_pstate1[`PSTATE_TRUE_WIDTH-1:3],
3927 
           true_pstate1[1:0]}),
3928 
    .en (~(tlu_update_pstate_l_w2[1])), .clk(clk),
3929 
    .se  (se),
3930 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3931 95 fafa1971 
    .so  ()
3932 
);
3933 
`else
3934 113 albert.wat 
dff_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate1 (
3935 95 fafa1971 
    .din ({restore_pstate1[`PSTATE_TRUE_WIDTH-1:3],
3936 
           restore_pstate1[1:0]}),
3937 
    .q   ({true_pstate1[`PSTATE_TRUE_WIDTH-1:3],
3938 
           true_pstate1[1:0]}),
3939 
    .clk (pstate1_clk),
3940 
    .se  (se),
3941 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3942 95 fafa1971 
    .so  ()
3943 
);
3944 
`endif
3945 
//
3946 113 albert.wat 
dffe_s dffe_pstate1_priv (
3947 95 fafa1971 
    .din (restore_pstate1[`PSTATE_PRIV]),
3948 
    .q   (true_pstate1[`PSTATE_PRIV]),
3949 
    .en  (pstate_priv_update_g[1]),
3950 
    .clk (clk),
3951 
    .se  (se),
3952 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3953 95 fafa1971 
    .so  ()
3954 
);
3955 
//
3956 
// modified for hypervisor support
3957 
assign restore_pstate1[11:10] = 2'b0;
3958 
assign restore_pstate1[0]     = 1'b0;
3959 
*/
3960 
//
3961 
// constructing the hpstate for hyper-privileged traps
3962 
//
3963 113 albert.wat 
assign hntrap_hpstate1_w2[`TLU_HPSTATE_WIDTH-1:0] =
3964 95 fafa1971 
       {hpstate_ibe_set[1],
3965 
        hpstate_enb_set[1],
3966 
        hpstate_redmode,  // Redmode bit
3967 
        hpstate_priv_set, // hyper-privileged bit
3968 
        hpstate_tlz_set[1]}; // TLZ interrupt bit
3969 
//
3970 
assign tlu_hpstate_hnt_sel1 =
3971 
       ~(tlu_hpstate_din_sel1[0] | tlu_hpstate_wsr_sel1);
3972 
//
3973 
assign tlu_hpstate_wsr_sel1 =
3974 
           tlu_hpstate_din_sel1[1] |
3975 113 albert.wat 
           (~true_hpstate1[`HPSTATE_ENB] & tlu_pstate_din_sel1[1]);
3976 95 fafa1971 
 
3977 113 albert.wat 
mux3ds #(`TLU_HPSTATE_WIDTH) mux_restore_hpstate1 (
3978 
       .in0  (dnrtry_hpstate1_w2[`TLU_HPSTATE_WIDTH-1:0]),
3979 
           .in1  (wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0]),
3980 
           .in2  (hntrap_hpstate1_w2[`TLU_HPSTATE_WIDTH-1:0]),
3981 95 fafa1971 
       .sel0 (tlu_hpstate_din_sel1[0]),
3982 
       .sel1 (tlu_hpstate_wsr_sel1),
3983 
           .sel2 (tlu_hpstate_hnt_sel1),
3984 113 albert.wat 
       .dout (restore_hpstate1[`TLU_HPSTATE_WIDTH-1:0])
3985 95 fafa1971 
);
3986 
 
3987 
// need to initialize hpstate.enb = 0
3988 
// need to initialize hpstate.ibe = 0
3989 
// modified due to the addition of hpstate.ibe
3990 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
3991 
dffre_s #(2) dffr_true_hpst1_enb_ibe (
3992 
    .din (restore_hpstate1[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
3993 
        .q   (true_hpstate1[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
3994 95 fafa1971 
    .rst (local_rst),
3995 
    .en (~(tlu_update_hpstate_l_w2[1])), .clk(clk),
3996 
    .se  (se),
3997 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
3998 95 fafa1971 
    .so  ()
3999 
);
4000 113 albert.wat 
`else
4001 
dffr_s #(2) dffr_true_hpst1_enb_ibe (
4002 
    .din (restore_hpstate1[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4003 
        .q   (true_hpstate1[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4004 
    .rst (local_rst),
4005 
    .clk (hpstate1_clk),
4006 
    .se  (se),
4007 
    `SIMPLY_RISC_SCANIN,
4008 
    .so  ()
4009 
);
4010 
`endif
4011 95 fafa1971 
//
4012 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
4013 
dffe_s #(2) dff_true_hpstate1 (
4014 
    .din ({restore_hpstate1[`HPSTATE_RED],
4015 
           restore_hpstate1[`HPSTATE_TLZ]}),
4016 
    .q   ({true_hpstate1[`HPSTATE_RED],
4017 
           true_hpstate1[`HPSTATE_TLZ]}),
4018 95 fafa1971 
    .en (~(tlu_update_hpstate_l_w2[1])), .clk(clk),
4019 
    .se  (se),
4020 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4021 95 fafa1971 
    .so  ()
4022 
);
4023 113 albert.wat 
`else
4024 
dff_s #(2) dff_true_hpstate1 (
4025 
    .din ({restore_hpstate1[`HPSTATE_RED],
4026 
           restore_hpstate1[`HPSTATE_TLZ]}),
4027 
    .q   ({true_hpstate1[`HPSTATE_RED],
4028 
           true_hpstate1[`HPSTATE_TLZ]}),
4029 
    .clk (hpstate1_clk),
4030 
    .se  (se),
4031 
    `SIMPLY_RISC_SCANIN,
4032 
    .so  ()
4033 
);
4034 
`endif
4035 95 fafa1971 
//
4036 113 albert.wat 
dffe_s dffe_hpstate1_priv (
4037 
    .din (restore_hpstate1[`HPSTATE_PRIV]),
4038 
    .q   (true_hpstate1[`HPSTATE_PRIV]),
4039 95 fafa1971 
    .en  (hpstate_priv_update_w2[1]),
4040 
    .clk (clk),
4041 
    .se  (se),
4042 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4043 95 fafa1971 
    .so  ()
4044 
);
4045 
 
4046 113 albert.wat 
assign tlu_ifu_pstate_pef[1]   = true_pstate1[`PSTATE_PEF];
4047 
assign tlu_lsu_pstate_cle[1]   = true_pstate1[`PSTATE_CLE];
4048 
assign tlu_lsu_pstate_priv[1]  = true_pstate1[`PSTATE_PRIV];
4049 
assign tlu_int_pstate_ie[1]    = true_pstate1[`PSTATE_IE];
4050 
assign local_pstate_ie[1]      = true_pstate1[`PSTATE_IE];
4051 95 fafa1971 
// assign tlu_pstate_cle[1]        = true_pstate1[`PSTATE_CLE];
4052 113 albert.wat 
assign tlu_pstate_tle[1]           = true_pstate1[`PSTATE_TLE];
4053 95 fafa1971 
// assign tlu_pstate_priv[1]       = true_pstate1[`PSTATE_PRIV];
4054 113 albert.wat 
assign local_pstate_priv[1]    = true_pstate1[`PSTATE_PRIV];
4055 
assign tlu_pstate_am[1]            = true_pstate1[`PSTATE_AM];
4056 95 fafa1971 
// assign tlu_pstate1_mmodel[1:0] = true_pstate1[`PSTATE_MM_HI:`PSTATE_MM_LO];
4057 
//
4058 113 albert.wat 
assign tlu_int_redmode[1] = true_hpstate1[`HPSTATE_RED];
4059 
assign tlu_lsu_redmode[1] = true_hpstate1[`HPSTATE_RED];
4060 95 fafa1971 
//
4061 
// hypervisor privilege indicator
4062 113 albert.wat 
assign tlu_hpstate_priv[1]   = true_hpstate1[`HPSTATE_PRIV];
4063 
assign local_hpstate_priv[1] = true_hpstate1[`HPSTATE_PRIV];
4064 
assign tcl_hpstate_priv[1]   = true_hpstate1[`HPSTATE_PRIV];
4065 95 fafa1971 
//
4066 
// hypervisor lite mode selector
4067 113 albert.wat 
assign tlu_hpstate_enb[1]   = true_hpstate1[`HPSTATE_ENB];
4068 
assign local_hpstate_enb[1] = true_hpstate1[`HPSTATE_ENB];
4069 
assign tcl_hpstate_enb[1]   = true_hpstate1[`HPSTATE_ENB];
4070 95 fafa1971 
 
4071 
// hypervisor tlz indicator
4072 113 albert.wat 
assign tlu_hpstate_tlz[1] = true_hpstate1[`HPSTATE_TLZ];
4073 95 fafa1971 
 
4074 
// hypervisor instruction breakpt enable
4075 113 albert.wat 
assign tlu_hpstate_ibe[1] = true_hpstate1[`HPSTATE_IBE];
4076 95 fafa1971 
 
4077 
// THREAD2
4078 
// added for bug 1575
4079 
// modified for bug 2584
4080 
// assign tlu_pstate_nt_sel2 = ~|(tlu_pstate_din_sel2[1:0]);
4081 
assign tlu_pstate_nt_sel2 =
4082 
          ~(tlu_pstate_din_sel2[0] | tlu_pstate_wsr_sel2);
4083 
//
4084 
// modified for bug 3349
4085 
assign tlu_pstate_wsr_sel2 =
4086 
           tlu_pstate_din_sel2[1] |
4087 113 albert.wat 
           (~(true_hpstate2[`HPSTATE_ENB] & wsr_data_w2[`WSR_HPSTATE_ENB]) &
4088 95 fafa1971 
              tlu_hpstate_din_sel2[1]);
4089 
//            (~true_hpstate2[`HPSTATE_ENB] & tlu_hpstate_din_sel2[1]);
4090 
 
4091 113 albert.wat 
mux3ds #(`WSR_PSTATE_VR_WIDTH) mux_restore_pstate2(
4092 
       .in0  (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
4093 
           .in1  (wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
4094 
           .in2  (ntrap_pstate2[`WSR_PSTATE_VR_WIDTH-1:0]),
4095 95 fafa1971 
       .sel0 (tlu_pstate_din_sel2[0]),
4096 
           .sel1 (tlu_pstate_wsr_sel2),
4097 
           .sel2 (tlu_pstate_nt_sel2),
4098 113 albert.wat 
       .dout (restore_pstate2[`WSR_PSTATE_VR_WIDTH-1:0])
4099 95 fafa1971 
);
4100 
 
4101 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
4102 
dffe_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate2_w3 (
4103 
    .din ({restore_pstate2[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
4104 
           restore_pstate2[`WSR_PSTATE_VRANGE1_LO]}),
4105 
    .q   ({restore_pstate2_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
4106 
           restore_pstate2_w3[`WSR_PSTATE_VRANGE1_LO]}),
4107 95 fafa1971 
    .en (~(tlu_update_pstate_l_w2[2])), .clk(clk),
4108 
    .se  (se),
4109 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4110 95 fafa1971 
    .so  ()
4111 
);
4112 113 albert.wat 
`else
4113 
dff_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate2_w3 (
4114 
    .din ({restore_pstate2[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
4115 
           restore_pstate2[`WSR_PSTATE_VRANGE1_LO]}),
4116 
    .q   ({restore_pstate2_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
4117 
           restore_pstate2_w3[`WSR_PSTATE_VRANGE1_LO]}),
4118 
    .clk (pstate2_clk),
4119 
    .se  (se),
4120 
    `SIMPLY_RISC_SCANIN,
4121 
    .so  ()
4122 
);
4123 
`endif
4124 95 fafa1971 
//
4125 113 albert.wat 
dffe_s dffe_pstate2_priv (
4126 
    .din (restore_pstate2[`WSR_PSTATE_VR_PRIV]),
4127 
    .q   (restore_pstate2_w3[`WSR_PSTATE_VR_PRIV]),
4128 95 fafa1971 
    .en  (pstate_priv_update_w2[2]),
4129 
    .clk (clk),
4130 
    .se  (se),
4131 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4132 95 fafa1971 
    .so  ()
4133 
);
4134 
//
4135 
// true_pstate2 assignments
4136 113 albert.wat 
assign true_pstate2[`PSTATE_TRUE_WIDTH-1:0] =
4137 95 fafa1971 
           {2'b0, // tlu_select_int_global - replaced by gl register
4138 
                  // tlu_select_mmu_global - replaced by gl register
4139 113 albert.wat 
            restore_pstate2_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE2_LO],
4140 95 fafa1971 
            2'b0, // fixed mmodel - TSO
4141 
            1'b0, // redmode - replaced by hpstate.red
4142 113 albert.wat 
            restore_pstate2_w3[`WSR_PSTATE_VRANGE1_HI:`WSR_PSTATE_VRANGE1_LO],
4143 95 fafa1971 
            1'b0}; // tlu_select_alt_global - replaced by gl register
4144 
//
4145 
// modified for timing
4146 
/*
4147 
mux3ds #(9) mux_restore_pstate2(
4148 
       .in0  (dnrtry_pstate[`PSTATE_TRUE_WIDTH-3:1]),
4149 
           .in1  (wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-3:1]),
4150 
           .in2  (ntrap_pstate2[`PSTATE_TRUE_WIDTH-3:1]),
4151 
       .sel0 (tlu_pstate_din_sel2[0]),
4152 
       // modified for bug 2584
4153 
           // .sel1 (tlu_pstate_din_sel2[1]),
4154 
           .sel1 (tlu_pstate_wsr_sel2),
4155 
           .sel2 (tlu_pstate_nt_sel2),
4156 
       .dout (restore_pstate2[`PSTATE_TRUE_WIDTH-3:1])
4157 
);
4158 
 
4159 
`ifdef FPGA_SYN_CLK_DFF
4160 113 albert.wat 
dffe_s #(`PSTATE_TRUE_WIDTH) pstate2_1 (
4161 95 fafa1971 
    .din (restore_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
4162 
        .q   (true_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
4163 
    .en (~(tlu_update_pstate_l_w2[2])), .clk(clk),
4164 
    .se  (se),
4165 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4166 95 fafa1971 
    .so  ()
4167 
);
4168 
`else
4169 113 albert.wat 
dff_s #(`PSTATE_TRUE_WIDTH) pstate2_1 (
4170 95 fafa1971 
    .din (restore_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
4171 
        .q   (true_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
4172 
    .clk (pstate2_clk),
4173 
    .se  (se),
4174 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4175 95 fafa1971 
    .so  ()
4176 
);
4177 
`endif
4178 
//
4179 
`ifdef FPGA_SYN_CLK_DFF
4180 113 albert.wat 
dffe_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate2 (
4181 95 fafa1971 
    .din ({restore_pstate2[`PSTATE_TRUE_WIDTH-1:3],
4182 
           restore_pstate2[1:0]}),
4183 
    .q   ({true_pstate2[`PSTATE_TRUE_WIDTH-1:3],
4184 
           true_pstate2[1:0]}),
4185 
    .en (~(tlu_update_pstate_l_w2[2])), .clk(clk),
4186 
    .se  (se),
4187 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4188 95 fafa1971 
    .so  ()
4189 
);
4190 
`else
4191 113 albert.wat 
dff_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate2 (
4192 95 fafa1971 
    .din ({restore_pstate2[`PSTATE_TRUE_WIDTH-1:3],
4193 
           restore_pstate2[1:0]}),
4194 
    .q   ({true_pstate2[`PSTATE_TRUE_WIDTH-1:3],
4195 
           true_pstate2[1:0]}),
4196 
    .clk (pstate2_clk),
4197 
    .se  (se),
4198 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4199 95 fafa1971 
    .so  ()
4200 
);
4201 
`endif
4202 
//
4203 113 albert.wat 
dffe_s dffe_pstate2_priv (
4204 95 fafa1971 
    .din (restore_pstate2[`PSTATE_PRIV]),
4205 
    .q   (true_pstate2[`PSTATE_PRIV]),
4206 
    .en  (pstate_priv_update_g[2]),
4207 
    .clk (clk),
4208 
    .se  (se),
4209 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4210 95 fafa1971 
    .so  ()
4211 
);
4212 
//
4213 
// modified for hypervisor support
4214 
assign restore_pstate2[11:10] = 2'b0;
4215 
assign restore_pstate2[0]     = 1'b0;
4216 
// modified to reflect the physical implementation
4217 
// restructing the hpstate for done/retry instructions
4218 
//
4219 
assign hpstate_dnrtry_priv_w2[2] =
4220 
           (true_hpstate2[`HPSTATE_ENB])?
4221 
            tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV] :
4222 
            dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV];
4223 
*/
4224 
mux2ds mx_hpstate_dnrtry_priv_w2_2 (
4225 113 albert.wat 
       .in0  (tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV]),
4226 
           .in1  (dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV]),
4227 
       .sel0 (true_hpstate2[`HPSTATE_ENB]),
4228 
           .sel1 (~true_hpstate2[`HPSTATE_ENB]),
4229 95 fafa1971 
       .dout (hpstate_dnrtry_priv_w2[2])
4230 
);
4231 
//
4232 113 albert.wat 
assign dnrtry_hpstate2_w2[`TLU_HPSTATE_WIDTH-1:0] =
4233 
       {tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1],
4234 
        true_hpstate2[`HPSTATE_ENB],
4235 
        tsa_dnrtry_hpstate_w2[`HPSTATE_RED],
4236 95 fafa1971 
        hpstate_dnrtry_priv_w2[2],
4237 113 albert.wat 
        tsa_dnrtry_hpstate_w2[`HPSTATE_TLZ]};
4238 95 fafa1971 
//
4239 
// constructing the hpstate for hyper-privileged traps
4240 
//
4241 113 albert.wat 
assign hntrap_hpstate2_w2[`TLU_HPSTATE_WIDTH-1:0] =
4242 95 fafa1971 
       {hpstate_ibe_set[2],
4243 
        hpstate_enb_set[2],
4244 
        hpstate_redmode,  // Redmode bit
4245 
        hpstate_priv_set, // hyper-privileged bit
4246 
        hpstate_tlz_set[2]}; // TLZ interrupt bit
4247 
//
4248 
assign tlu_hpstate_hnt_sel2 =
4249 
       ~(tlu_hpstate_din_sel2[0] | tlu_hpstate_wsr_sel2);
4250 
//
4251 
assign tlu_hpstate_wsr_sel2 =
4252 
           tlu_hpstate_din_sel2[1] |
4253 113 albert.wat 
           (~true_hpstate2[`HPSTATE_ENB] & tlu_pstate_din_sel2[1]);
4254 95 fafa1971 
 
4255 113 albert.wat 
mux3ds #(`TLU_HPSTATE_WIDTH) mux_restore_hpstate2 (
4256 
       .in0  (dnrtry_hpstate2_w2[`TLU_HPSTATE_WIDTH-1:0]),
4257 
           .in1  (wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0]),
4258 
           .in2  (hntrap_hpstate2_w2[`TLU_HPSTATE_WIDTH-1:0]),
4259 95 fafa1971 
       .sel0 (tlu_hpstate_din_sel2[0]),
4260 
           .sel1 (tlu_hpstate_wsr_sel2),
4261 
           .sel2 (tlu_hpstate_hnt_sel2),
4262 113 albert.wat 
       .dout (restore_hpstate2[`TLU_HPSTATE_WIDTH-1:0])
4263 95 fafa1971 
);
4264 
//
4265 
// need to initialize hpstate.enb = 0
4266 
// need to initialize hpstate.ibe = 0
4267 
// modified due to the addition of hpstate.ibe
4268 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
4269 
dffre_s #(2) dffr_true_hpst2_enb_ibe (
4270 
    .din (restore_hpstate2[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4271 
        .q   (true_hpstate2[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4272 95 fafa1971 
    .rst (local_rst),
4273 
    .en (~(tlu_update_hpstate_l_w2[2])), .clk(clk),
4274 
    .se  (se),
4275 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4276 95 fafa1971 
    .so  ()
4277 
);
4278 113 albert.wat 
`else
4279 
dffr_s #(2) dffr_true_hpst2_enb_ibe (
4280 
    .din (restore_hpstate2[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4281 
        .q   (true_hpstate2[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4282 
    .rst (local_rst),
4283 
    .clk (hpstate2_clk),
4284 
    .se  (se),
4285 
    `SIMPLY_RISC_SCANIN,
4286 
    .so  ()
4287 
);
4288 
`endif
4289 95 fafa1971 
//
4290 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
4291 
dffe_s #(2) dff_true_hpstate2 (
4292 
    .din ({restore_hpstate2[`HPSTATE_RED],
4293 
           restore_hpstate2[`HPSTATE_TLZ]}),
4294 
    .q   ({true_hpstate2[`HPSTATE_RED],
4295 
           true_hpstate2[`HPSTATE_TLZ]}),
4296 95 fafa1971 
    .en (~(tlu_update_hpstate_l_w2[2])), .clk(clk),
4297 
    .se  (se),
4298 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4299 95 fafa1971 
    .so  ()
4300 
);
4301 113 albert.wat 
`else
4302 
dff_s #(2) dff_true_hpstate2 (
4303 
    .din ({restore_hpstate2[`HPSTATE_RED],
4304 
           restore_hpstate2[`HPSTATE_TLZ]}),
4305 
    .q   ({true_hpstate2[`HPSTATE_RED],
4306 
           true_hpstate2[`HPSTATE_TLZ]}),
4307 
    .clk (hpstate2_clk),
4308 
    .se  (se),
4309 
    `SIMPLY_RISC_SCANIN,
4310 
    .so  ()
4311 
);
4312 
`endif
4313 95 fafa1971 
//
4314 113 albert.wat 
dffe_s dffe_hpstate2_priv (
4315 
    .din (restore_hpstate2[`HPSTATE_PRIV]),
4316 
    .q   (true_hpstate2[`HPSTATE_PRIV]),
4317 95 fafa1971 
    .en  (hpstate_priv_update_w2[2]),
4318 
    .clk (clk),
4319 
    .se  (se),
4320 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4321 95 fafa1971 
    .so  ()
4322 
);
4323 
 
4324 113 albert.wat 
assign tlu_ifu_pstate_pef[2]   = true_pstate2[`PSTATE_PEF];
4325 
assign tlu_lsu_pstate_cle[2]   = true_pstate2[`PSTATE_CLE];
4326 
assign tlu_lsu_pstate_priv[2]  = true_pstate2[`PSTATE_PRIV];
4327 
assign tlu_int_pstate_ie[2]    = true_pstate2[`PSTATE_IE];
4328 
assign local_pstate_ie[2]      = true_pstate2[`PSTATE_IE];
4329 95 fafa1971 
// assign tlu_pstate_cle[2]        = true_pstate2[`PSTATE_CLE];
4330 113 albert.wat 
assign tlu_pstate_tle[2]           = true_pstate2[`PSTATE_TLE];
4331 95 fafa1971 
// assign tlu_pstate_priv[2]       = true_pstate2[`PSTATE_PRIV];
4332 113 albert.wat 
assign local_pstate_priv[2]    = true_pstate2[`PSTATE_PRIV];
4333 
assign tlu_pstate_am[2]            = true_pstate2[`PSTATE_AM];
4334 95 fafa1971 
// assign tlu_pstate2_mmodel[1:0] = true_pstate2[`PSTATE_MM_HI:`PSTATE_MM_LO];
4335 
//
4336 
// modified for hypervisor support
4337 
// assign       tlu_int_redmode[2]      = true_pstate2[`PSTATE_RED];
4338 113 albert.wat 
assign tlu_int_redmode[2] = true_hpstate2[`HPSTATE_RED];
4339 
assign tlu_lsu_redmode[2] = true_hpstate2[`HPSTATE_RED];
4340 95 fafa1971 
//
4341 
// hypervisor privilege indicator
4342 113 albert.wat 
assign tlu_hpstate_priv[2]   = true_hpstate2[`HPSTATE_PRIV];
4343 
assign local_hpstate_priv[2] = true_hpstate2[`HPSTATE_PRIV];
4344 
assign tcl_hpstate_priv[2]   = true_hpstate2[`HPSTATE_PRIV];
4345 95 fafa1971 
//
4346 
// hypervisor lite mode selector
4347 113 albert.wat 
assign tlu_hpstate_enb[2]   = true_hpstate2[`HPSTATE_ENB];
4348 
assign local_hpstate_enb[2] = true_hpstate2[`HPSTATE_ENB];
4349 
assign tcl_hpstate_enb[2]   = true_hpstate2[`HPSTATE_ENB];
4350 95 fafa1971 
 
4351 
// hypervisor tlz indicator
4352 113 albert.wat 
assign tlu_hpstate_tlz[2] = true_hpstate2[`HPSTATE_TLZ];
4353 95 fafa1971 
 
4354 
// hypervisor instruction breakpt enable
4355 113 albert.wat 
assign tlu_hpstate_ibe[2] = true_hpstate2[`HPSTATE_IBE];
4356 95 fafa1971 
 
4357 
// THREAD3
4358 
// added for bug 1575
4359 
// modified for bug 2584
4360 
// assign tlu_pstate_nt_sel3 = ~|(tlu_pstate_din_sel3[1:0]);
4361 
assign tlu_pstate_nt_sel3 =
4362 
          ~(tlu_pstate_din_sel3[0] | tlu_pstate_wsr_sel3);
4363 
//
4364 
// modified for bug 3349
4365 
assign tlu_pstate_wsr_sel3 =
4366 
           tlu_pstate_din_sel3[1] |
4367 113 albert.wat 
           (~(true_hpstate3[`HPSTATE_ENB] & wsr_data_w2[`WSR_HPSTATE_ENB]) &
4368 95 fafa1971 
              tlu_hpstate_din_sel3[1]);
4369 
//            (~true_hpstate3[`HPSTATE_ENB] & tlu_hpstate_din_sel3[1]);
4370 
//
4371 113 albert.wat 
mux3ds #(`WSR_PSTATE_VR_WIDTH) mux_restore_pstate3(
4372 
       .in0  (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
4373 
           .in1  (wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
4374 
           .in2  (ntrap_pstate3[`WSR_PSTATE_VR_WIDTH-1:0]),
4375 95 fafa1971 
       .sel0 (tlu_pstate_din_sel3[0]),
4376 
           .sel1 (tlu_pstate_wsr_sel3),
4377 
           .sel2 (tlu_pstate_nt_sel3),
4378 113 albert.wat 
       .dout (restore_pstate3[`WSR_PSTATE_VR_WIDTH-1:0])
4379 95 fafa1971 
);
4380 
 
4381 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
4382 
dffe_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate3_w3 (
4383 
    .din ({restore_pstate3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
4384 
           restore_pstate3[`WSR_PSTATE_VRANGE1_LO]}),
4385 
    .q   ({restore_pstate3_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
4386 
           restore_pstate3_w3[`WSR_PSTATE_VRANGE1_LO]}),
4387 95 fafa1971 
    .en (~(tlu_update_pstate_l_w2[3])), .clk(clk),
4388 
    .se  (se),
4389 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4390 95 fafa1971 
    .so  ()
4391 
);
4392 113 albert.wat 
`else
4393 
dff_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate3_w3 (
4394 
    .din ({restore_pstate3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
4395 
           restore_pstate3[`WSR_PSTATE_VRANGE1_LO]}),
4396 
    .q   ({restore_pstate3_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
4397 
           restore_pstate3_w3[`WSR_PSTATE_VRANGE1_LO]}),
4398 
    .clk (pstate3_clk),
4399 
    .se  (se),
4400 
    `SIMPLY_RISC_SCANIN,
4401 
    .so  ()
4402 
);
4403 
`endif
4404 95 fafa1971 
//
4405 113 albert.wat 
dffe_s dffe_pstate3_priv (
4406 
    .din (restore_pstate3[`WSR_PSTATE_VR_PRIV]),
4407 
    .q   (restore_pstate3_w3[`WSR_PSTATE_VR_PRIV]),
4408 95 fafa1971 
    .en  (pstate_priv_update_w2[3]),
4409 
    .clk (clk),
4410 
    .se  (se),
4411 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4412 95 fafa1971 
    .so  ()
4413 
);
4414 
//
4415 
// true_pstate3 assignments
4416 113 albert.wat 
assign true_pstate3[`PSTATE_TRUE_WIDTH-1:0] =
4417 95 fafa1971 
           {2'b0, // tlu_select_int_global - replaced by gl register
4418 
                  // tlu_select_mmu_global - replaced by gl register
4419 113 albert.wat 
            restore_pstate3_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE2_LO],
4420 95 fafa1971 
            2'b0, // fixed mmodel - TSO
4421 
            1'b0, // redmode - replaced by hpstate.red
4422 113 albert.wat 
            restore_pstate3_w3[`WSR_PSTATE_VRANGE1_HI:`WSR_PSTATE_VRANGE1_LO],
4423 95 fafa1971 
            1'b0}; // tlu_select_alt_global - replaced by gl register
4424 
//
4425 
// modified for timing
4426 
/*
4427 
mux3ds #(9) mux_restore_pstate3(
4428 
       .in0  (dnrtry_pstate[`PSTATE_TRUE_WIDTH-3:1]),
4429 
           .in1  (wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-3:1]),
4430 
           .in2  (ntrap_pstate3[`PSTATE_TRUE_WIDTH-3:1]),
4431 
       .sel0 (tlu_pstate_din_sel3[0]),
4432 
       // modified for bug 2584
4433 
           // .sel1 (tlu_pstate_din_sel3[1]),
4434 
           .sel1 (tlu_pstate_wsr_sel3),
4435 
           .sel2 (tlu_pstate_nt_sel3),
4436 
       .dout (restore_pstate3[`PSTATE_TRUE_WIDTH-3:1])
4437 
);
4438 
//
4439 
`ifdef FPGA_SYN_CLK_DFF
4440 113 albert.wat 
dffe_s #(`PSTATE_TRUE_WIDTH) pstate3_1 (
4441 95 fafa1971 
    .din (restore_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
4442 
        .q   (true_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
4443 
    .en (~(tlu_update_pstate_l_w2[3])), .clk(clk),
4444 
    .se  (se),
4445 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4446 95 fafa1971 
    .so  ()
4447 
);
4448 
`else
4449 113 albert.wat 
dff_s #(`PSTATE_TRUE_WIDTH) pstate3_1 (
4450 95 fafa1971 
    .din (restore_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
4451 
        .q   (true_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
4452 
    .clk (pstate3_clk),
4453 
    .se  (se),
4454 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4455 95 fafa1971 
    .so  ()
4456 
);
4457 
`endif
4458 
//
4459 
`ifdef FPGA_SYN_CLK_DFF
4460 113 albert.wat 
dffe_s #(`PSTATE_TRUE_WIDTH-1) pstate3_1 (
4461 95 fafa1971 
    .din ({restore_pstate3[`PSTATE_TRUE_WIDTH-1:3],
4462 
           restore_pstate3[1:0]}),
4463 
    .q   ({true_pstate3[`PSTATE_TRUE_WIDTH-1:3],
4464 
           true_pstate3[1:0]}),
4465 
    .en (~(tlu_update_pstate_l_w2[3])), .clk(clk),
4466 
    .se  (se),
4467 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4468 95 fafa1971 
    .so  ()
4469 
);
4470 
`else
4471 113 albert.wat 
dff_s #(`PSTATE_TRUE_WIDTH-1) pstate3_1 (
4472 95 fafa1971 
    .din ({restore_pstate3[`PSTATE_TRUE_WIDTH-1:3],
4473 
           restore_pstate3[1:0]}),
4474 
    .q   ({true_pstate3[`PSTATE_TRUE_WIDTH-1:3],
4475 
           true_pstate3[1:0]}),
4476 
    .clk (pstate3_clk),
4477 
    .se  (se),
4478 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4479 95 fafa1971 
    .so  ()
4480 
);
4481 
`endif
4482 
//
4483 113 albert.wat 
dffe_s dffe_pstate3_priv (
4484 95 fafa1971 
    .din (restore_pstate3[`PSTATE_PRIV]),
4485 
    .q   (true_pstate3[`PSTATE_PRIV]),
4486 
    .en  (pstate_priv_update_g[3]),
4487 
    .clk (clk),
4488 
    .se  (se),
4489 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4490 95 fafa1971 
    .so  ()
4491 
);
4492 
//
4493 
// modified for hypervisor support
4494 
assign restore_pstate3[11:10] = 2'b0;
4495 
assign restore_pstate3[0]     = 1'b0;
4496 
//
4497 
// modified to reflect the physical implementation
4498 
assign hpstate_dnrtry_priv_w2[3] =
4499 
           (true_hpstate3[`HPSTATE_ENB])?
4500 
            tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV] :
4501 
            dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV];
4502 
*/
4503 
mux2ds mx_hpstate_dnrtry_priv_w2_3 (
4504 113 albert.wat 
       .in0  (tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV]),
4505 
           .in1  (dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV]),
4506 
       .sel0 (true_hpstate3[`HPSTATE_ENB]),
4507 
           .sel1 (~true_hpstate3[`HPSTATE_ENB]),
4508 95 fafa1971 
       .dout (hpstate_dnrtry_priv_w2[3])
4509 
);
4510 
//
4511 113 albert.wat 
assign dnrtry_hpstate3_w2[`TLU_HPSTATE_WIDTH-1:0] =
4512 
       {tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1],
4513 
        true_hpstate3[`HPSTATE_ENB],
4514 
        tsa_dnrtry_hpstate_w2[`HPSTATE_RED],
4515 95 fafa1971 
        hpstate_dnrtry_priv_w2[3],
4516 113 albert.wat 
        tsa_dnrtry_hpstate_w2[`HPSTATE_TLZ]};
4517 95 fafa1971 
//
4518 
// constructing the hpstate for hyper-privileged traps
4519 
//
4520 113 albert.wat 
assign hntrap_hpstate3_w2[`TLU_HPSTATE_WIDTH-1:0] =
4521 95 fafa1971 
       {hpstate_ibe_set[3],
4522 
        hpstate_enb_set[3],
4523 
        hpstate_redmode,  // Redmode bit
4524 
        hpstate_priv_set, // hyper-privileged bit
4525 
        hpstate_tlz_set[3]}; // TLZ interrupt bit
4526 
 
4527 
assign tlu_hpstate_hnt_sel3 =
4528 
       ~(tlu_hpstate_din_sel3[0] | tlu_hpstate_wsr_sel3);
4529 
//
4530 
assign tlu_hpstate_wsr_sel3 =
4531 
           tlu_hpstate_din_sel3[1] |
4532 113 albert.wat 
           (~true_hpstate3[`HPSTATE_ENB] & tlu_pstate_din_sel3[1]);
4533 95 fafa1971 
 
4534 113 albert.wat 
mux3ds #(`TLU_HPSTATE_WIDTH) mux_restore_hpstate3 (
4535 
       .in0  (dnrtry_hpstate3_w2[`TLU_HPSTATE_WIDTH-1:0]),
4536 
           .in1  (wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0]),
4537 
           .in2  (hntrap_hpstate3_w2[`TLU_HPSTATE_WIDTH-1:0]),
4538 95 fafa1971 
       .sel0 (tlu_hpstate_din_sel3[0]),
4539 
           .sel1 (tlu_hpstate_wsr_sel3),
4540 
           .sel2 (tlu_hpstate_hnt_sel3),
4541 113 albert.wat 
       .dout (restore_hpstate3[`TLU_HPSTATE_WIDTH-1:0])
4542 95 fafa1971 
);
4543 
//
4544 
// need to initialize hpstate.enb = 0
4545 
// need to initialize hpstate.ibe = 0
4546 
// modified due to the addition of hpstate.ibe
4547 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
4548 
dffre_s #(2) dffr_true_hpst3_enb_ibe (
4549 
    .din (restore_hpstate3[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4550 
        .q   (true_hpstate3[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4551 95 fafa1971 
    .rst (local_rst),
4552 
    .en (~(tlu_update_hpstate_l_w2[3])), .clk(clk),
4553 
    .se  (se),
4554 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4555 95 fafa1971 
    .so  ()
4556 
);
4557 113 albert.wat 
`else
4558 
dffr_s #(2) dffr_true_hpst3_enb_ibe (
4559 
    .din (restore_hpstate3[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4560 
        .q   (true_hpstate3[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
4561 
    .rst (local_rst),
4562 
    .clk (hpstate3_clk),
4563 
    .se  (se),
4564 
    `SIMPLY_RISC_SCANIN,
4565 
    .so  ()
4566 
);
4567 
`endif
4568 95 fafa1971 
//
4569 
//
4570 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
4571 
dffe_s #(2) dff_true_hpstate3 (
4572 
    .din ({restore_hpstate3[`HPSTATE_RED],
4573 
           restore_hpstate3[`HPSTATE_TLZ]}),
4574 
    .q   ({true_hpstate3[`HPSTATE_RED],
4575 
           true_hpstate3[`HPSTATE_TLZ]}),
4576 95 fafa1971 
    .en (~(tlu_update_hpstate_l_w2[3])), .clk(clk),
4577 
    .se  (se),
4578 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4579 95 fafa1971 
    .so  ()
4580 
);
4581 113 albert.wat 
`else
4582 
dff_s #(2) dff_true_hpstate3 (
4583 
    .din ({restore_hpstate3[`HPSTATE_RED],
4584 
           restore_hpstate3[`HPSTATE_TLZ]}),
4585 
    .q   ({true_hpstate3[`HPSTATE_RED],
4586 
           true_hpstate3[`HPSTATE_TLZ]}),
4587 
    .clk (hpstate3_clk),
4588 
    .se  (se),
4589 
    `SIMPLY_RISC_SCANIN,
4590 
    .so  ()
4591 
);
4592 
`endif
4593 95 fafa1971 
//
4594 113 albert.wat 
dffe_s dffe_hpstate3_priv (
4595 
    .din (restore_hpstate3[`HPSTATE_PRIV]),
4596 
    .q   (true_hpstate3[`HPSTATE_PRIV]),
4597 95 fafa1971 
    .en  (hpstate_priv_update_w2[3]),
4598 
    .clk (clk),
4599 
    .se  (se),
4600 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4601 95 fafa1971 
    .so  ()
4602 
);
4603 
 
4604 113 albert.wat 
assign tlu_ifu_pstate_pef[3]   = true_pstate3[`PSTATE_PEF];
4605 
assign tlu_lsu_pstate_cle[3]   = true_pstate3[`PSTATE_CLE];
4606 
assign tlu_lsu_pstate_priv[3]  = true_pstate3[`PSTATE_PRIV];
4607 
assign tlu_int_pstate_ie[3]    = true_pstate3[`PSTATE_IE];
4608 
assign local_pstate_ie[3]      = true_pstate3[`PSTATE_IE];
4609 95 fafa1971 
// assign tlu_pstate_cle[3]        = true_pstate3[`PSTATE_CLE];
4610 113 albert.wat 
assign tlu_pstate_tle[3]           = true_pstate3[`PSTATE_TLE];
4611 95 fafa1971 
// assign tlu_pstate_priv[3]       = true_pstate3[`PSTATE_PRIV];
4612 113 albert.wat 
assign local_pstate_priv[3]    = true_pstate3[`PSTATE_PRIV];
4613 
assign tlu_pstate_am[3]            = true_pstate3[`PSTATE_AM];
4614 95 fafa1971 
// assign tlu_pstate3_mmodel[1:0] = true_pstate3[`PSTATE_MM_HI:`PSTATE_MM_LO];
4615 
//
4616 
// modified for hypervisor support
4617 
// assign       tlu_int_redmode[3]      = true_pstate3[`PSTATE_RED];
4618 113 albert.wat 
assign tlu_int_redmode[3] = true_hpstate3[`HPSTATE_RED];
4619 
assign tlu_lsu_redmode[3] = true_hpstate3[`HPSTATE_RED];
4620 95 fafa1971 
//
4621 
// hypervisor privilege indicator
4622 113 albert.wat 
assign tlu_hpstate_priv[3]   = true_hpstate3[`HPSTATE_PRIV];
4623 
assign local_hpstate_priv[3] = true_hpstate3[`HPSTATE_PRIV];
4624 
assign tcl_hpstate_priv[3]   = true_hpstate3[`HPSTATE_PRIV];
4625 95 fafa1971 
//
4626 
// hypervisor lite mode selector
4627 113 albert.wat 
assign tlu_hpstate_enb[3]   = true_hpstate3[`HPSTATE_ENB];
4628 
assign local_hpstate_enb[3] = true_hpstate3[`HPSTATE_ENB];
4629 
assign tcl_hpstate_enb[3]   = true_hpstate3[`HPSTATE_ENB];
4630 95 fafa1971 
 
4631 
// hypervisor tlz indicator
4632 113 albert.wat 
assign tlu_hpstate_tlz[3] = true_hpstate3[`HPSTATE_TLZ];
4633 95 fafa1971 
 
4634 
// hypervisor instruction breakpt enable
4635 113 albert.wat 
assign tlu_hpstate_ibe[3] = true_hpstate3[`HPSTATE_IBE];
4636 95 fafa1971 
 
4637 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
4638 95 fafa1971 
 
4639 
// Mux to choose the pstate register to read base on thread
4640 113 albert.wat 
wire [`PSTATE_TRUE_WIDTH-1:0] pstate_rdata;
4641 
wire [`RDSR_HPSTATE_WIDTH-1:0] hpstate_rdata;
4642 95 fafa1971 
 
4643 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
4644 
   assign       pstate_rdata[`PSTATE_TRUE_WIDTH-1:0] = true_pstate0[`PSTATE_TRUE_WIDTH-1:0];
4645 
   assign       true_hpstate[`TLU_HPSTATE_WIDTH-1:0] = true_hpstate0[`TLU_HPSTATE_WIDTH-1:0];
4646 
`else
4647 95 fafa1971 
 
4648 
mux4ds #(12) pstate_mx_sel (
4649 113 albert.wat 
       .in0  (true_pstate0[`PSTATE_TRUE_WIDTH-1:0]),
4650 
       .in1  (true_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
4651 
       .in2  (true_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
4652 
       .in3  (true_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
4653 95 fafa1971 
       .sel0 (tlu_thrd_rsel_e[0]),
4654 
       .sel1 (tlu_thrd_rsel_e[1]),
4655 
       .sel2 (tlu_thrd_rsel_e[2]),
4656 
       .sel3 (tlu_thrd_rsel_e[3]),
4657 113 albert.wat 
       .dout (pstate_rdata[`PSTATE_TRUE_WIDTH-1:0])
4658 95 fafa1971 
);
4659 
//
4660 
// added for hypervisor support
4661 
// mux to choose the pstate register to read base on thread
4662 
 
4663 113 albert.wat 
mux4ds #(`TLU_HPSTATE_WIDTH) hpstate_mx_sel (
4664 
       .in0  (true_hpstate0[`TLU_HPSTATE_WIDTH-1:0]),
4665 
       .in1  (true_hpstate1[`TLU_HPSTATE_WIDTH-1:0]),
4666 
       .in2  (true_hpstate2[`TLU_HPSTATE_WIDTH-1:0]),
4667 
       .in3  (true_hpstate3[`TLU_HPSTATE_WIDTH-1:0]),
4668 95 fafa1971 
       .sel0 (tlu_thrd_rsel_e[0]),
4669 
       .sel1 (tlu_thrd_rsel_e[1]),
4670 
       .sel2 (tlu_thrd_rsel_e[2]),
4671 
       .sel3 (tlu_thrd_rsel_e[3]),
4672 113 albert.wat 
       .dout (true_hpstate[`TLU_HPSTATE_WIDTH-1:0])
4673 95 fafa1971 
);
4674 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
4675 95 fafa1971 
 
4676 
//
4677 
// assigned the stored hpstate bits to the ASR positions
4678 
//
4679 113 albert.wat 
assign hpstate_rdata[`WSR_HPSTATE_ENB]  = true_hpstate[`HPSTATE_ENB];
4680 
assign hpstate_rdata[`WSR_HPSTATE_IBE]  = true_hpstate[`HPSTATE_IBE];
4681 
assign hpstate_rdata[`WSR_HPSTATE_RED]  = true_hpstate[`HPSTATE_RED];
4682 
assign hpstate_rdata[`WSR_HPSTATE_PRIV] = true_hpstate[`HPSTATE_PRIV];
4683 
assign hpstate_rdata[`WSR_HPSTATE_TLZ]  = true_hpstate[`HPSTATE_TLZ];
4684 95 fafa1971 
//
4685 
// grounding the reserved bits
4686 
// modified due to the addition of hpstate.ibe
4687 
// assign hpstate_rdata[`WSR_HPSTATE_ENB-1 :`WSR_HPSTATE_RED+1]  = 5'h00;
4688 113 albert.wat 
assign hpstate_rdata[`WSR_HPSTATE_IBE-1 :`WSR_HPSTATE_RED+1]  = 4'h0;
4689 
assign hpstate_rdata[`WSR_HPSTATE_RED-1 :`WSR_HPSTATE_PRIV+1] = 2'b00;
4690 
assign hpstate_rdata[`WSR_HPSTATE_PRIV-1:`WSR_HPSTATE_TLZ+1]  = 1'b0;
4691 95 fafa1971 
//
4692 
// constructing data for htstate
4693 
//
4694 113 albert.wat 
wire [`RDSR_HPSTATE_WIDTH-1:0] htstate_rdata;
4695 95 fafa1971 
 
4696 
// assign htstate_rdata[`WSR_HPSTATE_RED]  = tsa_rdata[`TLU_HTSTATE_HI];
4697 
// assign htstate_rdata[`WSR_HPSTATE_PRIV] = tsa_rdata[`TLU_HTSTATE_HI-1];
4698 
/* modified due to logic redistribution
4699 
assign htstate_rdata[`WSR_HPSTATE_IBE]  = tsa_rdata[`TLU_HTSTATE_HI];
4700 
assign htstate_rdata[`WSR_HPSTATE_RED]  = tsa_rdata[`TLU_HTSTATE_HI-1];
4701 
assign htstate_rdata[`WSR_HPSTATE_PRIV] = tsa_rdata[`TLU_HTSTATE_HI-2];
4702 
assign htstate_rdata[`WSR_HPSTATE_TLZ]  = tsa_rdata[`TLU_HTSTATE_LO];
4703 
*/
4704 113 albert.wat 
assign htstate_rdata[`WSR_HPSTATE_IBE]  = tsa_rdata[`TLU_RD_HTSTATE_HI];
4705 
assign htstate_rdata[`WSR_HPSTATE_RED]  = tsa_rdata[`TLU_RD_HTSTATE_HI-1];
4706 
assign htstate_rdata[`WSR_HPSTATE_PRIV] = tsa_rdata[`TLU_RD_HTSTATE_HI-2];
4707 
assign htstate_rdata[`WSR_HPSTATE_TLZ]  = tsa_rdata[`TLU_RD_HTSTATE_LO];
4708 95 fafa1971 
//
4709 
// grounding the reserved bits
4710 
// modified due to addition of hpstate.ibe
4711 
// assign htstate_rdata[`RDSR_HPSTATE_WIDTH-1 :`WSR_HPSTATE_RED+1] = 6'h00;
4712 113 albert.wat 
assign htstate_rdata[`RDSR_HPSTATE_WIDTH-1] = 1'b0;
4713 
assign htstate_rdata[`WSR_HPSTATE_IBE-1 :`WSR_HPSTATE_RED+1]  = 4'h0;
4714 
assign htstate_rdata[`WSR_HPSTATE_RED-1 :`WSR_HPSTATE_PRIV+1] = 2'b00;
4715 
assign htstate_rdata[`WSR_HPSTATE_PRIV-1:`WSR_HPSTATE_TLZ+1]  = 1'b0;
4716 95 fafa1971 
 
4717 
//=========================================================================================
4718 
//      RDPR - This section has been recoded due to timing
4719 
//=========================================================================================
4720 
 
4721 
// mux data width - 2b
4722 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
4723 
   assign global_rdata[`TSA_GLOBAL_WIDTH-1:0] = tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0];
4724 
   assign hintp_rdata = tlu_hintp[0];
4725 
`else
4726 95 fafa1971 
 
4727 
 
4728 113 albert.wat 
mux4ds #(`TSA_GLOBAL_WIDTH) mux_global_rdata (
4729 
       .in0  (tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0]),
4730 
       .in1  (tlu_gl_lvl1[`TSA_GLOBAL_WIDTH-1:0]),
4731 
       .in2  (tlu_gl_lvl2[`TSA_GLOBAL_WIDTH-1:0]),
4732 
       .in3  (tlu_gl_lvl3[`TSA_GLOBAL_WIDTH-1:0]),
4733 95 fafa1971 
       .sel0 (tlu_thrd_rsel_e[0]),
4734 
       .sel1 (tlu_thrd_rsel_e[1]),
4735 
       .sel2 (tlu_thrd_rsel_e[2]),
4736 
       .sel3 (tlu_thrd_rsel_e[3]),
4737 113 albert.wat 
       .dout (global_rdata[`TSA_GLOBAL_WIDTH-1:0])
4738 95 fafa1971 
);
4739 
//
4740 
// htickcmp interrupt enable
4741 
//
4742 
mux4ds #(1) mux_hintp_rdata (
4743 
        .in0    (tlu_hintp[0]),
4744 
        .in1    (tlu_hintp[1]),
4745 
        .in2    (tlu_hintp[2]),
4746 
        .in3    (tlu_hintp[3]),
4747 
        .sel0   (tlu_thrd_rsel_e[0]),
4748 
        .sel1   (tlu_thrd_rsel_e[1]),
4749 
        .sel2   (tlu_thrd_rsel_e[2]),
4750 
        .sel3   (tlu_thrd_rsel_e[3]),
4751 
        .dout   (hintp_rdata)
4752 
);
4753 113 albert.wat 
`endif // !`ifdef FPGA_SYN_1THREAD
4754 95 fafa1971 
 
4755 
//
4756 
// tstate.gl - 2b
4757 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_GL_HI:`WSR_TSTATE_GL_LO] =
4758 
       tsa_rdata[`TLU_GL_HI:`TLU_GL_LO];
4759 95 fafa1971 
//
4760 
// tstate.ccr - 8b
4761 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_CCR_HI:`WSR_TSTATE_CCR_LO] =
4762 
       tsa_rdata[`TLU_CCR_HI:`TLU_CCR_LO];
4763 95 fafa1971 
//
4764 
// tstate.asi - 8b
4765 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_ASI_HI:`WSR_TSTATE_ASI_LO] =
4766 
       tsa_rdata[`TLU_ASI_HI:`TLU_ASI_LO];
4767 95 fafa1971 
//
4768 
// tstate.pstate(valid range 2) - 2b
4769 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_PS2_HI:`WSR_TSTATE_PS2_LO] =
4770 
       tsa_rdata[`TSA_PSTATE_VRANGE2_HI:`TSA_PSTATE_VRANGE2_LO];
4771 95 fafa1971 
//
4772 
// added for to please lint
4773 
assign tstate_dummy_zero[1:0] =
4774 113 albert.wat 
       tsa_rdata[`TSA_PSTATE_VRANGE2_LO-1:`TSA_PSTATE_VRANGE1_HI+1] & 2'b0;
4775 95 fafa1971 
//
4776 
// tstate.pstate(valid range 1) - 4b
4777 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_PS1_HI:`WSR_TSTATE_PS1_LO] =
4778 
       tsa_rdata[`TSA_PSTATE_VRANGE1_HI:`TSA_PSTATE_VRANGE1_LO];
4779 95 fafa1971 
//
4780 
// tstate.cwp - 3b
4781 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_CWP_HI:`WSR_TSTATE_CWP_LO] =
4782 
       tsa_rdata[`TLU_CWP_HI:`TLU_CWP_LO];
4783 95 fafa1971 
//
4784 
// reserved bits with ASR - assign to  1'b0
4785 113 albert.wat 
assign tstate_rdata[`RDSR_TSTATE_WIDTH-1:`WSR_TSTATE_GL_HI+1] =
4786 95 fafa1971 
       6'h00;
4787 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_ASI_LO-1:`WSR_TSTATE_PS2_HI+1] =
4788 95 fafa1971 
       6'h00;
4789 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_PS2_LO-1:`WSR_TSTATE_PS1_HI+1] =
4790 95 fafa1971 
       {1'b0, tstate_dummy_zero[1:0]};
4791 113 albert.wat 
assign tstate_rdata[`WSR_TSTATE_PS1_LO-1:`WSR_TSTATE_CWP_HI+1] =
4792 95 fafa1971 
       6'h00;
4793 
//
4794 
//============================================================================
4795 
// new rdpr mux coding due to timing changes
4796 
//============================================================================
4797 
//
4798 
// added for bug 2332
4799 
assign rdpr_mx1_onehot_sel =
4800 
           ~(|tlu_rdpr_mx1_sel[3:1]);
4801 
// mux1- 64b
4802 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH) rdpr_mx1(
4803 95 fafa1971 
        .in0({tlu_tick_npt,true_tick[60:0], 2'b0}),
4804 113 albert.wat 
        .in1(tickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0]),
4805 
        .in2(stickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0]),
4806 
        .in3({tlu_htickcmp_intdis,htickcmp_rdata[`TLU_ASR_DATA_WIDTH-2:0]}),
4807 95 fafa1971 
        .sel0(rdpr_mx1_onehot_sel),
4808 
        .sel1(tlu_rdpr_mx1_sel[1]),
4809 
        .sel2(tlu_rdpr_mx1_sel[2]),
4810 
        .sel3(tlu_rdpr_mx1_sel[3]),
4811 113 albert.wat 
        .dout(tlu_rdpr_mx1_out[`TLU_ASR_DATA_WIDTH-1:0])
4812 95 fafa1971 
);
4813 
//
4814 
//
4815 
// added for bug 2332
4816 
assign rdpr_mx2_onehot_sel =
4817 
           ~(|tlu_rdpr_mx2_sel[3:1]);
4818 
//
4819 
// mux2 - 4b
4820 
mux4ds #(4) rdpr_mx2(
4821 113 albert.wat 
        .in0({2'b0,global_rdata[`TSA_GLOBAL_WIDTH-1:0]}),
4822 95 fafa1971 
        .in1({3'b0,hintp_rdata}),
4823 
        .in2({1'b0,tlu_trp_lvl[2:0]}),
4824 
        .in3(tlu_pil[3:0]),
4825 
        .sel0(rdpr_mx2_onehot_sel),
4826 
        .sel1(tlu_rdpr_mx2_sel[1]),
4827 
        .sel2(tlu_rdpr_mx2_sel[2]),
4828 
        .sel3(tlu_rdpr_mx2_sel[3]),
4829 
        .dout(tlu_rdpr_mx2_out[3:0])
4830 
);
4831 
//
4832 
// added for bug 2332
4833 
assign rdpr_mx3_onehot_sel =
4834 
           ~(|tlu_rdpr_mx3_sel[2:1]);
4835 
//
4836 
// mux3 - 17b
4837 113 albert.wat 
mux3ds #(`SFTINT_WIDTH) rdpr_mx3(
4838 
        .in0(sftint_rdata[`SFTINT_WIDTH-1:0]),
4839 
        .in1({5'b0,pstate_rdata[`PSTATE_TRUE_WIDTH-1:0]}),
4840 
        .in2({5'b0,hpstate_rdata[`RDSR_HPSTATE_WIDTH-1:0]}),
4841 95 fafa1971 
        .sel0(rdpr_mx3_onehot_sel),
4842 
        .sel1(tlu_rdpr_mx3_sel[1]),
4843 
        .sel2(tlu_rdpr_mx3_sel[2]),
4844 113 albert.wat 
        .dout(tlu_rdpr_mx3_out[`SFTINT_WIDTH-1:0])
4845 95 fafa1971 
);
4846 
//
4847 
// added for bug 2332
4848 
assign rdpr_mx4_onehot_sel =
4849 
           ~(|tlu_rdpr_mx4_sel[2:1]);
4850 
//
4851 
// mux4 - 48b
4852 113 albert.wat 
mux3ds #(`RDSR_TSTATE_WIDTH) rdpr_mx4(
4853 
        .in0({tsa_rdata[`TLU_RD_PC_HI:`TLU_RD_PC_LO],2'b00}),
4854 
        .in1({tsa_rdata[`TLU_RD_NPC_HI:`TLU_NPC_LO],2'b00}),
4855 95 fafa1971 
        // .in0({tsa_rdata[`TLU_PC_HI-1:`TLU_PC_LO],2'b00}),
4856 
        // .in1({tsa_rdata[`TLU_NPC_HI-1:`TLU_NPC_LO],2'b00}),
4857 113 albert.wat 
    .in2(tstate_rdata[`RDSR_TSTATE_WIDTH-1:0]),
4858 95 fafa1971 
        .sel0(rdpr_mx4_onehot_sel),
4859 
        .sel1(tlu_rdpr_mx4_sel[1]),
4860 
        .sel2(tlu_rdpr_mx4_sel[2]),
4861 113 albert.wat 
        .dout(tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1:0])
4862 95 fafa1971 
);
4863 
//
4864 
// added for bug 2332
4865 
assign rdpr_mx5_onehot_sel =
4866 
           ~(|tlu_rdpr_mx5_sel[3:1]);
4867 
//
4868 
// mux5 - 64b
4869 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH) rdpr_mx5(
4870 
        .in0({{16{tba_rdata[`TLU_TBA_WIDTH-1]}},
4871 
           tba_rdata[`TLU_TBA_WIDTH-1:0],15'h0000}),
4872 
        .in1({{16{htba_rdata[`TLU_HTBA_WIDTH-1]}},
4873 
           htba_rdata[`TLU_HTBA_WIDTH-1:0],14'h0000}),
4874 
        .in2(tlu_rdpr_mx1_out[`TLU_ASR_DATA_WIDTH-1:0]),
4875 
        .in3(tlu_pib_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0]),
4876 95 fafa1971 
        .sel0(rdpr_mx5_onehot_sel),
4877 
        .sel1(tlu_rdpr_mx5_sel[1]),
4878 
        .sel2(tlu_rdpr_mx5_sel[2]),
4879 
        .sel3(tlu_rdpr_mx5_sel[3]),
4880 113 albert.wat 
        .dout(tlu_rdpr_mx5_out[`TLU_ASR_DATA_WIDTH-1:0])
4881 95 fafa1971 
);
4882 
//
4883 
// added for bug 2332
4884 
assign rdpr_mx6_onehot_sel =
4885 
           ~(|tlu_rdpr_mx6_sel[2:0]);
4886 
//
4887 
// mux6 - 12b
4888 113 albert.wat 
mux4ds #(`SFTINT_WIDTH) rdpr_mx6(
4889 95 fafa1971 
        .in0({8'b0,tsa_rdata[8:0]}),  // ttype
4890 113 albert.wat 
        .in1({5'b0,htstate_rdata[`RDSR_HPSTATE_WIDTH-1:0]}),
4891 95 fafa1971 
        .in2({13'b0,tlu_rdpr_mx2_out[3:0]}),
4892 113 albert.wat 
        .in3({tlu_rdpr_mx3_out[`SFTINT_WIDTH-1:0]}),
4893 95 fafa1971 
        .sel0(rdpr_mx6_onehot_sel),
4894 
        .sel1(tlu_rdpr_mx6_sel[0]),
4895 
        .sel2(tlu_rdpr_mx6_sel[1]),
4896 
        .sel3(tlu_rdpr_mx6_sel[2]),
4897 113 albert.wat 
        .dout(tlu_rdpr_mx6_out[`SFTINT_WIDTH-1:0])
4898 95 fafa1971 
);
4899 
//
4900 
// mux7- 64b
4901 113 albert.wat 
mux4ds #(`TLU_ASR_DATA_WIDTH) rdpr_mx7(
4902 
        .in0({{16{tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1]}},
4903 
           tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1:0]}),
4904 
        .in1(tlu_rdpr_mx5_out[`TLU_ASR_DATA_WIDTH-1:0]),
4905 
        .in2({47'b0,tlu_rdpr_mx6_out[`SFTINT_WIDTH-1:0]}),
4906 95 fafa1971 
        .in3({56'b0,lsu_tlu_rsr_data_e[7:0]}),
4907 
        .sel0(tlu_rdpr_mx7_sel[0]),
4908 
        .sel1(tlu_rdpr_mx7_sel[1]),
4909 
        .sel2(tlu_rdpr_mx7_sel[2]),
4910 
        .sel3(tlu_rdpr_mx7_sel[3]),
4911 113 albert.wat 
        .dout(tlu_rdpr_mx7_out[`TLU_ASR_DATA_WIDTH-1:0])
4912 95 fafa1971 
);
4913 
/*
4914 
mux4ds #(`TLU_ASR_DATA_WIDTH) rdpr_mx7(
4915 
        .in0({{16{tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1]}},
4916 
           tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1:0]}),
4917 
        .in1(tlu_rdpr_mx5_out[`TLU_ASR_DATA_WIDTH-1:0]),
4918 
        .in2({47'b0,tlu_rdpr_mx6_out[`SFTINT_WIDTH-1:0]}),
4919 
        .in3({56'b0,lsu_tlu_rsr_data_e[7:0]}),
4920 
        .sel0(tlu_rdpr_mx7_sel[0]),
4921 
        .sel1(tlu_rdpr_mx7_sel[1]),
4922 
        .sel2(tlu_rdpr_mx7_sel[2]),
4923 
        .sel3(tlu_rdpr_mx7_sel[3]),
4924 
        .dout(tlu_rdpr_mx7_out[`TLU_ASR_DATA_WIDTH-1:0])
4925 
);
4926 
*/
4927 
//
4928 
// drive rsr data to exu
4929 113 albert.wat 
assign tlu_exu_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0] =
4930 
           tlu_rdpr_mx7_out[`TLU_ASR_DATA_WIDTH-1:0];
4931 95 fafa1971 
//
4932 
// added for timing
4933 113 albert.wat 
dff_s #(`TLU_ASR_DATA_WIDTH) dff_tlu_exu_rsr_data_m (
4934 
    .din (tlu_exu_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0]),
4935 
    .q   (tlu_exu_rsr_data_m[`TLU_ASR_DATA_WIDTH-1:0]),
4936 95 fafa1971 
    .clk (clk),
4937 
    .se  (se),
4938 113 albert.wat 
    `SIMPLY_RISC_SCANIN,
4939 95 fafa1971 
    .so  ()
4940 
);
4941 
 
4942 
endmodule

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