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32 |
fafa1971 |
/*
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* Simply RISC S1 Core - Boot code
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*
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* Cutdown version from the original OpenSPARC T1:
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*
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* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
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*
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* Main changes:
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36 |
fafa1971 |
* - L1 and L2 cache handling are not enabled;
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32 |
fafa1971 |
* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
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*
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* Sun Microsystems' copyright notices follow:
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*/
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/*
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* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: hred_reset_handler.s
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this work; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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102 |
fafa1971 |
!! Enable L2-ucache: currently unused in S1 Core
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32 |
fafa1971 |
/*
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102 |
fafa1971 |
!! SunStudio version
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setx cregs_l2_ctl_reg_r64, %g1, %l1
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mov 0xa9, %g1
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sllx %g1, 32, %g1
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stx %l1, [%g1 + 0x00]
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stx %l1, [%g1 + 0x40]
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stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0xc0]
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*/
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/*
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!! GCC version
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wr %g0, 5, %asr26
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clr %l1
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32 |
fafa1971 |
mov 0xa9, %g1
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sllx %g1, 32, %g1
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stx %l1, [%g1 + 0x00]
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stx %l1, [%g1 + 0x40]
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stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0xc0]
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*/
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102 |
fafa1971 |
!! Set the LSU Diagnostic Register to enable all ways for L1-icache and L1-dcache
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!! and using the "random replacement" algorithm
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/*
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!! SunStudio version
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setx cregs_lsu_diag_reg_r64, %g1, %l1
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mov 0x10, %g1
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stxa %l1, [%g1] ASI_LSU_DIAG_REG
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*/
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!! GCC version
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mov 0x10, %g1
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stxa %l1, [%g1] (66)
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73 |
fafa1971 |
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102 |
fafa1971 |
!! Set the LSU Control Register to enable L1-icache and L1-dcache
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36 |
fafa1971 |
/*
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102 |
fafa1971 |
!! SunStudio version
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setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1
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stxa %l1, [%g0] ASI_LSU_CTL_REG
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36 |
fafa1971 |
*/
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fafa1971 |
!! GCC version
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mov 3, %l1
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stxa %l1, [%g0] (69)
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88 |
fafa1971 |
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35 |
fafa1971 |
!! Set hpstate.red = 0 and hpstate.enb = 1
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102 |
fafa1971 |
/*
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!! SunStudio version
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rdhpr %hpstate, %l1
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wrhpr %l1, 0x820, %hpstate
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*/
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!! GCC version
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fafa1971 |
rdhpr %hpstate, %l1
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73 |
fafa1971 |
and %l1,0x820,%l2
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xor %l2,0x800,%l2
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102 |
fafa1971 |
wrhpr %l1,%l2,%hpstate !! ensure red=0 and enb=1 leaving the other 2 bits of the register unchanged
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32 |
fafa1971 |
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102 |
fafa1971 |
!! Initialize Interrupt Queue Registers: currently unused in S1 Core
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32 |
fafa1971 |
/*
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wr %g0, 0x25, %asi
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stxa %g0, [0x3c0] %asi
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stxa %g0, [0x3c8] %asi
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stxa %g0, [0x3d0] %asi
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stxa %g0, [0x3d8] %asi
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stxa %g0, [0x3e0] %asi
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stxa %g0, [0x3e8] %asi
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stxa %g0, [0x3f0] %asi
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stxa %g0, [0x3f8] %asi
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wrpr 0, %tl
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wrpr 0, %g0, %gl
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wr %g0, cregs_fprs_imm, %fprs
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wr %g0, cregs_ccr_imm, %ccr
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wr %g0, cregs_asi_imm, %asi
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setx cregs_tick_r64, %g1, %g2
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35 |
fafa1971 |
!! FIXME set other ticks also
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32 |
fafa1971 |
wrpr %g2, %tick
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setx cregs_stick_r64, %g1, %g2
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wr %g2, %g0, %sys_tick
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mov 0x1, %g2
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sllx %g2, 63, %g2
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wr %g2, %g0, %tick_cmpr
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wr %g2, %g0, %sys_tick_cmpr
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wrhpr %g2, %g0, %hsys_tick_cmpr
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mov %g0, %y
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wrpr cregs_pil_imm, %pil
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wrpr cregs_cwp_imm, %cwp
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wrpr cregs_cansave_imm, %cansave
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wrpr cregs_canrestore_imm, %canrestore
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wrpr cregs_otherwin_imm, %otherwin
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wrpr cregs_cleanwin_imm, %cleanwin
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wrpr cregs_wstate_imm, %wstate
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*/
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35 |
fafa1971 |
!! Clear L1-icache and L1-dcache SFSR
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fafa1971 |
mov 0x18, %g1
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102 |
fafa1971 |
stxa %g0, [%g0 + %g1] 0x50 !! IMMU Synchronous Fault Status register=0
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stxa %g0, [%g0 + %g1] 0x58 !! DMMU Synchronous Fault Status register=0
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32 |
fafa1971 |
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102 |
fafa1971 |
!! Enable error trap
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/*
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!! SunStudio version
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setx cregs_sparc_error_en_reg_r64, %g1, %l1
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stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG
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*/
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!! GCC version
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!! in file defines.h constant cregs_sparc_error_en_reg_r64:=3
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fafa1971 |
!! so the effect should be "trap on correctable error" and "trap on uncorrectable error"
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fafa1971 |
sethi %hh(0x3),%g1
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or %g1,%hm(0x3),%g1
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sllx %g1,32,%g1
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sethi %hi(0x3),%l1
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or %l1,%g1,%l1
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or %l1,%lo(0x3),%l1
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88 |
fafa1971 |
stxa %l1, [%g0] (75) !! copy the content of the l1 register into the "SPARC Error Enable reg"
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32 |
fafa1971 |
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102 |
fafa1971 |
!! Enable L2-ucache error trap: currently unused in S1 Core
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32 |
fafa1971 |
/*
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setx cregs_l2_error_en_reg_r64, %g1, %l1
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mov 0xaa, %g1
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sllx %g1, 32, %g1
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stx %l1, [%g1 + 0x00]
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stx %l1, [%g1 + 0x40]
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stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0xc0]
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*/
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88 |
fafa1971 |
!! Load Partition ID (permits to multiple OSs to share the same TLB)
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102 |
fafa1971 |
/*
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!! SunStudio version
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rd %asr26, %l1
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set 0x0300, %g1
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32 |
fafa1971 |
and %l1, %g1, %l1
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102 |
fafa1971 |
srlx %l1, 8, %l1 ! %l1 has thread ID
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setx part_id_list, %g1, %g2
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sllx %l1, 3, %l1 ! offset - partition list
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ldx [%g2 + %l1], %g2 ! %g2 contains partition ID
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mov 0x80, %g1
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stxa %g2, [%g1] 0x58
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*/
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/*
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!! GCC version
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rd %asr26, %l1 !! ASR26 is the Strand Status and Control register
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set 0x0300, %g1
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and %l1, %g1, %l1
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35 |
fafa1971 |
srlx %l1, 8, %l1 !! %l1 has thread ID
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88 |
fafa1971 |
sethi %hi(0), %g1
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sethi %hi(0x4c000), %g2
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mov %g1, %g1
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mov %g2, %g2
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sllx %g1, 0x20, %g1
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or %g2, %g1, %g2
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102 |
fafa1971 |
sllx %l1, 3, %l1 !! offset - partition list
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ldx [%g2 + %l1], %g2 !! %g2 contains partition ID
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32 |
fafa1971 |
mov 0x80, %g1
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102 |
fafa1971 |
stxa %g2, [%g1] 0x58 !! I/DMMU Partition ID=g2
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*/
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35 |
fafa1971 |
!! Set Hypervisor Trap Base Address
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102 |
fafa1971 |
/*
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!! SunStudio version
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setx HV_TRAP_BASE_PA, %l0, %l7
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wrhpr %l7, %g0, %htba
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*/
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!! GCC version
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73 |
fafa1971 |
sethi %hh(0x80000),%g1
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or %g1,%hm(0x80000),%g1
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sllx %g1,32,%g1
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sethi %hi(0x80000),%l1
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or %l1,%g1,%l1
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or %l1,%lo(0x80000),%l1
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102 |
fafa1971 |
wrhpr %l7, %g0, %htba !! bits 63-14 select the trap vector
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| 219 |
73 |
fafa1971 |
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102 |
fafa1971 |
!! Load TSB config/base from memory and write to corresponding ASIs
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!! Set tsb-reg (4 at present) for one partition
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| 222 |
35 |
fafa1971 |
!! 2 i-config, 2-dconfig
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| 223 |
102 |
fafa1971 |
/*
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!! SunStudio version
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setx tsb_config_base_list, %l0, %g1
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*/
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/*
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!! GCC version
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| 229 |
88 |
fafa1971 |
sethi %hi(0), %l0
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sethi %hi(0x4c000), %g1
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mov %l0, %l0
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or %g1, 0x140, %g1
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sllx %l0, 0x20, %l0
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or %g1, %l0, %g1
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77 |
fafa1971 |
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35 |
fafa1971 |
sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list
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add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list
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32 |
fafa1971 |
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35 |
fafa1971 |
!! IMMU_CXT_Z_CONFIG (0x37, VA=0x00)
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| 240 |
32 |
fafa1971 |
ldx [%g1], %l1
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stxa %l1, [%g0] 0x37
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| 243 |
35 |
fafa1971 |
!! IMMU_CXT_NZ_CONFIG (0x3f, VA=0x00)
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| 244 |
32 |
fafa1971 |
ldx [%g1+8], %l1
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stxa %l1, [%g0] 0x3f
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| 247 |
35 |
fafa1971 |
!! IMMU_CXT_Z_PS0_TSB (0x35, VA=0x0)
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| 248 |
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!! IMMU_CXT_Z_PS1_TSB (0x36, VA=0x0)
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| 249 |
32 |
fafa1971 |
ldx [%g1+16], %l1
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| 250 |
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stxa %l1, [%g0] 0x35
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ldx [%g1+32], %l1
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| 252 |
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stxa %l1, [%g0] 0x36
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| 253 |
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| 254 |
35 |
fafa1971 |
!! IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)
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| 255 |
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!! IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)
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| 256 |
32 |
fafa1971 |
ldx [%g1+24], %l1
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| 257 |
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stxa %l1, [%g0] 0x3d
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| 258 |
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ldx [%g1+40], %l1
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| 259 |
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stxa %l1, [%g0] 0x3e
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| 260 |
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| 261 |
35 |
fafa1971 |
!! DMMU_CXT_Z_CONFIG (0x33, VA=0x00)
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| 262 |
32 |
fafa1971 |
ldx [%g1+64], %l1
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| 263 |
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stxa %l1, [%g0] 0x33
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| 264 |
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| 265 |
35 |
fafa1971 |
!! DMMU_CXT_NZ_CONFIG (0x3b, VA=0x00)
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| 266 |
32 |
fafa1971 |
ldx [%g1+72], %l1
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| 267 |
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stxa %l1, [%g0] 0x3b
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| 268 |
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| 269 |
35 |
fafa1971 |
!! DMMU_CXT_Z_PS0_TSB (0x31, VA=0x00)
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| 270 |
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!! DMMU_CXT_Z_PS1_TSB (0x32, VA=0x00)
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| 271 |
32 |
fafa1971 |
ldx [%g1+80], %l1
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| 272 |
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stxa %l1, [%g0] 0x31
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| 273 |
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ldx [%g1+96], %l1
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| 274 |
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stxa %l1, [%g0] 0x32
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| 275 |
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| 276 |
35 |
fafa1971 |
!! DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)
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| 277 |
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!! DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)
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| 278 |
32 |
fafa1971 |
ldx [%g1+88], %l1
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| 279 |
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stxa %l1, [%g0] 0x39
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| 280 |
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ldx [%g1+104], %l1
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| 281 |
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stxa %l1, [%g0] 0x3a
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| 282 |
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| 283 |
35 |
fafa1971 |
!! Demap all itlb and dtlb
|
| 284 |
32 |
fafa1971 |
mov 0x80, %o2
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| 285 |
102 |
fafa1971 |
stxa %g0, [%o2] 0x57 !! register ASI_IMMU_DEMAP=0 (IMMU TLB demap)
|
| 286 |
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stxa %g0, [%o2] 0x5f !! register ASI_DMMU_DEMAP=0 (DMMU TLB demap)
|
| 287 |
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*/
|
| 288 |
32 |
fafa1971 |
|
| 289 |
102 |
fafa1971 |
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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| 290 |
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|
!! Instructions merged from file hboot_tlb_init.s !!
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| 291 |
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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| 292 |
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| 293 |
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!! Init all itlb entries
|
| 294 |
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mov 0x30, %g1
|
| 295 |
|
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mov %g0, %g2
|
| 296 |
|
|
itlb_init_loop:
|
| 297 |
|
|
!! clear data and tag entries of the TLB buffer
|
| 298 |
|
|
stxa %g0, [%g1] 0x50 !! IMMU TLB Tag Access register=0
|
| 299 |
|
|
stxa %g0, [%g2] 0x55 !! IMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
|
| 300 |
|
|
|
| 301 |
|
|
add %g2, 8, %g2 !! increment the g2 register 8 bytes every time (64 bits)
|
| 302 |
|
|
cmp %g2, 0x200 !! compare g2 with 512 (512*8=4096=0x1000), but max VA=0x7F8
|
| 303 |
|
|
bne itlb_init_loop !! if (g2!=512) then run another loop
|
| 304 |
|
|
nop
|
| 305 |
|
|
|
| 306 |
|
|
!! Init all dtlb entries
|
| 307 |
|
|
mov 0x30, %g1
|
| 308 |
|
|
mov %g0, %g2
|
| 309 |
|
|
dtlb_init_loop:
|
| 310 |
|
|
stxa %g0, [%g1] 0x58 !! DMMU TLB Tag Access register=0
|
| 311 |
|
|
stxa %g0, [%g2] 0x5d !! DMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
|
| 312 |
|
|
|
| 313 |
|
|
add %g2, 8, %g2 !! increment the g2 register 64 bits each time
|
| 314 |
|
|
cmp %g2, 0x200 !! compare g2 with 512
|
| 315 |
|
|
bne dtlb_init_loop !! if (g2!=512) then run another loop
|
| 316 |
|
|
nop
|
| 317 |
|
|
|
| 318 |
|
|
!! Clear itlb/dtlb valid
|
| 319 |
|
|
stxa %g0, [%g0] 0x60 !! ASI_ITLB_INVALIDATE_ALL(IMMU TLB Invalidate register)=0
|
| 320 |
|
|
mov 0x8, %g1
|
| 321 |
|
|
stxa %g0, [%g0 + %g1] 0x60 !! ASI_DTLB_INVALIDATE_ALL(DMMU TLB Invalidate register)=0
|
| 322 |
|
|
|
| 323 |
|
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
| 324 |
|
|
!! End of inserted instructions !!
|
| 325 |
|
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
| 326 |
|
|
|
| 327 |
35 |
fafa1971 |
!! Initialize primary context register
|
| 328 |
32 |
fafa1971 |
mov 0x8, %l1
|
| 329 |
|
|
stxa %g0, [%l1] 0x21
|
| 330 |
|
|
|
| 331 |
35 |
fafa1971 |
!! Initialize secondary context register
|
| 332 |
32 |
fafa1971 |
mov 0x10, %l1
|
| 333 |
|
|
stxa %g0, [%l1] 0x21
|
| 334 |
|
|
|
| 335 |
35 |
fafa1971 |
!! Initialize dtsb entry for i context zero ps0, ps1
|
| 336 |
102 |
fafa1971 |
!! Set LSU Control Register to enable icache, dcache, immu, dmmu
|
| 337 |
36 |
fafa1971 |
/*
|
| 338 |
102 |
fafa1971 |
!! SunStudio version
|
| 339 |
|
|
setx cregs_lsu_ctl_reg_r64, %g1, %l1
|
| 340 |
36 |
fafa1971 |
*/
|
| 341 |
102 |
fafa1971 |
!! GCC version
|
| 342 |
|
|
!! LSU_CTL_REG[3]=1 (DMMU enabled)
|
| 343 |
|
|
!! LSU_CTL_REG[2]=1 (IMMU enabled)
|
| 344 |
|
|
!! LSU_CTL_REG[1]=1 (L1-dcache enabled)
|
| 345 |
|
|
!! LSU_CTL_REG[0]=1 (L1-icache enabled)
|
| 346 |
|
|
mov 0xF, %l1
|
| 347 |
88 |
fafa1971 |
stxa %l1, [%g0] (69)
|
| 348 |
|
|
|
| 349 |
102 |
fafa1971 |
!! Reset handler
|
| 350 |
|
|
/*
|
| 351 |
|
|
!! SunStudio version
|
| 352 |
|
|
setx HPriv_Reset_Handler, %g1, %g2
|
| 353 |
|
|
*/
|
| 354 |
|
|
!! GCC version
|
| 355 |
88 |
fafa1971 |
sethi %hi(0), %g1
|
| 356 |
|
|
sethi %hi(0x144000), %g2
|
| 357 |
|
|
mov %g1, %g1
|
| 358 |
|
|
mov %g2, %g2
|
| 359 |
|
|
sllx %g1, 0x20, %g1
|
| 360 |
|
|
or %g2, %g1, %g2
|
| 361 |
32 |
fafa1971 |
|
| 362 |
|
|
rdhpr %hpstate, %g3
|
| 363 |
88 |
fafa1971 |
wrpr 1, %tl !! current trap level = 1
|
| 364 |
77 |
fafa1971 |
|
| 365 |
102 |
fafa1971 |
!! HTSTATE
|
| 366 |
|
|
/*
|
| 367 |
|
|
!! SunStudio version
|
| 368 |
|
|
setx cregs_htstate_r64, %g1, %g4
|
| 369 |
|
|
*/
|
| 370 |
|
|
!! GCC version
|
| 371 |
73 |
fafa1971 |
sethi %hh(0x0),%g1
|
| 372 |
|
|
or %g1,%hm(0x0),%g1
|
| 373 |
|
|
sllx %g1,32,%g1
|
| 374 |
|
|
sethi %hi(0x0),%l1
|
| 375 |
|
|
or %l1,%g1,%l1
|
| 376 |
|
|
or %l1,%lo(0x0),%l1
|
| 377 |
|
|
|
| 378 |
102 |
fafa1971 |
wrhpr %g4, %g0, %htstate !! reset HTSTATE reg that store hyperpriviliged state after a trap
|
| 379 |
|
|
wrpr 0, %tl !! current trap level = 0 (No Trap)
|
| 380 |
|
|
mov 0x0, %o0 !! please don't delete since used in customized IMMU miss trap
|
| 381 |
32 |
fafa1971 |
jmp %g2
|
| 382 |
102 |
fafa1971 |
!! wrhpr %g0, 0x800, %hpstate !! ensure bit 11 of the HPSTATE register is set
|
| 383 |
32 |
fafa1971 |
nop
|
| 384 |
|
|
nop
|
| 385 |
|
|
|
