| 1 |
32 |
fafa1971 |
/*
|
| 2 |
|
|
* Simply RISC S1 Core - Boot code
|
| 3 |
|
|
*
|
| 4 |
|
|
* Cutdown version from the original OpenSPARC T1:
|
| 5 |
|
|
*
|
| 6 |
|
|
* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
|
| 7 |
|
|
*
|
| 8 |
|
|
* Main changes:
|
| 9 |
36 |
fafa1971 |
* - L1 and L2 cache handling are not enabled;
|
| 10 |
32 |
fafa1971 |
* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
|
| 11 |
|
|
*
|
| 12 |
|
|
* Sun Microsystems' copyright notices follow:
|
| 13 |
|
|
*/
|
| 14 |
|
|
|
| 15 |
|
|
/*
|
| 16 |
|
|
* ========== Copyright Header Begin ==========================================
|
| 17 |
|
|
*
|
| 18 |
|
|
* OpenSPARC T1 Processor File: hred_reset_handler.s
|
| 19 |
|
|
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
| 20 |
|
|
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
| 21 |
|
|
*
|
| 22 |
|
|
* The above named program is free software; you can redistribute it and/or
|
| 23 |
|
|
* modify it under the terms of the GNU General Public
|
| 24 |
|
|
* License version 2 as published by the Free Software Foundation.
|
| 25 |
|
|
*
|
| 26 |
|
|
* The above named program is distributed in the hope that it will be
|
| 27 |
|
|
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 28 |
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
| 29 |
|
|
* General Public License for more details.
|
| 30 |
|
|
*
|
| 31 |
|
|
* You should have received a copy of the GNU General Public
|
| 32 |
|
|
* License along with this work; if not, write to the Free Software
|
| 33 |
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 34 |
|
|
*
|
| 35 |
|
|
* ========== Copyright Header End ============================================
|
| 36 |
|
|
*/
|
| 37 |
|
|
|
| 38 |
102 |
fafa1971 |
!! Enable L2-ucache: currently unused in S1 Core
|
| 39 |
32 |
fafa1971 |
/*
|
| 40 |
102 |
fafa1971 |
!! SunStudio version
|
| 41 |
|
|
setx cregs_l2_ctl_reg_r64, %g1, %l1
|
| 42 |
|
|
mov 0xa9, %g1
|
| 43 |
|
|
sllx %g1, 32, %g1
|
| 44 |
|
|
stx %l1, [%g1 + 0x00]
|
| 45 |
|
|
stx %l1, [%g1 + 0x40]
|
| 46 |
|
|
stx %l1, [%g1 + 0x80]
|
| 47 |
|
|
stx %l1, [%g1 + 0xc0]
|
| 48 |
|
|
*/
|
| 49 |
|
|
|
| 50 |
|
|
/*
|
| 51 |
|
|
!! GCC version
|
| 52 |
|
|
wr %g0, 5, %asr26
|
| 53 |
|
|
clr %l1
|
| 54 |
32 |
fafa1971 |
mov 0xa9, %g1
|
| 55 |
|
|
sllx %g1, 32, %g1
|
| 56 |
|
|
stx %l1, [%g1 + 0x00]
|
| 57 |
|
|
stx %l1, [%g1 + 0x40]
|
| 58 |
|
|
stx %l1, [%g1 + 0x80]
|
| 59 |
|
|
stx %l1, [%g1 + 0xc0]
|
| 60 |
|
|
*/
|
| 61 |
|
|
|
| 62 |
102 |
fafa1971 |
!! Set the LSU Diagnostic Register to enable all ways for L1-icache and L1-dcache
|
| 63 |
|
|
!! and using the "random replacement" algorithm
|
| 64 |
|
|
/*
|
| 65 |
|
|
!! SunStudio version
|
| 66 |
|
|
setx cregs_lsu_diag_reg_r64, %g1, %l1
|
| 67 |
|
|
mov 0x10, %g1
|
| 68 |
|
|
stxa %l1, [%g1] ASI_LSU_DIAG_REG
|
| 69 |
|
|
*/
|
| 70 |
|
|
!! GCC version
|
| 71 |
|
|
mov 0x10, %g1
|
| 72 |
|
|
stxa %l1, [%g1] (66)
|
| 73 |
73 |
fafa1971 |
|
| 74 |
102 |
fafa1971 |
!! Set the LSU Control Register to enable L1-icache and L1-dcache
|
| 75 |
36 |
fafa1971 |
/*
|
| 76 |
102 |
fafa1971 |
!! SunStudio version
|
| 77 |
|
|
setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1
|
| 78 |
|
|
stxa %l1, [%g0] ASI_LSU_CTL_REG
|
| 79 |
36 |
fafa1971 |
*/
|
| 80 |
102 |
fafa1971 |
!! GCC version
|
| 81 |
|
|
mov 3, %l1
|
| 82 |
|
|
stxa %l1, [%g0] (69)
|
| 83 |
88 |
fafa1971 |
|
| 84 |
35 |
fafa1971 |
!! Set hpstate.red = 0 and hpstate.enb = 1
|
| 85 |
102 |
fafa1971 |
rdhpr %hpstate, %l1
|
| 86 |
|
|
wrhpr %l1, 0x820, %hpstate
|
| 87 |
32 |
fafa1971 |
|
| 88 |
102 |
fafa1971 |
!! Initialize Interrupt Queue Registers: currently unused in S1 Core
|
| 89 |
32 |
fafa1971 |
/*
|
| 90 |
|
|
wr %g0, 0x25, %asi
|
| 91 |
|
|
|
| 92 |
|
|
stxa %g0, [0x3c0] %asi
|
| 93 |
|
|
stxa %g0, [0x3c8] %asi
|
| 94 |
|
|
stxa %g0, [0x3d0] %asi
|
| 95 |
|
|
stxa %g0, [0x3d8] %asi
|
| 96 |
|
|
|
| 97 |
|
|
stxa %g0, [0x3e0] %asi
|
| 98 |
|
|
stxa %g0, [0x3e8] %asi
|
| 99 |
|
|
stxa %g0, [0x3f0] %asi
|
| 100 |
|
|
stxa %g0, [0x3f8] %asi
|
| 101 |
|
|
|
| 102 |
|
|
wrpr 0, %tl
|
| 103 |
|
|
wrpr 0, %g0, %gl
|
| 104 |
|
|
wr %g0, cregs_fprs_imm, %fprs
|
| 105 |
|
|
wr %g0, cregs_ccr_imm, %ccr
|
| 106 |
|
|
|
| 107 |
|
|
wr %g0, cregs_asi_imm, %asi
|
| 108 |
|
|
setx cregs_tick_r64, %g1, %g2
|
| 109 |
35 |
fafa1971 |
!! FIXME set other ticks also
|
| 110 |
32 |
fafa1971 |
wrpr %g2, %tick
|
| 111 |
|
|
setx cregs_stick_r64, %g1, %g2
|
| 112 |
|
|
|
| 113 |
|
|
wr %g2, %g0, %sys_tick
|
| 114 |
|
|
mov 0x1, %g2
|
| 115 |
|
|
sllx %g2, 63, %g2
|
| 116 |
|
|
wr %g2, %g0, %tick_cmpr
|
| 117 |
|
|
|
| 118 |
|
|
wr %g2, %g0, %sys_tick_cmpr
|
| 119 |
|
|
wrhpr %g2, %g0, %hsys_tick_cmpr
|
| 120 |
|
|
mov %g0, %y
|
| 121 |
|
|
wrpr cregs_pil_imm, %pil
|
| 122 |
|
|
|
| 123 |
|
|
wrpr cregs_cwp_imm, %cwp
|
| 124 |
|
|
wrpr cregs_cansave_imm, %cansave
|
| 125 |
|
|
wrpr cregs_canrestore_imm, %canrestore
|
| 126 |
|
|
wrpr cregs_otherwin_imm, %otherwin
|
| 127 |
|
|
|
| 128 |
|
|
wrpr cregs_cleanwin_imm, %cleanwin
|
| 129 |
|
|
wrpr cregs_wstate_imm, %wstate
|
| 130 |
|
|
*/
|
| 131 |
|
|
|
| 132 |
35 |
fafa1971 |
!! Clear L1-icache and L1-dcache SFSR
|
| 133 |
32 |
fafa1971 |
mov 0x18, %g1
|
| 134 |
102 |
fafa1971 |
stxa %g0, [%g0 + %g1] 0x50 !! IMMU Synchronous Fault Status register=0
|
| 135 |
|
|
stxa %g0, [%g0 + %g1] 0x58 !! DMMU Synchronous Fault Status register=0
|
| 136 |
32 |
fafa1971 |
|
| 137 |
102 |
fafa1971 |
!! Enable error trap
|
| 138 |
|
|
/*
|
| 139 |
|
|
!! SunStudio version
|
| 140 |
|
|
setx cregs_sparc_error_en_reg_r64, %g1, %l1
|
| 141 |
|
|
stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG
|
| 142 |
|
|
*/
|
| 143 |
|
|
!! GCC version
|
| 144 |
|
|
!! in file defines.h constant cregs_sparc_error_en_reg_r64:=3
|
| 145 |
88 |
fafa1971 |
!! so the effect should be "trap on correctable error" and "trap on uncorrectable error"
|
| 146 |
73 |
fafa1971 |
sethi %hh(0x3),%g1
|
| 147 |
|
|
or %g1,%hm(0x3),%g1
|
| 148 |
|
|
sllx %g1,32,%g1
|
| 149 |
|
|
sethi %hi(0x3),%l1
|
| 150 |
|
|
or %l1,%g1,%l1
|
| 151 |
|
|
or %l1,%lo(0x3),%l1
|
| 152 |
88 |
fafa1971 |
stxa %l1, [%g0] (75) !! copy the content of the l1 register into the "SPARC Error Enable reg"
|
| 153 |
32 |
fafa1971 |
|
| 154 |
102 |
fafa1971 |
!! Enable L2-ucache error trap: currently unused in S1 Core
|
| 155 |
32 |
fafa1971 |
/*
|
| 156 |
|
|
setx cregs_l2_error_en_reg_r64, %g1, %l1
|
| 157 |
|
|
|
| 158 |
|
|
mov 0xaa, %g1
|
| 159 |
|
|
sllx %g1, 32, %g1
|
| 160 |
|
|
stx %l1, [%g1 + 0x00]
|
| 161 |
|
|
stx %l1, [%g1 + 0x40]
|
| 162 |
|
|
|
| 163 |
|
|
stx %l1, [%g1 + 0x80]
|
| 164 |
|
|
stx %l1, [%g1 + 0xc0]
|
| 165 |
|
|
*/
|
| 166 |
|
|
|
| 167 |
88 |
fafa1971 |
!! Load Partition ID (permits to multiple OSs to share the same TLB)
|
| 168 |
102 |
fafa1971 |
/*
|
| 169 |
|
|
!! SunStudio version
|
| 170 |
|
|
rd %asr26, %l1
|
| 171 |
|
|
set 0x0300, %g1
|
| 172 |
32 |
fafa1971 |
and %l1, %g1, %l1
|
| 173 |
102 |
fafa1971 |
srlx %l1, 8, %l1 ! %l1 has thread ID
|
| 174 |
|
|
setx part_id_list, %g1, %g2
|
| 175 |
|
|
sllx %l1, 3, %l1 ! offset - partition list
|
| 176 |
|
|
ldx [%g2 + %l1], %g2 ! %g2 contains partition ID
|
| 177 |
|
|
mov 0x80, %g1
|
| 178 |
|
|
stxa %g2, [%g1] 0x58
|
| 179 |
|
|
*/
|
| 180 |
|
|
/*
|
| 181 |
|
|
!! GCC version
|
| 182 |
|
|
rd %asr26, %l1 !! ASR26 is the Strand Status and Control register
|
| 183 |
|
|
set 0x0300, %g1
|
| 184 |
|
|
and %l1, %g1, %l1
|
| 185 |
35 |
fafa1971 |
srlx %l1, 8, %l1 !! %l1 has thread ID
|
| 186 |
88 |
fafa1971 |
sethi %hi(0), %g1
|
| 187 |
|
|
sethi %hi(0x4c000), %g2
|
| 188 |
|
|
mov %g1, %g1
|
| 189 |
|
|
mov %g2, %g2
|
| 190 |
|
|
sllx %g1, 0x20, %g1
|
| 191 |
|
|
or %g2, %g1, %g2
|
| 192 |
102 |
fafa1971 |
sllx %l1, 3, %l1 !! offset - partition list
|
| 193 |
|
|
ldx [%g2 + %l1], %g2 !! %g2 contains partition ID
|
| 194 |
32 |
fafa1971 |
mov 0x80, %g1
|
| 195 |
102 |
fafa1971 |
stxa %g2, [%g1] 0x58 !! I/DMMU Partition ID=g2
|
| 196 |
|
|
*/
|
| 197 |
35 |
fafa1971 |
!! Set Hypervisor Trap Base Address
|
| 198 |
102 |
fafa1971 |
/*
|
| 199 |
|
|
!! SunStudio version
|
| 200 |
|
|
setx HV_TRAP_BASE_PA, %l0, %l7
|
| 201 |
|
|
wrhpr %l7, %g0, %htba
|
| 202 |
|
|
*/
|
| 203 |
|
|
!! GCC version
|
| 204 |
73 |
fafa1971 |
sethi %hh(0x80000),%g1
|
| 205 |
|
|
or %g1,%hm(0x80000),%g1
|
| 206 |
|
|
sllx %g1,32,%g1
|
| 207 |
|
|
sethi %hi(0x80000),%l1
|
| 208 |
|
|
or %l1,%g1,%l1
|
| 209 |
|
|
or %l1,%lo(0x80000),%l1
|
| 210 |
102 |
fafa1971 |
wrhpr %l7, %g0, %htba !! bits 63-14 select the trap vector
|
| 211 |
73 |
fafa1971 |
|
| 212 |
102 |
fafa1971 |
!! Load TSB config/base from memory and write to corresponding ASIs
|
| 213 |
|
|
!! Set tsb-reg (4 at present) for one partition
|
| 214 |
35 |
fafa1971 |
!! 2 i-config, 2-dconfig
|
| 215 |
102 |
fafa1971 |
/*
|
| 216 |
|
|
!! SunStudio version
|
| 217 |
|
|
setx tsb_config_base_list, %l0, %g1
|
| 218 |
|
|
*/
|
| 219 |
|
|
/*
|
| 220 |
|
|
!! GCC version
|
| 221 |
88 |
fafa1971 |
sethi %hi(0), %l0
|
| 222 |
|
|
sethi %hi(0x4c000), %g1
|
| 223 |
|
|
mov %l0, %l0
|
| 224 |
|
|
or %g1, 0x140, %g1
|
| 225 |
|
|
sllx %l0, 0x20, %l0
|
| 226 |
|
|
or %g1, %l0, %g1
|
| 227 |
77 |
fafa1971 |
|
| 228 |
35 |
fafa1971 |
sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list
|
| 229 |
|
|
add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list
|
| 230 |
32 |
fafa1971 |
|
| 231 |
35 |
fafa1971 |
!! IMMU_CXT_Z_CONFIG (0x37, VA=0x00)
|
| 232 |
32 |
fafa1971 |
ldx [%g1], %l1
|
| 233 |
|
|
stxa %l1, [%g0] 0x37
|
| 234 |
|
|
|
| 235 |
35 |
fafa1971 |
!! IMMU_CXT_NZ_CONFIG (0x3f, VA=0x00)
|
| 236 |
32 |
fafa1971 |
ldx [%g1+8], %l1
|
| 237 |
|
|
stxa %l1, [%g0] 0x3f
|
| 238 |
|
|
|
| 239 |
35 |
fafa1971 |
!! IMMU_CXT_Z_PS0_TSB (0x35, VA=0x0)
|
| 240 |
|
|
!! IMMU_CXT_Z_PS1_TSB (0x36, VA=0x0)
|
| 241 |
32 |
fafa1971 |
ldx [%g1+16], %l1
|
| 242 |
|
|
stxa %l1, [%g0] 0x35
|
| 243 |
|
|
ldx [%g1+32], %l1
|
| 244 |
|
|
stxa %l1, [%g0] 0x36
|
| 245 |
|
|
|
| 246 |
35 |
fafa1971 |
!! IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)
|
| 247 |
|
|
!! IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)
|
| 248 |
32 |
fafa1971 |
ldx [%g1+24], %l1
|
| 249 |
|
|
stxa %l1, [%g0] 0x3d
|
| 250 |
|
|
ldx [%g1+40], %l1
|
| 251 |
|
|
stxa %l1, [%g0] 0x3e
|
| 252 |
|
|
|
| 253 |
35 |
fafa1971 |
!! DMMU_CXT_Z_CONFIG (0x33, VA=0x00)
|
| 254 |
32 |
fafa1971 |
ldx [%g1+64], %l1
|
| 255 |
|
|
stxa %l1, [%g0] 0x33
|
| 256 |
|
|
|
| 257 |
35 |
fafa1971 |
!! DMMU_CXT_NZ_CONFIG (0x3b, VA=0x00)
|
| 258 |
32 |
fafa1971 |
ldx [%g1+72], %l1
|
| 259 |
|
|
stxa %l1, [%g0] 0x3b
|
| 260 |
|
|
|
| 261 |
35 |
fafa1971 |
!! DMMU_CXT_Z_PS0_TSB (0x31, VA=0x00)
|
| 262 |
|
|
!! DMMU_CXT_Z_PS1_TSB (0x32, VA=0x00)
|
| 263 |
32 |
fafa1971 |
ldx [%g1+80], %l1
|
| 264 |
|
|
stxa %l1, [%g0] 0x31
|
| 265 |
|
|
ldx [%g1+96], %l1
|
| 266 |
|
|
stxa %l1, [%g0] 0x32
|
| 267 |
|
|
|
| 268 |
35 |
fafa1971 |
!! DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)
|
| 269 |
|
|
!! DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)
|
| 270 |
32 |
fafa1971 |
ldx [%g1+88], %l1
|
| 271 |
|
|
stxa %l1, [%g0] 0x39
|
| 272 |
|
|
ldx [%g1+104], %l1
|
| 273 |
|
|
stxa %l1, [%g0] 0x3a
|
| 274 |
|
|
|
| 275 |
35 |
fafa1971 |
!! Demap all itlb and dtlb
|
| 276 |
32 |
fafa1971 |
mov 0x80, %o2
|
| 277 |
102 |
fafa1971 |
stxa %g0, [%o2] 0x57 !! register ASI_IMMU_DEMAP=0 (IMMU TLB demap)
|
| 278 |
|
|
stxa %g0, [%o2] 0x5f !! register ASI_DMMU_DEMAP=0 (DMMU TLB demap)
|
| 279 |
|
|
*/
|
| 280 |
32 |
fafa1971 |
|
| 281 |
102 |
fafa1971 |
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
| 282 |
|
|
!! Instructions merged from file hboot_tlb_init.s !!
|
| 283 |
|
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
| 284 |
|
|
|
| 285 |
|
|
!! Init all itlb entries
|
| 286 |
|
|
mov 0x30, %g1
|
| 287 |
|
|
mov %g0, %g2
|
| 288 |
|
|
itlb_init_loop:
|
| 289 |
|
|
!! clear data and tag entries of the TLB buffer
|
| 290 |
|
|
stxa %g0, [%g1] 0x50 !! IMMU TLB Tag Access register=0
|
| 291 |
|
|
stxa %g0, [%g2] 0x55 !! IMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
|
| 292 |
|
|
|
| 293 |
|
|
add %g2, 8, %g2 !! increment the g2 register 8 bytes every time (64 bits)
|
| 294 |
|
|
cmp %g2, 0x200 !! compare g2 with 512 (512*8=4096=0x1000), but max VA=0x7F8
|
| 295 |
|
|
bne itlb_init_loop !! if (g2!=512) then run another loop
|
| 296 |
|
|
nop
|
| 297 |
|
|
|
| 298 |
|
|
!! Init all dtlb entries
|
| 299 |
|
|
mov 0x30, %g1
|
| 300 |
|
|
mov %g0, %g2
|
| 301 |
|
|
dtlb_init_loop:
|
| 302 |
|
|
stxa %g0, [%g1] 0x58 !! DMMU TLB Tag Access register=0
|
| 303 |
|
|
stxa %g0, [%g2] 0x5d !! DMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
|
| 304 |
|
|
|
| 305 |
|
|
add %g2, 8, %g2 !! increment the g2 register 64 bits each time
|
| 306 |
|
|
cmp %g2, 0x200 !! compare g2 with 512
|
| 307 |
|
|
bne dtlb_init_loop !! if (g2!=512) then run another loop
|
| 308 |
|
|
nop
|
| 309 |
|
|
|
| 310 |
|
|
!! Clear itlb/dtlb valid
|
| 311 |
|
|
stxa %g0, [%g0] 0x60 !! ASI_ITLB_INVALIDATE_ALL(IMMU TLB Invalidate register)=0
|
| 312 |
|
|
mov 0x8, %g1
|
| 313 |
|
|
stxa %g0, [%g0 + %g1] 0x60 !! ASI_DTLB_INVALIDATE_ALL(DMMU TLB Invalidate register)=0
|
| 314 |
|
|
|
| 315 |
|
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
| 316 |
|
|
!! End of inserted instructions !!
|
| 317 |
|
|
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
| 318 |
|
|
|
| 319 |
35 |
fafa1971 |
!! Initialize primary context register
|
| 320 |
32 |
fafa1971 |
mov 0x8, %l1
|
| 321 |
|
|
stxa %g0, [%l1] 0x21
|
| 322 |
|
|
|
| 323 |
35 |
fafa1971 |
!! Initialize secondary context register
|
| 324 |
32 |
fafa1971 |
mov 0x10, %l1
|
| 325 |
|
|
stxa %g0, [%l1] 0x21
|
| 326 |
|
|
|
| 327 |
35 |
fafa1971 |
!! Initialize dtsb entry for i context zero ps0, ps1
|
| 328 |
102 |
fafa1971 |
!! Set LSU Control Register to enable icache, dcache, immu, dmmu
|
| 329 |
36 |
fafa1971 |
/*
|
| 330 |
102 |
fafa1971 |
!! SunStudio version
|
| 331 |
|
|
setx cregs_lsu_ctl_reg_r64, %g1, %l1
|
| 332 |
36 |
fafa1971 |
*/
|
| 333 |
102 |
fafa1971 |
!! GCC version
|
| 334 |
|
|
!! LSU_CTL_REG[3]=1 (DMMU enabled)
|
| 335 |
|
|
!! LSU_CTL_REG[2]=1 (IMMU enabled)
|
| 336 |
|
|
!! LSU_CTL_REG[1]=1 (L1-dcache enabled)
|
| 337 |
|
|
!! LSU_CTL_REG[0]=1 (L1-icache enabled)
|
| 338 |
|
|
mov 0xF, %l1
|
| 339 |
88 |
fafa1971 |
stxa %l1, [%g0] (69)
|
| 340 |
|
|
|
| 341 |
102 |
fafa1971 |
!! Reset handler
|
| 342 |
|
|
/*
|
| 343 |
|
|
!! SunStudio version
|
| 344 |
|
|
setx HPriv_Reset_Handler, %g1, %g2
|
| 345 |
|
|
*/
|
| 346 |
|
|
!! GCC version
|
| 347 |
88 |
fafa1971 |
sethi %hi(0), %g1
|
| 348 |
103 |
fafa1971 |
sethi %hi(0x40000), %g2 !! New jump address in memory (used by last op of this file)
|
| 349 |
88 |
fafa1971 |
mov %g1, %g1
|
| 350 |
|
|
mov %g2, %g2
|
| 351 |
|
|
sllx %g1, 0x20, %g1
|
| 352 |
|
|
or %g2, %g1, %g2
|
| 353 |
32 |
fafa1971 |
|
| 354 |
|
|
rdhpr %hpstate, %g3
|
| 355 |
103 |
fafa1971 |
wrpr 1, %tl !! current trap level = 1
|
| 356 |
77 |
fafa1971 |
|
| 357 |
102 |
fafa1971 |
!! HTSTATE
|
| 358 |
|
|
/*
|
| 359 |
|
|
!! SunStudio version
|
| 360 |
|
|
setx cregs_htstate_r64, %g1, %g4
|
| 361 |
|
|
*/
|
| 362 |
|
|
!! GCC version
|
| 363 |
73 |
fafa1971 |
sethi %hh(0x0),%g1
|
| 364 |
|
|
or %g1,%hm(0x0),%g1
|
| 365 |
|
|
sllx %g1,32,%g1
|
| 366 |
|
|
sethi %hi(0x0),%l1
|
| 367 |
|
|
or %l1,%g1,%l1
|
| 368 |
|
|
or %l1,%lo(0x0),%l1
|
| 369 |
|
|
|
| 370 |
102 |
fafa1971 |
wrhpr %g4, %g0, %htstate !! reset HTSTATE reg that store hyperpriviliged state after a trap
|
| 371 |
|
|
wrpr 0, %tl !! current trap level = 0 (No Trap)
|
| 372 |
|
|
mov 0x0, %o0 !! please don't delete since used in customized IMMU miss trap
|
| 373 |
32 |
fafa1971 |
jmp %g2
|
| 374 |
102 |
fafa1971 |
!! wrhpr %g0, 0x800, %hpstate !! ensure bit 11 of the HPSTATE register is set
|
| 375 |
32 |
fafa1971 |
nop
|
| 376 |
|
|
nop
|
| 377 |
|
|
|
