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fafa1971 |
/*
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* Simply RISC S1 Core - Boot code
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*
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* Cutdown version from the original OpenSPARC T1:
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*
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* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
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*
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* Main changes:
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36 |
fafa1971 |
* - L1 and L2 cache handling are not enabled;
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fafa1971 |
* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
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*
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* Sun Microsystems' copyright notices follow:
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*/
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/*
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* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: hred_reset_handler.s
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this work; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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albert.wat |
/* Base address for Power-On Reser is 0xFFF0000020, adding 8 NOPs to artificially create the 0x20 offset */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* Initialize windowed local, output and input GPRs */
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wrpr %g0, %g0, %cwp !! CWP = 0
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wrpr %g0, 0x6, %cansave !! CANSAVE = 6
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wrpr %g0, %g0, %canrestore !! CANRESTORE = 0
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wrpr %g0, %g0, %otherwin !! OTHERWIN = 0
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wrpr %g0, 0x7, %cleanwin !! CLEANWIN = 7
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wrpr %g0, 0x7, %wstate !! WSTATE = (b)000_111
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add %g0, 0x1, %l1 !! l1 = 1
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add %g0, 0x1, %o1 !! o1 = 1
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add %g0, 0x1, %i1 !! i1 = 1
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add %l1, 0x1, %l2 !! l1 = 2
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add %o1, 0x1, %o2 !! o1 = 2
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add %i1, 0x1, %i2 !! i1 = 2
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add %l2, 0x1, %l3 !! l1 = 3
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add %o2, 0x1, %o3 !! o1 = 3
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add %i2, 0x1, %i3 !! i1 = 3
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nop; nop; nop; nop
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fafa1971 |
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albert.wat |
/* Set the LSU Diagnostic Register to enable all ways for L1-icache and L1-dcache and using the "random replacement" algorithm */
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clr %l1 !! Clear l1
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mov 0x10, %g1
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stxa %l1, [%g1] (66) !! LSU_DIAG_REG = b00
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fafa1971 |
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albert.wat |
/* Set the LSU Control Register to enable L1-icache and L1-dcache */
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! mov 3, %l1
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! stxa %l1, [%g0] (69)
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fafa1971 |
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albert.wat |
/* Set hpstate.red = 0 and hpstate.enb = 1 */
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rdhpr %hpstate, %l1
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wrhpr %l1, 0x820, %hpstate
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fafa1971 |
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albert.wat |
/* Clear L1-icache and L1-dcache SFSR */
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mov 0x18, %g1
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stxa %g0, [%g0 + %g1] 0x50 !! IMMU Synchronous Fault Status (SFS) register=0
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stxa %g0, [%g0 + %g1] 0x58 !! DMMU Synchronous Fault Status (SFS) register=0
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fafa1971 |
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albert.wat |
/* SPARC Error Enable Reg. */
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fafa1971 |
!! in file defines.h constant cregs_sparc_error_en_reg_r64:=3
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fafa1971 |
!! so the effect should be "trap on correctable error" and "trap on uncorrectable error"
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albert.wat |
or %g0, 0x3, %l1 !! l1 = 3
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stxa %l1, [%g0] (75) !! SPARC_Error_Enable_reg = 3
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fafa1971 |
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albert.wat |
/* Set HTBA: HTBA[63:14] = 0x12 */
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mov 1, %g1 !! g1 = 1
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sllx %g1, 18, %l1 !! l1 = 40000
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sllx %g1, 15, %g1 !! g1 = 8000
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or %l1, %g1, %l1 !! l1 = 48000
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wrhpr %l1, %g0, %htba !! bits 63-14 select Hpriv trap vector
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fafa1971 |
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albert.wat |
/**************************************************/
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/* Instructions merged from file hboot_tlb_init.s */
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/**************************************************/
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fafa1971 |
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albert.wat |
/* Init all itlb entries */
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fafa1971 |
mov 0x30, %g1
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mov %g0, %g2
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itlb_init_loop:
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stxa %g0, [%g1] 0x50 !! IMMU TLB Tag Access register=0
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stxa %g0, [%g2] 0x55 !! IMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
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add %g2, 8, %g2 !! increment the g2 register 8 bytes every time (64 bits)
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cmp %g2, 0x200 !! compare g2 with 512 (512*8=4096=0x1000), but max VA=0x7F8
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bne itlb_init_loop !! if (g2!=512) then run another loop
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nop
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albert.wat |
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/* Init all dtlb entries */
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fafa1971 |
mov 0x30, %g1
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mov %g0, %g2
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dtlb_init_loop:
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stxa %g0, [%g1] 0x58 !! DMMU TLB Tag Access register=0
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stxa %g0, [%g2] 0x5d !! DMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
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add %g2, 8, %g2 !! increment the g2 register 64 bits each time
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cmp %g2, 0x200 !! compare g2 with 512
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bne dtlb_init_loop !! if (g2!=512) then run another loop
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nop
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albert.wat |
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/* Clear itlb/dtlb valid */
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fafa1971 |
stxa %g0, [%g0] 0x60 !! ASI_ITLB_INVALIDATE_ALL(IMMU TLB Invalidate register)=0
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mov 0x8, %g1
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stxa %g0, [%g0 + %g1] 0x60 !! ASI_DTLB_INVALIDATE_ALL(DMMU TLB Invalidate register)=0
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albert.wat |
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/********************************/
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/* End of inserted instructions */
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/********************************/
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fafa1971 |
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albert.wat |
/* Initialize primary context register = 0 */
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fafa1971 |
mov 0x8, %l1
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stxa %g0, [%l1] 0x21
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albert.wat |
/* Initialize secondary context register = 0 */
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fafa1971 |
mov 0x10, %l1
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albert.wat |
stxa %g0, [%l1] 0x21
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fafa1971 |
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albert.wat |
/* LSU_CTL_REG[3]=1 (DMMU enabled)
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LSU_CTL_REG[2]=1 (IMMU enabled)
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LSU_CTL_REG[1]=0 (L1-dcache disabled)
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LSU_CTL_REG[0]=0 (L1-icache disabled) */
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mov 0xC, %l1 !! all enabled
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stxa %l1, [%g0] (69)
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fafa1971 |
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albert.wat |
/* Jump to program in RAM */
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sethi %hi(0), %g1
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sethi %hi(0x40000), %g2 !! Jump address in RAM
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mov %g1, %g1
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mov %g2, %g2
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sllx %g1, 0x20, %g1
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or %g2, %g1, %g2
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fafa1971 |
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albert.wat |
/* HTSTATE[TL=1] */
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rdhpr %hpstate, %g3
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wrpr 1, %tl !! current trap level = 1
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mov 0x0, %l1 !! l1 = 0
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wrhpr %g3, %g0, %htstate !! reset HTSTATE reg that store hyperpriviliged state after a trap
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wrpr 0, %tl !! current trap level = 0 (No Trap)
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mov 0x0, %o0 !! please don’t delete since used in customized IMMU miss trap
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fafa1971 |
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albert.wat |
/* Jump in RAM */
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jmp %g2 !! jump to 0x40000
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!! wrhpr %g0, 0x804, %hpstate !! ensure bit 11 of the HPSTATE register is set
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nop
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nop
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