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fafa1971 |
/*
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* Simply RISC S1 Core - Boot code
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*
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* Cutdown version from the original OpenSPARC T1:
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*
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* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
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*
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* Main changes:
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* - L2 cache handling commented out since not implemented in S1 Core ;
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* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
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*
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* Sun Microsystems' copyright notices follow:
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*/
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/*
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* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: hred_reset_handler.s
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this work; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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33 |
fafa1971 |
#include "defines.h"
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32 |
fafa1971 |
// Enable L2-ucache: Unused in S1 Core
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/*
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setx cregs_l2_ctl_reg_r64, %g1, %l1 // aka "wr %g0, 5, %asr26" "clr %l1"
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mov 0xa9, %g1
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sllx %g1, 32, %g1
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stx %l1, [%g1 + 0x00]
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stx %l1, [%g1 + 0x40]
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stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0xc0]
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*/
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// Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
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setx cregs_lsu_diag_reg_r64, %g1, %l1 // aka "clr %l1"
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mov 0x10, %g1
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stxa %l1, [%g1] ASI_LSU_DIAG_REG // aka "stxa %l1, [%g1] (66)"
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// Set LSU Control Register to enable L1-icache and L1-dcache
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setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 // aka "mov 3, %l1"
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stxa %l1, [%g0] ASI_LSU_CTL_REG // aka "stxa %l1, [ %g0 ] (69)"
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// Set hpstate.red = 0 and hpstate.enb = 1
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rdhpr %hpstate, %l1
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wrhpr %l1, 0x820, %hpstate
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// Initialize Interrupt Queue Registers: Currently disabled in S1 Core
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/*
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wr %g0, 0x25, %asi
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stxa %g0, [0x3c0] %asi
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stxa %g0, [0x3c8] %asi
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stxa %g0, [0x3d0] %asi
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stxa %g0, [0x3d8] %asi
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stxa %g0, [0x3e0] %asi
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stxa %g0, [0x3e8] %asi
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stxa %g0, [0x3f0] %asi
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stxa %g0, [0x3f8] %asi
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wrpr 0, %tl
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wrpr 0, %g0, %gl
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wr %g0, cregs_fprs_imm, %fprs
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wr %g0, cregs_ccr_imm, %ccr
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wr %g0, cregs_asi_imm, %asi
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setx cregs_tick_r64, %g1, %g2
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// FIXME set other ticks also
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wrpr %g2, %tick
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setx cregs_stick_r64, %g1, %g2
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wr %g2, %g0, %sys_tick
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mov 0x1, %g2
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sllx %g2, 63, %g2
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wr %g2, %g0, %tick_cmpr
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wr %g2, %g0, %sys_tick_cmpr
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wrhpr %g2, %g0, %hsys_tick_cmpr
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mov %g0, %y
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wrpr cregs_pil_imm, %pil
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wrpr cregs_cwp_imm, %cwp
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wrpr cregs_cansave_imm, %cansave
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wrpr cregs_canrestore_imm, %canrestore
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wrpr cregs_otherwin_imm, %otherwin
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wrpr cregs_cleanwin_imm, %cleanwin
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wrpr cregs_wstate_imm, %wstate
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*/
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// Clear L1-icache and L1-dcache SFSR
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mov 0x18, %g1
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stxa %g0, [%g0 + %g1] 0x50
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stxa %g0, [%g0 + %g1] 0x58
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// Enable error trap
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setx cregs_sparc_error_en_reg_r64, %g1, %l1 // aka "mov 3, %l1"
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stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG // aka "stxa %l1, [%g0] (75)"
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// Enable L2-ucache error trap: Unused in S1 Core
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/*
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setx cregs_l2_error_en_reg_r64, %g1, %l1
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mov 0xaa, %g1
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sllx %g1, 32, %g1
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stx %l1, [%g1 + 0x00]
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stx %l1, [%g1 + 0x40]
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stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0xc0]
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*/
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// Load Partition ID
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rd %asr26, %l1
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set 0x0300, %g1 // aka "sethi %hi(0x1c00), %g1" "or %g1, 0x300, %g1"
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and %l1, %g1, %l1
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srlx %l1, 8, %l1 // %l1 has thread ID
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setx part_id_list, %g1, %g2
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// this instruction expands as
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// "sethi %hi(0), %g1"
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// "sethi %hi(0x4c000), %g2"
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// "mov %g1, %g1"
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// "mov %g2, %g2"
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// "sllx %g1, 0x20, %g1"
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// "or %g2, %g1, %g2"
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sllx %l1, 3, %l1 // offset - partition list
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ldx [%g2 + %l1], %g2 // %g2 contains partition ID
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mov 0x80, %g1
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stxa %g2, [%g1] 0x58
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// Set Hypervisor Trap Base Address
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setx HV_TRAP_BASE_PA, %l0, %l7 // sethi %hi(0x80000), %l7
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wrhpr %l7, %g0, %htba
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// Load TSB config/base from memory and write to corresponding ASI's
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// set tsb-reg (4 at present) for one partition
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// 2 i-config, 2-dconfig
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setx tsb_config_base_list, %l0, %g1
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// this instructions expands as
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// sethi %hi(0), %l0
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// sethi %hi(0x4c000), %g1
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// mov %l0, %l0
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// or %g1, 0x140, %g1
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// sllx %l0, 0x20, %l0
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// or %g1, %l0, %g1
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sllx %g2, 7, %g2 // %g2 contains offset to tsb_config_base_list
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add %g1, %g2, %g1 // %g1 contains pointer to tsb_config_base_list
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// IMMU_CXT_Z_CONFIG (0x37, VA=0x00)
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ldx [%g1], %l1
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stxa %l1, [%g0] 0x37
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// IMMU_CXT_NZ_CONFIG (0x3f, VA=0x00)
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ldx [%g1+8], %l1
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stxa %l1, [%g0] 0x3f
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// IMMU_CXT_Z_PS0_TSB (0x35, VA=0x0)
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// IMMU_CXT_Z_PS1_TSB (0x36, VA=0x0)
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ldx [%g1+16], %l1
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stxa %l1, [%g0] 0x35
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ldx [%g1+32], %l1
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stxa %l1, [%g0] 0x36
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// IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)
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// IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)
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ldx [%g1+24], %l1
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stxa %l1, [%g0] 0x3d
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ldx [%g1+40], %l1
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stxa %l1, [%g0] 0x3e
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// DMMU_CXT_Z_CONFIG (0x33, VA=0x00)
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ldx [%g1+64], %l1
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stxa %l1, [%g0] 0x33
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// DMMU_CXT_NZ_CONFIG (0x3b, VA=0x00)
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ldx [%g1+72], %l1
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stxa %l1, [%g0] 0x3b
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// DMMU_CXT_Z_PS0_TSB (0x31, VA=0x00)
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// DMMU_CXT_Z_PS1_TSB (0x32, VA=0x00)
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ldx [%g1+80], %l1
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stxa %l1, [%g0] 0x31
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ldx [%g1+96], %l1
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stxa %l1, [%g0] 0x32
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// DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)
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// DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)
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ldx [%g1+88], %l1
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stxa %l1, [%g0] 0x39
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ldx [%g1+104], %l1
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stxa %l1, [%g0] 0x3a
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// Demap all itlb and dtlb
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mov 0x80, %o2
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stxa %g0, [%o2] 0x57
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stxa %g0, [%o2] 0x5f
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// Initialize primary context register
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mov 0x8, %l1
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stxa %g0, [%l1] 0x21
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// Initialize secondary context register
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mov 0x10, %l1
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stxa %g0, [%l1] 0x21
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// Initialize dtsb entry for i context zero ps0, ps1
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// Set LSU Control Register to enable icache, dcache, immu, dmmu
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setx cregs_lsu_ctl_reg_r64, %g1, %l1 // aka "mov 0xf, %l1"
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stxa %l1, [%g0] ASI_LSU_CTL_REG // aka "stxa %l1, [%g0] (69)"
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setx HPriv_Reset_Handler, %g1, %g2
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// this instructions expands as
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// sethi %hi(0), %g1
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// sethi %hi(0x144000), %g2
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// mov %g1, %g1
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// mov %g2, %g2
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// sllx %g1, 0x20, %g1
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// or %g2, %g1, %g2
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rdhpr %hpstate, %g3
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wrpr 1, %tl
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setx cregs_htstate_r64, %g1, %g4 // aka "clr %g4"
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wrhpr %g4, %g0, %htstate
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wrpr 0, %tl
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mov 0x0, %o0 // aka "clr %o0", don't delete since used in customized IMMU miss trap
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jmp %g2
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wrhpr %g0, 0x800, %hpstate
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nop
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nop
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