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/*
 * Simply RISC S1 Core - Boot code
 *
 * Cutdown version from the original OpenSPARC T1:
 *
 *   $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
 *
 * Main changes:
 * - L1 and L2 cache handling are not enabled;
 * - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
 *
 * Sun Microsystems' copyright notices follow:
 */
 
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: hred_reset_handler.s
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
 
#include "defines.h"
 
        !! Enable L2-ucache: Unused in S1 Core
/*
        setx    cregs_l2_ctl_reg_r64, %g1, %l1                          !! aka "wr  %g0, 5, %asr26" "clr  %l1"
        mov     0xa9, %g1
        sllx    %g1, 32, %g1
 
        stx     %l1, [%g1 + 0x00]
        stx     %l1, [%g1 + 0x40]
        stx     %l1, [%g1 + 0x80]
        stx     %l1, [%g1 + 0xc0]
*/
 
        !! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
        setx    cregs_lsu_diag_reg_r64, %g1, %l1                                !! aka "clr  %l1"
        mov     0x10, %g1
        stxa %l1, [%g1] (66)                                                    !! aka "stxa    %l1, [%g1] ASI_LSU_DIAG_REG"
 
        !! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core
/*
        setx    (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1  !! aka "mov  3, %l1"
        stxa  %l1, [ %g0 ] (69)                                                 !! aka "stxa    %l1, [%g0] ASI_LSU_CTL_REG"
*/
        !! Set hpstate.red = 0 and hpstate.enb = 1
        rdhpr   %hpstate, %l1
        wrhpr   %l1, 0x820, %hpstate
 
        !! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
/*
        wr %g0, 0x25, %asi
 
        stxa %g0, [0x3c0] %asi
        stxa %g0, [0x3c8] %asi
        stxa %g0, [0x3d0] %asi
        stxa %g0, [0x3d8] %asi
 
        stxa %g0, [0x3e0] %asi
        stxa %g0, [0x3e8] %asi
        stxa %g0, [0x3f0] %asi
        stxa %g0, [0x3f8] %asi
 
        wrpr    0, %tl
        wrpr    0, %g0, %gl
        wr      %g0, cregs_fprs_imm, %fprs
        wr      %g0, cregs_ccr_imm, %ccr
 
        wr      %g0, cregs_asi_imm, %asi
        setx    cregs_tick_r64, %g1, %g2
        !! FIXME set other ticks also
        wrpr    %g2, %tick
        setx    cregs_stick_r64, %g1, %g2
 
        wr      %g2, %g0, %sys_tick
        mov     0x1, %g2
        sllx    %g2, 63, %g2
        wr      %g2, %g0, %tick_cmpr
 
        wr      %g2, %g0, %sys_tick_cmpr
        wrhpr   %g2, %g0, %hsys_tick_cmpr
        mov     %g0, %y
        wrpr    cregs_pil_imm, %pil
 
        wrpr    cregs_cwp_imm, %cwp
        wrpr    cregs_cansave_imm, %cansave
        wrpr    cregs_canrestore_imm, %canrestore
        wrpr    cregs_otherwin_imm, %otherwin
 
        wrpr    cregs_cleanwin_imm, %cleanwin
        wrpr    cregs_wstate_imm, %wstate
*/
 
        !! Clear L1-icache and L1-dcache SFSR
        mov     0x18, %g1
        stxa    %g0, [%g0 + %g1] 0x50
        stxa    %g0, [%g0 + %g1] 0x58
 
        !! Enable error trap
        setx    cregs_sparc_error_en_reg_r64, %g1, %l1                  !! aka "mov  3, %l1"
        stxa  %l1, [%g0] (75)                                           !! aka "stxa    %l1, [%g0] ASI_SPARC_ERROR_EN_REG"
 
        !! Enable L2-ucache error trap: Unused in S1 Core
/*
        setx    cregs_l2_error_en_reg_r64, %g1, %l1
 
        mov     0xaa, %g1
        sllx    %g1, 32, %g1
        stx     %l1, [%g1 + 0x00]
        stx     %l1, [%g1 + 0x40]
 
        stx     %l1, [%g1 + 0x80]
        stx     %l1, [%g1 + 0xc0]
*/
 
        !! Load Partition ID
        rd      %asr26, %l1
        set     0x0300, %g1                             !! aka "sethi %hi(0x1c00), %g1" "or  %g1, 0x300, %g1"
        and     %l1, %g1, %l1
        srlx    %l1, 8, %l1                             !! %l1 has thread ID
 
        setx    part_id_list, %g1, %g2
        !! this instruction expands as
        !! "sethi  %hi(0), %g1"
        !! "sethi  %hi(0x4c000), %g2"
        !! "mov  %g1, %g1"
        !! "mov  %g2, %g2"
        !! "sllx  %g1, 0x20, %g1"
        !! "or  %g2, %g1, %g2"
 
        sllx    %l1, 3, %l1                                                     !! offset - partition list
        ldx     [%g2 + %l1], %g2                                                !! %g2 contains partition ID
        mov     0x80, %g1
        stxa    %g2, [%g1] 0x58
 
        !! Set Hypervisor Trap Base Address
        setx HV_TRAP_BASE_PA, %l0, %l7                                          !! sethi %hi(0x80000), %l7
        wrhpr %l7, %g0, %htba
 
        !! Load TSB config/base from memory and write to corresponding ASI's
        !! set tsb-reg (4 at present) for one partition
        !! 2 i-config, 2-dconfig
 
        setx    tsb_config_base_list, %l0, %g1
        !! this instructions expands as
        !! sethi  %hi(0), %l0
        !! sethi  %hi(0x4c000), %g1
        !! mov  %l0, %l0
        !! or  %g1, 0x140, %g1
        !! sllx  %l0, 0x20, %l0
        !! or  %g1, %l0, %g1
 
        sllx    %g2, 7, %g2                                     !! %g2 contains offset to tsb_config_base_list
        add     %g1, %g2, %g1                                   !! %g1 contains pointer to tsb_config_base_list
 
        !! IMMU_CXT_Z_CONFIG   (0x37, VA=0x00)
        ldx     [%g1], %l1
        stxa    %l1, [%g0] 0x37
 
        !! IMMU_CXT_NZ_CONFIG  (0x3f, VA=0x00)
        ldx     [%g1+8], %l1
        stxa    %l1, [%g0] 0x3f
 
        !! IMMU_CXT_Z_PS0_TSB  (0x35, VA=0x0)
        !! IMMU_CXT_Z_PS1_TSB  (0x36, VA=0x0)
        ldx     [%g1+16], %l1
        stxa    %l1, [%g0] 0x35
        ldx     [%g1+32], %l1
        stxa    %l1, [%g0] 0x36
 
        !! IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)
        !! IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)
        ldx     [%g1+24], %l1
        stxa    %l1, [%g0] 0x3d
        ldx     [%g1+40], %l1
        stxa    %l1, [%g0] 0x3e
 
        !! DMMU_CXT_Z_CONFIG   (0x33, VA=0x00)
        ldx     [%g1+64], %l1
        stxa    %l1, [%g0] 0x33
 
        !! DMMU_CXT_NZ_CONFIG  (0x3b, VA=0x00)
        ldx     [%g1+72], %l1
        stxa    %l1, [%g0] 0x3b
 
        !! DMMU_CXT_Z_PS0_TSB  (0x31, VA=0x00)
        !! DMMU_CXT_Z_PS1_TSB  (0x32, VA=0x00)
        ldx     [%g1+80], %l1
        stxa    %l1, [%g0] 0x31
        ldx     [%g1+96], %l1
        stxa    %l1, [%g0] 0x32
 
        !! DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)
        !! DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)
        ldx     [%g1+88], %l1
        stxa    %l1, [%g0] 0x39
        ldx     [%g1+104], %l1
        stxa    %l1, [%g0] 0x3a
 
        !! Demap all itlb and dtlb
        mov     0x80, %o2
        stxa    %g0, [%o2] 0x57
        stxa    %g0, [%o2] 0x5f
 
        !! Initialize primary context register
        mov 0x8, %l1
        stxa %g0, [%l1] 0x21
 
        !! Initialize secondary context register
        mov 0x10, %l1
        stxa %g0, [%l1] 0x21
 
        !! Initialize dtsb entry for i context zero ps0, ps1
/*
        !! Set LSU Control Register to enable icache, dcache, immu, dmmu
        setx    cregs_lsu_ctl_reg_r64, %g1, %l1                                 !! aka "mov  0xf, %l1"
*/
        !! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache
        mov  0xc, %l1
        stxa  %l1, [%g0] (69)                                                   !! aka "stxa    %l1, [%g0] ASI_LSU_CTL_REG"
 
        setx    HPriv_Reset_Handler, %g1, %g2
        !! this instructions expands as
        !! sethi  %hi(0), %g1
        !! sethi  %hi(0x144000), %g2
        !! mov  %g1, %g1
        !! mov  %g2, %g2
        !! sllx  %g1, 0x20, %g1
        !! or  %g2, %g1, %g2
 
        rdhpr   %hpstate, %g3
        wrpr    1, %tl
        setx    cregs_htstate_r64, %g1, %g4                     !! aka "clr  %g4"
        wrhpr   %g4, %g0, %htstate
        wrpr    0, %tl
        mov     0x0, %o0                !! aka "clr %o0", don't delete since used in customized IMMU miss trap
        jmp     %g2
        wrhpr   %g0, 0x800, %hpstate
        nop
        nop
 
 

Line No.	Rev	Author	Line
1	32	fafa1971	`/*`
2			`* Simply RISC S1 Core - Boot code`
3			`*`
4			`* Cutdown version from the original OpenSPARC T1:`
5			`*`
6			`* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s`
7			`*`
8			`* Main changes:`
9	36	fafa1971	`* - L1 and L2 cache handling are not enabled;`
10	32	fafa1971	`* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.`
11			`*`
12			`* Sun Microsystems' copyright notices follow:`
13			`*/`
14
15			`/*`
16			`* ========== Copyright Header Begin ==========================================`
17			`*`
18			`* OpenSPARC T1 Processor File: hred_reset_handler.s`
19			`* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
20			`* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
21			`*`
22			`* The above named program is free software; you can redistribute it and/or`
23			`* modify it under the terms of the GNU General Public`
24			`* License version 2 as published by the Free Software Foundation.`
25			`*`
26			`* The above named program is distributed in the hope that it will be`
27			`* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
28			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
29			`* General Public License for more details.`
30			`*`
31			`* You should have received a copy of the GNU General Public`
32			`* License along with this work; if not, write to the Free Software`
33			`* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
34			`*`
35			`* ========== Copyright Header End ============================================`
36			`*/`
37
38	33	fafa1971	`#include "defines.h"`
39
40	35	fafa1971	`!! Enable L2-ucache: Unused in S1 Core`
41	32	fafa1971	`/*`
42	35	fafa1971	`setx cregs_l2_ctl_reg_r64, %g1, %l1 !! aka "wr %g0, 5, %asr26" "clr %l1"`
43	32	fafa1971	`mov 0xa9, %g1`
44			`sllx %g1, 32, %g1`
45
46			`stx %l1, [%g1 + 0x00]`
47			`stx %l1, [%g1 + 0x40]`
48			`stx %l1, [%g1 + 0x80]`
49			`stx %l1, [%g1 + 0xc0]`
50			`*/`
51
52	35	fafa1971	`!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache`
53			`setx cregs_lsu_diag_reg_r64, %g1, %l1 !! aka "clr %l1"`
54	32	fafa1971	`mov 0x10, %g1`
55	36	fafa1971	`stxa %l1, [%g1] (66) !! aka "stxa %l1, [%g1] ASI_LSU_DIAG_REG"`
56	32	fafa1971
57	36	fafa1971	`!! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core`
58			`/*`
59	35	fafa1971	`setx (CREGS_LSU_CTL_REG_IC \| (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"`
60	36	fafa1971	`stxa %l1, [ %g0 ] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"`
61			`*/`
62	35	fafa1971	`!! Set hpstate.red = 0 and hpstate.enb = 1`
63	32	fafa1971	`rdhpr %hpstate, %l1`
64			`wrhpr %l1, 0x820, %hpstate`
65
66	35	fafa1971	`!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core`
67	32	fafa1971	`/*`
68			`wr %g0, 0x25, %asi`
69
70			`stxa %g0, [0x3c0] %asi`
71			`stxa %g0, [0x3c8] %asi`
72			`stxa %g0, [0x3d0] %asi`
73			`stxa %g0, [0x3d8] %asi`
74
75			`stxa %g0, [0x3e0] %asi`
76			`stxa %g0, [0x3e8] %asi`
77			`stxa %g0, [0x3f0] %asi`
78			`stxa %g0, [0x3f8] %asi`
79
80			`wrpr 0, %tl`
81			`wrpr 0, %g0, %gl`
82			`wr %g0, cregs_fprs_imm, %fprs`
83			`wr %g0, cregs_ccr_imm, %ccr`
84
85			`wr %g0, cregs_asi_imm, %asi`
86			`setx cregs_tick_r64, %g1, %g2`
87	35	fafa1971	`!! FIXME set other ticks also`
88	32	fafa1971	`wrpr %g2, %tick`
89			`setx cregs_stick_r64, %g1, %g2`
90
91			`wr %g2, %g0, %sys_tick`
92			`mov 0x1, %g2`
93			`sllx %g2, 63, %g2`
94			`wr %g2, %g0, %tick_cmpr`
95
96			`wr %g2, %g0, %sys_tick_cmpr`
97			`wrhpr %g2, %g0, %hsys_tick_cmpr`
98			`mov %g0, %y`
99			`wrpr cregs_pil_imm, %pil`
100
101			`wrpr cregs_cwp_imm, %cwp`
102			`wrpr cregs_cansave_imm, %cansave`
103			`wrpr cregs_canrestore_imm, %canrestore`
104			`wrpr cregs_otherwin_imm, %otherwin`
105
106			`wrpr cregs_cleanwin_imm, %cleanwin`
107			`wrpr cregs_wstate_imm, %wstate`
108			`*/`
109
110	35	fafa1971	`!! Clear L1-icache and L1-dcache SFSR`
111	32	fafa1971	`mov 0x18, %g1`
112			`stxa %g0, [%g0 + %g1] 0x50`
113			`stxa %g0, [%g0 + %g1] 0x58`
114
115	35	fafa1971	`!! Enable error trap`
116			`setx cregs_sparc_error_en_reg_r64, %g1, %l1 !! aka "mov 3, %l1"`
117	36	fafa1971	`stxa %l1, [%g0] (75) !! aka "stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG"`
118	32	fafa1971
119	35	fafa1971	`!! Enable L2-ucache error trap: Unused in S1 Core`
120	32	fafa1971	`/*`
121			`setx cregs_l2_error_en_reg_r64, %g1, %l1`
122
123			`mov 0xaa, %g1`
124			`sllx %g1, 32, %g1`
125			`stx %l1, [%g1 + 0x00]`
126			`stx %l1, [%g1 + 0x40]`
127
128			`stx %l1, [%g1 + 0x80]`
129			`stx %l1, [%g1 + 0xc0]`
130			`*/`
131
132	35	fafa1971	`!! Load Partition ID`
133	32	fafa1971	`rd %asr26, %l1`
134	35	fafa1971	`set 0x0300, %g1 !! aka "sethi %hi(0x1c00), %g1" "or %g1, 0x300, %g1"`
135	32	fafa1971	`and %l1, %g1, %l1`
136	35	fafa1971	`srlx %l1, 8, %l1 !! %l1 has thread ID`
137	32	fafa1971
138			`setx part_id_list, %g1, %g2`
139	35	fafa1971	`!! this instruction expands as`
140			`!! "sethi %hi(0), %g1"`
141			`!! "sethi %hi(0x4c000), %g2"`
142			`!! "mov %g1, %g1"`
143			`!! "mov %g2, %g2"`
144			`!! "sllx %g1, 0x20, %g1"`
145			`!! "or %g2, %g1, %g2"`
146	32	fafa1971
147	35	fafa1971	`sllx %l1, 3, %l1 !! offset - partition list`
148			`ldx [%g2 + %l1], %g2 !! %g2 contains partition ID`
149	32	fafa1971	`mov 0x80, %g1`
150			`stxa %g2, [%g1] 0x58`
151
152	35	fafa1971	`!! Set Hypervisor Trap Base Address`
153			`setx HV_TRAP_BASE_PA, %l0, %l7 !! sethi %hi(0x80000), %l7`
154	32	fafa1971	`wrhpr %l7, %g0, %htba`
155
156	35	fafa1971	`!! Load TSB config/base from memory and write to corresponding ASI's`
157			`!! set tsb-reg (4 at present) for one partition`
158			`!! 2 i-config, 2-dconfig`
159	32	fafa1971
160			`setx tsb_config_base_list, %l0, %g1`
161	35	fafa1971	`!! this instructions expands as`
162			`!! sethi %hi(0), %l0`
163			`!! sethi %hi(0x4c000), %g1`
164			`!! mov %l0, %l0`
165			`!! or %g1, 0x140, %g1`
166			`!! sllx %l0, 0x20, %l0`
167			`!! or %g1, %l0, %g1`
168	32	fafa1971
169	35	fafa1971	`sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list`
170			`add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list`
171	32	fafa1971
172	35	fafa1971	`!! IMMU_CXT_Z_CONFIG (0x37, VA=0x00)`
173	32	fafa1971	`ldx [%g1], %l1`
174			`stxa %l1, [%g0] 0x37`
175
176	35	fafa1971	`!! IMMU_CXT_NZ_CONFIG (0x3f, VA=0x00)`
177	32	fafa1971	`ldx [%g1+8], %l1`
178			`stxa %l1, [%g0] 0x3f`
179
180	35	fafa1971	`!! IMMU_CXT_Z_PS0_TSB (0x35, VA=0x0)`
181			`!! IMMU_CXT_Z_PS1_TSB (0x36, VA=0x0)`
182	32	fafa1971	`ldx [%g1+16], %l1`
183			`stxa %l1, [%g0] 0x35`
184			`ldx [%g1+32], %l1`
185			`stxa %l1, [%g0] 0x36`
186
187	35	fafa1971	`!! IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)`
188			`!! IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)`
189	32	fafa1971	`ldx [%g1+24], %l1`
190			`stxa %l1, [%g0] 0x3d`
191			`ldx [%g1+40], %l1`
192			`stxa %l1, [%g0] 0x3e`
193
194	35	fafa1971	`!! DMMU_CXT_Z_CONFIG (0x33, VA=0x00)`
195	32	fafa1971	`ldx [%g1+64], %l1`
196			`stxa %l1, [%g0] 0x33`
197
198	35	fafa1971	`!! DMMU_CXT_NZ_CONFIG (0x3b, VA=0x00)`
199	32	fafa1971	`ldx [%g1+72], %l1`
200			`stxa %l1, [%g0] 0x3b`
201
202	35	fafa1971	`!! DMMU_CXT_Z_PS0_TSB (0x31, VA=0x00)`
203			`!! DMMU_CXT_Z_PS1_TSB (0x32, VA=0x00)`
204	32	fafa1971	`ldx [%g1+80], %l1`
205			`stxa %l1, [%g0] 0x31`
206			`ldx [%g1+96], %l1`
207			`stxa %l1, [%g0] 0x32`
208
209	35	fafa1971	`!! DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)`
210			`!! DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)`
211	32	fafa1971	`ldx [%g1+88], %l1`
212			`stxa %l1, [%g0] 0x39`
213			`ldx [%g1+104], %l1`
214			`stxa %l1, [%g0] 0x3a`
215
216	35	fafa1971	`!! Demap all itlb and dtlb`
217	32	fafa1971	`mov 0x80, %o2`
218			`stxa %g0, [%o2] 0x57`
219			`stxa %g0, [%o2] 0x5f`
220
221	35	fafa1971	`!! Initialize primary context register`
222	32	fafa1971	`mov 0x8, %l1`
223			`stxa %g0, [%l1] 0x21`
224
225	35	fafa1971	`!! Initialize secondary context register`
226	32	fafa1971	`mov 0x10, %l1`
227			`stxa %g0, [%l1] 0x21`
228
229	35	fafa1971	`!! Initialize dtsb entry for i context zero ps0, ps1`
230	36	fafa1971	`/*`
231	35	fafa1971	`!! Set LSU Control Register to enable icache, dcache, immu, dmmu`
232			`setx cregs_lsu_ctl_reg_r64, %g1, %l1 !! aka "mov 0xf, %l1"`
233	36	fafa1971	`*/`
234			`!! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache`
235			`mov 0xc, %l1`
236			`stxa %l1, [%g0] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"`
237	32	fafa1971
238			`setx HPriv_Reset_Handler, %g1, %g2`
239	35	fafa1971	`!! this instructions expands as`
240			`!! sethi %hi(0), %g1`
241			`!! sethi %hi(0x144000), %g2`
242			`!! mov %g1, %g1`
243			`!! mov %g2, %g2`
244			`!! sllx %g1, 0x20, %g1`
245			`!! or %g2, %g1, %g2`
246	32	fafa1971
247			`rdhpr %hpstate, %g3`
248			`wrpr 1, %tl`
249	35	fafa1971	`setx cregs_htstate_r64, %g1, %g4 !! aka "clr %g4"`
250	32	fafa1971	`wrhpr %g4, %g0, %htstate`
251			`wrpr 0, %tl`
252	35	fafa1971	`mov 0x0, %o0 !! aka "clr %o0", don't delete since used in customized IMMU miss trap`
253	32	fafa1971	`jmp %g2`
254			`wrhpr %g0, 0x800, %hpstate`
255			`nop`
256			`nop`
257
258

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