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/*
 * Simply RISC S1 Core - Boot code
 *
 * Cutdown version from the original OpenSPARC T1:
 *
 *   $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
 *
 * Main changes:
 * - L1 and L2 cache handling are not enabled;
 * - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
 *
 * Sun Microsystems' copyright notices follow:
 */
 
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: hred_reset_handler.s
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
 
        !! Enable L2-ucache: Unused in S1 Core
/*
        setx    cregs_l2_ctl_reg_r64, %g1, %l1                          !! aka "wr  %g0, 5, %asr26" "clr  %l1"
        mov     0xa9, %g1
        sllx    %g1, 32, %g1
 
        stx     %l1, [%g1 + 0x00]
        stx     %l1, [%g1 + 0x40]
        stx     %l1, [%g1 + 0x80]
        stx     %l1, [%g1 + 0xc0]
*/
 
        !! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
 
        !!setx  cregs_lsu_diag_reg_r64, %g1, %l1                !!ho sostituito questa istruzione con la sua espansione (!! aka "clr  %l1")
        sethi %hh(0x0),%g1
        or    %g1,%hm(0x0),%g1
        sllx  %g1,32,%g1
        sethi %hi(0x0),%l1
        or    %l1,%g1,%l1
        or    %l1,%lo(0x0),%l1
 
        mov     0x10, %g1
        stxa %l1, [%g1] (66)                                                    !! aka "stxa    %l1, [%g1] ASI_LSU_DIAG_REG"
 
        !! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core
/*
        setx    (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1  !! aka "mov  3, %l1"
        stxa  %l1, [ %g0 ] (69)                                                 !! aka "stxa    %l1, [%g0] ASI_LSU_CTL_REG"
*/
        !! Set hpstate.red = 0 and hpstate.enb = 1
        rdhpr   %hpstate, %l1
        and %l1,0x820,%l2
        xor %l2,0x800,%l2
        wrhpr %l1,%l2,%hpstate          !!questo meccanismo "dovrebbe" assicurarni red=0 enb=1
 
        !!wrhpr %l1, 0x820, %hpstate    !! in questo modo hpstate.red=1 altrimenti dovremmo usare 0x8000 inoltre troviamo red=1 e hpriv=0
                                        !! cmq dipende da l1, dovrebbe fare l1 xor 100000100000
                                        !!stiamo presumendo che red=1 e enb=0 precedentemente
 
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!   !!momentaneamente ho tolto le istruzioni che ho aggiunto
!!aggiunta dal file hboot_tlb_init.s
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
 
! init all itlb entries
    !!    mov   0x30, %g1
        !!mov   %g0, %g2
!!itlb_init_loop:
        !!stxa  %g0, [ %g1 ] 0x50
        !!stxa  %g0, [ %g2 ] 0x55 !!pulisce data e tag entry del buffer per TLB
 
        !!add   %g2, 8, %g2     !!g2= somma 8 (byte) alla volta  (64 bit)
        !!cmp   %g2, 0x200      !!confronta con 512  (512*8=4096=0x1000), ma al max VA=0x7F8
 
        !!bne   itlb_init_loop
        !!nop
! init all dtlb entries
        !!mov   0x30, %g1
        !!mov   %g0, %g2
!!dtlb_init_loop:
        !!stxa  %g0, [ %g1 ] 0x58
        !!stxa  %g0, [ %g2 ] 0x5d
 
        !!add   %g2, 8, %g2
        !!cmp   %g2, 0x200
        !!bne   dtlb_init_loop
        !!nop
 
 
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
! Clear itlb/dtlb valid
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
        !!stxa  %g0, [%g0] 0x60         ! ASI_ITLB_INVALIDATE_ALL
        !!mov   0x8, %g1
        !!stxa  %g0, [%g0 + %g1] 0x60   ! ASI_DTLB_INVALIDATE_ALL
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!fine aggiunta
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
 
 
 
        !! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
/*
        wr %g0, 0x25, %asi
 
        stxa %g0, [0x3c0] %asi
        stxa %g0, [0x3c8] %asi
        stxa %g0, [0x3d0] %asi
        stxa %g0, [0x3d8] %asi
 
        stxa %g0, [0x3e0] %asi
        stxa %g0, [0x3e8] %asi
        stxa %g0, [0x3f0] %asi
        stxa %g0, [0x3f8] %asi
 
        wrpr    0, %tl
        wrpr    0, %g0, %gl
        wr      %g0, cregs_fprs_imm, %fprs
        wr      %g0, cregs_ccr_imm, %ccr
 
        wr      %g0, cregs_asi_imm, %asi
        setx    cregs_tick_r64, %g1, %g2
        !! FIXME set other ticks also
        wrpr    %g2, %tick
        setx    cregs_stick_r64, %g1, %g2
 
        wr      %g2, %g0, %sys_tick
        mov     0x1, %g2
        sllx    %g2, 63, %g2
        wr      %g2, %g0, %tick_cmpr
 
        wr      %g2, %g0, %sys_tick_cmpr
        wrhpr   %g2, %g0, %hsys_tick_cmpr
        mov     %g0, %y
        wrpr    cregs_pil_imm, %pil
 
        wrpr    cregs_cwp_imm, %cwp
        wrpr    cregs_cansave_imm, %cansave
        wrpr    cregs_canrestore_imm, %canrestore
        wrpr    cregs_otherwin_imm, %otherwin
 
        wrpr    cregs_cleanwin_imm, %cleanwin
        wrpr    cregs_wstate_imm, %wstate
*/
 
        !! Clear L1-icache and L1-dcache SFSR
        mov     0x18, %g1
        stxa    %g0, [%g0 + %g1] 0x50
        stxa    %g0, [%g0 + %g1] 0x58
 
        !! Enable error trap
        !!setx  cregs_sparc_error_en_reg_r64, %g1, %l1         !!ho sostituito questa istruzione con la sua espansione e costante=3(!!aka "mov  3, %l1")
        sethi %hh(0x3),%g1
        or    %g1,%hm(0x3),%g1
        sllx  %g1,32,%g1
        sethi %hi(0x3),%l1
        or    %l1,%g1,%l1
        or    %l1,%lo(0x3),%l1
        stxa  %l1, [%g0] (75)                                           !! aka "stxa    %l1, [%g0] ASI_SPARC_ERROR_EN_REG"
 
        !! Enable L2-ucache error trap: Unused in S1 Core
/*
        setx    cregs_l2_error_en_reg_r64, %g1, %l1
 
        mov     0xaa, %g1
        sllx    %g1, 32, %g1
        stx     %l1, [%g1 + 0x00]
        stx     %l1, [%g1 + 0x40]
 
        stx     %l1, [%g1 + 0x80]
        stx     %l1, [%g1 + 0xc0]
*/
 
        !! Load Partition ID
        rd      %asr26, %l1
        set     0x0300, %g1                             !! aka "sethi %hi(0x1c00), %g1" "or  %g1, 0x300, %g1"
        and     %l1, %g1, %l1
 
        srlx    %l1, 8, %l1                             !! %l1 has thread ID
 
        !!setx  part_id_list, %g1, %g2
        !! this instruction expands as
         sethi  %hi(0), %g1
         sethi  %hi(0x4c000), %g2       !! THIS INSTRUCTION CONTAINS THE ADDRESS IN MEMORY
         mov  %g1, %g1
         mov  %g2, %g2
         sllx  %g1, 0x20, %g1
         or  %g2, %g1, %g2
 
        sllx    %l1, 3, %l1                                                     !! offset - partition list
        ldx     [%g2 + %l1], %g2                                                !! %g2 contains partition ID
        mov     0x80, %g1
        stxa    %g2, [%g1] 0x58         !! BY FF - AFTER THIS INSTRUCTION WE GET TWO CONSECUTIVE ACCESSES
 
        !! Set Hypervisor Trap Base Address
        !!setx HV_TRAP_BASE_PA, %l0, %l7                                !!sostituita con la sua espansione e costante=0x80000(!!sethi %hi(0x80000), %l7)
        sethi %hh(0x80000),%g1
        or    %g1,%hm(0x80000),%g1
        sllx  %g1,32,%g1
        sethi %hi(0x80000),%l1
        or    %l1,%g1,%l1
        or    %l1,%lo(0x80000),%l1
 
        wrhpr %l7, %g0, %htba
 
        !! Load TSB config/base from memory and write to corresponding ASI's
        !! set tsb-reg (4 at present) for one partition
        !! 2 i-config, 2-dconfig
 
        !!setx  tsb_config_base_list, %l0, %g1          !!sostituita con le successive istruzioni
        !! this instructions expands as
         sethi  %hi(0), %l0
         sethi  %hi(0x4c000), %g1
         mov  %l0, %l0
         or  %g1, 0x140, %g1
         sllx  %l0, 0x20, %l0
         or  %g1, %l0, %g1
 
        sllx    %g2, 7, %g2                                     !! %g2 contains offset to tsb_config_base_list
        add     %g1, %g2, %g1                                   !! %g1 contains pointer to tsb_config_base_list
 
        !! IMMU_CXT_Z_CONFIG   (0x37, VA=0x00)
        ldx     [%g1], %l1
        stxa    %l1, [%g0] 0x37
 
        !! IMMU_CXT_NZ_CONFIG  (0x3f, VA=0x00)
        ldx     [%g1+8], %l1
        stxa    %l1, [%g0] 0x3f
 
        !! IMMU_CXT_Z_PS0_TSB  (0x35, VA=0x0)
        !! IMMU_CXT_Z_PS1_TSB  (0x36, VA=0x0)
        ldx     [%g1+16], %l1
        stxa    %l1, [%g0] 0x35
        ldx     [%g1+32], %l1
        stxa    %l1, [%g0] 0x36
 
        !! IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)
        !! IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)
        ldx     [%g1+24], %l1
        stxa    %l1, [%g0] 0x3d
        ldx     [%g1+40], %l1
        stxa    %l1, [%g0] 0x3e
 
        !! DMMU_CXT_Z_CONFIG   (0x33, VA=0x00)
        ldx     [%g1+64], %l1
        stxa    %l1, [%g0] 0x33
 
        !! DMMU_CXT_NZ_CONFIG  (0x3b, VA=0x00)
        ldx     [%g1+72], %l1
        stxa    %l1, [%g0] 0x3b
 
        !! DMMU_CXT_Z_PS0_TSB  (0x31, VA=0x00)
        !! DMMU_CXT_Z_PS1_TSB  (0x32, VA=0x00)
        ldx     [%g1+80], %l1
        stxa    %l1, [%g0] 0x31
        ldx     [%g1+96], %l1
        stxa    %l1, [%g0] 0x32
 
        !! DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)
        !! DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)
        ldx     [%g1+88], %l1
        stxa    %l1, [%g0] 0x39
        ldx     [%g1+104], %l1
        stxa    %l1, [%g0] 0x3a
 
        !! Demap all itlb and dtlb
        mov     0x80, %o2
        stxa    %g0, [%o2] 0x57
        stxa    %g0, [%o2] 0x5f
 
 
 
        !! Initialize primary context register
        mov 0x8, %l1
        stxa %g0, [%l1] 0x21
 
        !! Initialize secondary context register
        mov 0x10, %l1
        stxa %g0, [%l1] 0x21
 
        !! Initialize dtsb entry for i context zero ps0, ps1
/*
        !! Set LSU Control Register to enable icache, dcache, immu, dmmu
        setx    cregs_lsu_ctl_reg_r64, %g1, %l1                                 !! aka "mov  0xf, %l1"
*/
        !! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache
        mov  0xc, %l1
        stxa  %l1, [%g0] (69)                                                   !! aka "stxa    %l1, [%g0] ASI_LSU_CTL_REG"
 
        !!setx  HPriv_Reset_Handler, %g1, %g2
        !! this instructions expands as
         sethi  %hi(0), %g1
         sethi  %hi(0x144000), %g2
         mov  %g1, %g1
         mov  %g2, %g2
         sllx  %g1, 0x20, %g1
         or  %g2, %g1, %g2
 
        rdhpr   %hpstate, %g3
        wrpr    1, %tl
        !!setx  cregs_htstate_r64, %g1, %g4                     !!sostituita con la successiva istruzione (!! aka "clr  %g4")
        sethi %hh(0x0),%g1
        or    %g1,%hm(0x0),%g1
        sllx  %g1,32,%g1
        sethi %hi(0x0),%l1
        or    %l1,%g1,%l1
        or    %l1,%lo(0x0),%l1
 
        wrhpr   %g4, %g0, %htstate
        wrpr    0, %tl
        mov     0x0, %o0                !! aka "clr %o0", don't delete since used in customized IMMU miss trap
        jmp     %g2
        wrhpr   %g0, 0x800, %hpstate
        nop
        nop
 
 

Line No.	Rev	Author	Line
1	32	fafa1971	`/*`
2			`* Simply RISC S1 Core - Boot code`
3			`*`
4			`* Cutdown version from the original OpenSPARC T1:`
5			`*`
6			`* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s`
7			`*`
8			`* Main changes:`
9	36	fafa1971	`* - L1 and L2 cache handling are not enabled;`
10	32	fafa1971	`* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.`
11			`*`
12			`* Sun Microsystems' copyright notices follow:`
13			`*/`
14
15			`/*`
16			`* ========== Copyright Header Begin ==========================================`
17			`*`
18			`* OpenSPARC T1 Processor File: hred_reset_handler.s`
19			`* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
20			`* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
21			`*`
22			`* The above named program is free software; you can redistribute it and/or`
23			`* modify it under the terms of the GNU General Public`
24			`* License version 2 as published by the Free Software Foundation.`
25			`*`
26			`* The above named program is distributed in the hope that it will be`
27			`* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
28			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
29			`* General Public License for more details.`
30			`*`
31			`* You should have received a copy of the GNU General Public`
32			`* License along with this work; if not, write to the Free Software`
33			`* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
34			`*`
35			`* ========== Copyright Header End ============================================`
36			`*/`
37
38	35	fafa1971	`!! Enable L2-ucache: Unused in S1 Core`
39	32	fafa1971	`/*`
40	35	fafa1971	`setx cregs_l2_ctl_reg_r64, %g1, %l1 !! aka "wr %g0, 5, %asr26" "clr %l1"`
41	32	fafa1971	`mov 0xa9, %g1`
42			`sllx %g1, 32, %g1`
43
44			`stx %l1, [%g1 + 0x00]`
45			`stx %l1, [%g1 + 0x40]`
46			`stx %l1, [%g1 + 0x80]`
47			`stx %l1, [%g1 + 0xc0]`
48			`*/`
49
50	35	fafa1971	`!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache`
51	73	fafa1971
52			`!!setx cregs_lsu_diag_reg_r64, %g1, %l1 !!ho sostituito questa istruzione con la sua espansione (!! aka "clr %l1")`
53			`sethi %hh(0x0),%g1`
54			`or %g1,%hm(0x0),%g1`
55			`sllx %g1,32,%g1`
56			`sethi %hi(0x0),%l1`
57			`or %l1,%g1,%l1`
58			`or %l1,%lo(0x0),%l1`
59
60			`mov 0x10, %g1`
61	36	fafa1971	`stxa %l1, [%g1] (66) !! aka "stxa %l1, [%g1] ASI_LSU_DIAG_REG"`
62	32	fafa1971
63	36	fafa1971	`!! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core`
64			`/*`
65	35	fafa1971	`setx (CREGS_LSU_CTL_REG_IC \| (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"`
66	36	fafa1971	`stxa %l1, [ %g0 ] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"`
67			`*/`
68	35	fafa1971	`!! Set hpstate.red = 0 and hpstate.enb = 1`
69	32	fafa1971	`rdhpr %hpstate, %l1`
70	73	fafa1971	`and %l1,0x820,%l2`
71			`xor %l2,0x800,%l2`
72			`wrhpr %l1,%l2,%hpstate !!questo meccanismo "dovrebbe" assicurarni red=0 enb=1`
73
74			`!!wrhpr %l1, 0x820, %hpstate !! in questo modo hpstate.red=1 altrimenti dovremmo usare 0x8000 inoltre troviamo red=1 e hpriv=0`
75			`!! cmq dipende da l1, dovrebbe fare l1 xor 100000100000`
76			`!!stiamo presumendo che red=1 e enb=0 precedentemente`
77
78			`/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!momentaneamente ho tolto le istruzioni che ho aggiunto`
79			`!!aggiunta dal file hboot_tlb_init.s`
80			`!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!`
81
82			`! init all itlb entries`
83			`!! mov 0x30, %g1`
84			`!!mov %g0, %g2`
85			`!!itlb_init_loop:`
86			`!!stxa %g0, [ %g1 ] 0x50`
87			`!!stxa %g0, [ %g2 ] 0x55 !!pulisce data e tag entry del buffer per TLB`
88	32	fafa1971
89	73	fafa1971	`!!add %g2, 8, %g2 !!g2= somma 8 (byte) alla volta (64 bit)`
90			`!!cmp %g2, 0x200 !!confronta con 512 (512*8=4096=0x1000), ma al max VA=0x7F8`
91
92			`!!bne itlb_init_loop`
93			`!!nop`
94			`! init all dtlb entries`
95			`!!mov 0x30, %g1`
96			`!!mov %g0, %g2`
97			`!!dtlb_init_loop:`
98			`!!stxa %g0, [ %g1 ] 0x58`
99			`!!stxa %g0, [ %g2 ] 0x5d`
100
101			`!!add %g2, 8, %g2`
102			`!!cmp %g2, 0x200`
103			`!!bne dtlb_init_loop`
104			`!!nop`
105
106
107			`!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!`
108			`! Clear itlb/dtlb valid`
109			`!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!`
110			`!!stxa %g0, [%g0] 0x60 ! ASI_ITLB_INVALIDATE_ALL`
111			`!!mov 0x8, %g1`
112			`!!stxa %g0, [%g0 + %g1] 0x60 ! ASI_DTLB_INVALIDATE_ALL`
113			`!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!`
114			`!!fine aggiunta`
115			`!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/`
116
117
118
119	35	fafa1971	`!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core`
120	32	fafa1971	`/*`
121			`wr %g0, 0x25, %asi`
122
123			`stxa %g0, [0x3c0] %asi`
124			`stxa %g0, [0x3c8] %asi`
125			`stxa %g0, [0x3d0] %asi`
126			`stxa %g0, [0x3d8] %asi`
127
128			`stxa %g0, [0x3e0] %asi`
129			`stxa %g0, [0x3e8] %asi`
130			`stxa %g0, [0x3f0] %asi`
131			`stxa %g0, [0x3f8] %asi`
132
133			`wrpr 0, %tl`
134			`wrpr 0, %g0, %gl`
135			`wr %g0, cregs_fprs_imm, %fprs`
136			`wr %g0, cregs_ccr_imm, %ccr`
137
138			`wr %g0, cregs_asi_imm, %asi`
139			`setx cregs_tick_r64, %g1, %g2`
140	35	fafa1971	`!! FIXME set other ticks also`
141	32	fafa1971	`wrpr %g2, %tick`
142			`setx cregs_stick_r64, %g1, %g2`
143
144			`wr %g2, %g0, %sys_tick`
145			`mov 0x1, %g2`
146			`sllx %g2, 63, %g2`
147			`wr %g2, %g0, %tick_cmpr`
148
149			`wr %g2, %g0, %sys_tick_cmpr`
150			`wrhpr %g2, %g0, %hsys_tick_cmpr`
151			`mov %g0, %y`
152			`wrpr cregs_pil_imm, %pil`
153
154			`wrpr cregs_cwp_imm, %cwp`
155			`wrpr cregs_cansave_imm, %cansave`
156			`wrpr cregs_canrestore_imm, %canrestore`
157			`wrpr cregs_otherwin_imm, %otherwin`
158
159			`wrpr cregs_cleanwin_imm, %cleanwin`
160			`wrpr cregs_wstate_imm, %wstate`
161			`*/`
162
163	35	fafa1971	`!! Clear L1-icache and L1-dcache SFSR`
164	32	fafa1971	`mov 0x18, %g1`
165			`stxa %g0, [%g0 + %g1] 0x50`
166			`stxa %g0, [%g0 + %g1] 0x58`
167
168	35	fafa1971	`!! Enable error trap`
169	73	fafa1971	`!!setx cregs_sparc_error_en_reg_r64, %g1, %l1 !!ho sostituito questa istruzione con la sua espansione e costante=3(!!aka "mov 3, %l1")`
170			`sethi %hh(0x3),%g1`
171			`or %g1,%hm(0x3),%g1`
172			`sllx %g1,32,%g1`
173			`sethi %hi(0x3),%l1`
174			`or %l1,%g1,%l1`
175			`or %l1,%lo(0x3),%l1`
176	36	fafa1971	`stxa %l1, [%g0] (75) !! aka "stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG"`
177	32	fafa1971
178	35	fafa1971	`!! Enable L2-ucache error trap: Unused in S1 Core`
179	32	fafa1971	`/*`
180			`setx cregs_l2_error_en_reg_r64, %g1, %l1`
181
182			`mov 0xaa, %g1`
183			`sllx %g1, 32, %g1`
184			`stx %l1, [%g1 + 0x00]`
185			`stx %l1, [%g1 + 0x40]`
186
187			`stx %l1, [%g1 + 0x80]`
188			`stx %l1, [%g1 + 0xc0]`
189			`*/`
190
191	35	fafa1971	`!! Load Partition ID`
192	32	fafa1971	`rd %asr26, %l1`
193	35	fafa1971	`set 0x0300, %g1 !! aka "sethi %hi(0x1c00), %g1" "or %g1, 0x300, %g1"`
194	32	fafa1971	`and %l1, %g1, %l1`
195	73	fafa1971
196	35	fafa1971	`srlx %l1, 8, %l1 !! %l1 has thread ID`
197	32	fafa1971
198	73	fafa1971	`!!setx part_id_list, %g1, %g2`
199	35	fafa1971	`!! this instruction expands as`
200	73	fafa1971	`sethi %hi(0), %g1`
201			`sethi %hi(0x4c000), %g2 !! THIS INSTRUCTION CONTAINS THE ADDRESS IN MEMORY`
202			`mov %g1, %g1`
203			`mov %g2, %g2`
204			`sllx %g1, 0x20, %g1`
205			`or %g2, %g1, %g2`
206	32	fafa1971
207	35	fafa1971	`sllx %l1, 3, %l1 !! offset - partition list`
208			`ldx [%g2 + %l1], %g2 !! %g2 contains partition ID`
209	32	fafa1971	`mov 0x80, %g1`
210	73	fafa1971	`stxa %g2, [%g1] 0x58 !! BY FF - AFTER THIS INSTRUCTION WE GET TWO CONSECUTIVE ACCESSES`
211	32	fafa1971
212	35	fafa1971	`!! Set Hypervisor Trap Base Address`
213	73	fafa1971	`!!setx HV_TRAP_BASE_PA, %l0, %l7 !!sostituita con la sua espansione e costante=0x80000(!!sethi %hi(0x80000), %l7)`
214			`sethi %hh(0x80000),%g1`
215			`or %g1,%hm(0x80000),%g1`
216			`sllx %g1,32,%g1`
217			`sethi %hi(0x80000),%l1`
218			`or %l1,%g1,%l1`
219			`or %l1,%lo(0x80000),%l1`
220
221	32	fafa1971	`wrhpr %l7, %g0, %htba`
222
223	35	fafa1971	`!! Load TSB config/base from memory and write to corresponding ASI's`
224			`!! set tsb-reg (4 at present) for one partition`
225			`!! 2 i-config, 2-dconfig`
226	32	fafa1971
227	73	fafa1971	`!!setx tsb_config_base_list, %l0, %g1 !!sostituita con le successive istruzioni`
228	35	fafa1971	`!! this instructions expands as`
229	73	fafa1971	`sethi %hi(0), %l0`
230			`sethi %hi(0x4c000), %g1`
231			`mov %l0, %l0`
232			`or %g1, 0x140, %g1`
233			`sllx %l0, 0x20, %l0`
234			`or %g1, %l0, %g1`
235	32	fafa1971
236	35	fafa1971	`sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list`
237			`add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list`
238	32	fafa1971
239	35	fafa1971	`!! IMMU_CXT_Z_CONFIG (0x37, VA=0x00)`
240	32	fafa1971	`ldx [%g1], %l1`
241			`stxa %l1, [%g0] 0x37`
242
243	35	fafa1971	`!! IMMU_CXT_NZ_CONFIG (0x3f, VA=0x00)`
244	32	fafa1971	`ldx [%g1+8], %l1`
245			`stxa %l1, [%g0] 0x3f`
246
247	35	fafa1971	`!! IMMU_CXT_Z_PS0_TSB (0x35, VA=0x0)`
248			`!! IMMU_CXT_Z_PS1_TSB (0x36, VA=0x0)`
249	32	fafa1971	`ldx [%g1+16], %l1`
250			`stxa %l1, [%g0] 0x35`
251			`ldx [%g1+32], %l1`
252			`stxa %l1, [%g0] 0x36`
253
254	35	fafa1971	`!! IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)`
255			`!! IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)`
256	32	fafa1971	`ldx [%g1+24], %l1`
257			`stxa %l1, [%g0] 0x3d`
258			`ldx [%g1+40], %l1`
259			`stxa %l1, [%g0] 0x3e`
260
261	35	fafa1971	`!! DMMU_CXT_Z_CONFIG (0x33, VA=0x00)`
262	32	fafa1971	`ldx [%g1+64], %l1`
263			`stxa %l1, [%g0] 0x33`
264
265	35	fafa1971	`!! DMMU_CXT_NZ_CONFIG (0x3b, VA=0x00)`
266	32	fafa1971	`ldx [%g1+72], %l1`
267			`stxa %l1, [%g0] 0x3b`
268
269	35	fafa1971	`!! DMMU_CXT_Z_PS0_TSB (0x31, VA=0x00)`
270			`!! DMMU_CXT_Z_PS1_TSB (0x32, VA=0x00)`
271	32	fafa1971	`ldx [%g1+80], %l1`
272			`stxa %l1, [%g0] 0x31`
273			`ldx [%g1+96], %l1`
274			`stxa %l1, [%g0] 0x32`
275
276	35	fafa1971	`!! DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)`
277			`!! DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)`
278	32	fafa1971	`ldx [%g1+88], %l1`
279			`stxa %l1, [%g0] 0x39`
280			`ldx [%g1+104], %l1`
281			`stxa %l1, [%g0] 0x3a`
282
283	35	fafa1971	`!! Demap all itlb and dtlb`
284	32	fafa1971	`mov 0x80, %o2`
285			`stxa %g0, [%o2] 0x57`
286			`stxa %g0, [%o2] 0x5f`
287
288	73	fafa1971
289
290	35	fafa1971	`!! Initialize primary context register`
291	32	fafa1971	`mov 0x8, %l1`
292			`stxa %g0, [%l1] 0x21`
293
294	35	fafa1971	`!! Initialize secondary context register`
295	32	fafa1971	`mov 0x10, %l1`
296			`stxa %g0, [%l1] 0x21`
297
298	35	fafa1971	`!! Initialize dtsb entry for i context zero ps0, ps1`
299	36	fafa1971	`/*`
300	35	fafa1971	`!! Set LSU Control Register to enable icache, dcache, immu, dmmu`
301			`setx cregs_lsu_ctl_reg_r64, %g1, %l1 !! aka "mov 0xf, %l1"`
302	36	fafa1971	`*/`
303			`!! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache`
304			`mov 0xc, %l1`
305			`stxa %l1, [%g0] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"`
306	32	fafa1971
307	73	fafa1971	`!!setx HPriv_Reset_Handler, %g1, %g2`
308	35	fafa1971	`!! this instructions expands as`
309	73	fafa1971	`sethi %hi(0), %g1`
310			`sethi %hi(0x144000), %g2`
311			`mov %g1, %g1`
312			`mov %g2, %g2`
313			`sllx %g1, 0x20, %g1`
314			`or %g2, %g1, %g2`
315	32	fafa1971
316			`rdhpr %hpstate, %g3`
317			`wrpr 1, %tl`
318	73	fafa1971	`!!setx cregs_htstate_r64, %g1, %g4 !!sostituita con la successiva istruzione (!! aka "clr %g4")`
319			`sethi %hh(0x0),%g1`
320			`or %g1,%hm(0x0),%g1`
321			`sllx %g1,32,%g1`
322			`sethi %hi(0x0),%l1`
323			`or %l1,%g1,%l1`
324			`or %l1,%lo(0x0),%l1`
325
326	32	fafa1971	`wrhpr %g4, %g0, %htstate`
327			`wrpr 0, %tl`
328	35	fafa1971	`mov 0x0, %o0 !! aka "clr %o0", don't delete since used in customized IMMU miss trap`
329	32	fafa1971	`jmp %g2`
330			`wrhpr %g0, 0x800, %hpstate`
331			`nop`
332			`nop`
333
334

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