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32 |
fafa1971 |
/*
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* Simply RISC S1 Core - Boot code
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*
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* Cutdown version from the original OpenSPARC T1:
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*
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* $T1_ROOT/verif/diag/assembly/include/hred_reset_handler.s
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*
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* Main changes:
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36 |
fafa1971 |
* - L1 and L2 cache handling are not enabled;
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32 |
fafa1971 |
* - Interrupt Queues handling currently commented out since causes troubles in S1 Core.
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*
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* Sun Microsystems' copyright notices follow:
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*/
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/*
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* ========== Copyright Header Begin ==========================================
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*
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* OpenSPARC T1 Processor File: hred_reset_handler.s
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* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this work; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* ========== Copyright Header End ============================================
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*/
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35 |
fafa1971 |
!! Enable L2-ucache: Unused in S1 Core
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32 |
fafa1971 |
/*
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35 |
fafa1971 |
setx cregs_l2_ctl_reg_r64, %g1, %l1 !! aka "wr %g0, 5, %asr26" "clr %l1"
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32 |
fafa1971 |
mov 0xa9, %g1
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sllx %g1, 32, %g1
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stx %l1, [%g1 + 0x00]
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stx %l1, [%g1 + 0x40]
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stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0xc0]
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*/
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fafa1971 |
!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
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73 |
fafa1971 |
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77 |
fafa1971 |
!!setx cregs_lsu_diag_reg_r64, %g1, %l1 !!la variabile (cregs_lsu_diag_reg_r64) contiene il valore 0 (defines.h)
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!!ho sostituito questa istruzione con la sua espansione (!! aka "clr %l1")
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fafa1971 |
sethi %hh(0x0),%g1
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or %g1,%hm(0x0),%g1
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sllx %g1,32,%g1
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sethi %hi(0x0),%l1
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or %l1,%g1,%l1
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or %l1,%lo(0x0),%l1
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mov 0x10, %g1
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fafa1971 |
stxa %l1, [%g1] (66) !! pone a zero il registro ASI_LSU_DIAG_REG ottenendo
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!!l'abilitazione di tutte le vie della cache e l'utilizzo
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!!dell'algoritmo "random replacement" (aka "stxa %l1, [%g1] ASI_LSU_DIAG_REG")
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fafa1971 |
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fafa1971 |
!! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core
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/*
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fafa1971 |
setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"
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fafa1971 |
stxa %l1, [ %g0 ] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
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*/
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fafa1971 |
!! Set hpstate.red = 0 and hpstate.enb = 1
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fafa1971 |
rdhpr %hpstate, %l1
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fafa1971 |
and %l1,0x820,%l2
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xor %l2,0x800,%l2
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fafa1971 |
wrhpr %l1,%l2,%hpstate !!questo meccanismo "dovrebbe" assicurarmi red=0 enb=1 mantenendo inalterati gli altri bit del registro
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fafa1971 |
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fafa1971 |
!!wrhpr %l1, 0x820, %hpstate !! vecchia istruzione: otteniamo red=0 ed enb=1 solo se in precedenza avevamo red=1 ed enb=0
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fafa1971 |
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fafa1971 |
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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!!istruzione aggiunte dal file dal file hboot_tlb_init.s
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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fafa1971 |
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fafa1971 |
!! init all itlb entries
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mov 0x30, %g1
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mov %g0, %g2
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itlb_init_loop:
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!!pulisce data e tag entry del buffer per TLB
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stxa %g0, [ %g1 ] 0x50 !!IMMU TLB Tag Access register=0
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stxa %g0, [ %g2 ] 0x55 !!IMMU TLB Data Access register=0, g2 assume valori da 0 a 0x7f8
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fafa1971 |
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fafa1971 |
add %g2, 8, %g2 !!g2= somma 8 (byte) alla volta (64 bit)
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cmp %g2, 0x200 !!confronta con 512 (512*8=4096=0x1000), (ma al max VA=0x7F8 ?)
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fafa1971 |
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fafa1971 |
bne itlb_init_loop !!se g2!=da 0x200 ritorna all''inizio del loop
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nop
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fafa1971 |
! init all dtlb entries
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fafa1971 |
mov 0x30, %g1
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mov %g0, %g2
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dtlb_init_loop:
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stxa %g0, [ %g1 ] 0x58 !!DMMU TLB Tag Access register=0
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stxa %g0, [ %g2 ] 0x5d !!ASI_DTLB_DATA_ACCESS_REG(DMMU TLB Data Access)=0 g2 assume valori da 0 a 0x7f8
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fafa1971 |
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fafa1971 |
add %g2, 8, %g2 !!incrementa g2 di 64 bit alla voltra
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cmp %g2, 0x200 !!confronta g2 con 0x200
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bne dtlb_init_loop !!se sono diversi ricomincia il loop
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nop
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fafa1971 |
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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! Clear itlb/dtlb valid
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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fafa1971 |
stxa %g0, [%g0] 0x60 ! ASI_ITLB_INVALIDATE_ALL(IMMU TLB Invalidate register)=0
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mov 0x8, %g1
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stxa %g0, [%g0 + %g1] 0x60 ! ASI_DTLB_INVALIDATE_ALL(DMMU TLB Invalidate register)=0
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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!!da qui riprende il vecchio file boot.s
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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fafa1971 |
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fafa1971 |
!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
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fafa1971 |
/*
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wr %g0, 0x25, %asi
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stxa %g0, [0x3c0] %asi
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stxa %g0, [0x3c8] %asi
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stxa %g0, [0x3d0] %asi
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stxa %g0, [0x3d8] %asi
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stxa %g0, [0x3e0] %asi
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stxa %g0, [0x3e8] %asi
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stxa %g0, [0x3f0] %asi
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stxa %g0, [0x3f8] %asi
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wrpr 0, %tl
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wrpr 0, %g0, %gl
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wr %g0, cregs_fprs_imm, %fprs
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wr %g0, cregs_ccr_imm, %ccr
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wr %g0, cregs_asi_imm, %asi
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setx cregs_tick_r64, %g1, %g2
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fafa1971 |
!! FIXME set other ticks also
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fafa1971 |
wrpr %g2, %tick
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setx cregs_stick_r64, %g1, %g2
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wr %g2, %g0, %sys_tick
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mov 0x1, %g2
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sllx %g2, 63, %g2
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wr %g2, %g0, %tick_cmpr
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wr %g2, %g0, %sys_tick_cmpr
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wrhpr %g2, %g0, %hsys_tick_cmpr
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mov %g0, %y
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wrpr cregs_pil_imm, %pil
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wrpr cregs_cwp_imm, %cwp
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wrpr cregs_cansave_imm, %cansave
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wrpr cregs_canrestore_imm, %canrestore
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wrpr cregs_otherwin_imm, %otherwin
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wrpr cregs_cleanwin_imm, %cleanwin
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wrpr cregs_wstate_imm, %wstate
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*/
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fafa1971 |
!! Clear L1-icache and L1-dcache SFSR
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fafa1971 |
mov 0x18, %g1
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fafa1971 |
stxa %g0, [%g0 + %g1] 0x50 !IMMU Synchronous Fault Status register=0
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stxa %g0, [%g0 + %g1] 0x58 !DMMU Synchronous Fault Status register=0
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fafa1971 |
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fafa1971 |
!! Enable error trap
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fafa1971 |
!!setx cregs_sparc_error_en_reg_r64, %g1, %l1 !! aka "stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG"
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!!ho sostituito questa istruzione con la sua espansione
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!!ponendo la costante cregs_sparc_error_en_reg_r64=3 (dal file defines.h)
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!!l'effetto dovrebbe essere "trap on correctable error" e "trap on uncorrectable error"
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!!(!!aka "mov 3, %l1")
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!!inizio espansione
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fafa1971 |
sethi %hh(0x3),%g1
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or %g1,%hm(0x3),%g1
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sllx %g1,32,%g1
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sethi %hi(0x3),%l1
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or %l1,%g1,%l1
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or %l1,%lo(0x3),%l1
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fafa1971 |
stxa %l1, [%g0] (75) !!mette il contenuto di l1 nel registro "SPARC Error Enable reg"
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!!fine espansione
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32 |
fafa1971 |
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fafa1971 |
!! Enable L2-ucache error trap: Unused in S1 Core
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fafa1971 |
/*
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setx cregs_l2_error_en_reg_r64, %g1, %l1
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mov 0xaa, %g1
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sllx %g1, 32, %g1
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stx %l1, [%g1 + 0x00]
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stx %l1, [%g1 + 0x40]
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stx %l1, [%g1 + 0x80]
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stx %l1, [%g1 + 0xc0]
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*/
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77 |
fafa1971 |
!! Load Partition ID (permette a S.O. multipli di condividere lo stesso TLB)
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rd %asr26, %l1 !!%asr26 corrisponde allo Strand Status and Control register
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fafa1971 |
set 0x0300, %g1 !! aka "sethi %hi(0x1c00), %g1" "or %g1, 0x300, %g1"
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32 |
fafa1971 |
and %l1, %g1, %l1
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73 |
fafa1971 |
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fafa1971 |
srlx %l1, 8, %l1 !! %l1 has thread ID
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fafa1971 |
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77 |
fafa1971 |
!!setx part_id_list, %g1, %g2 (part_id_list viene definito nel file hboot.s)
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!! this instruction expands as (preso dal file ACCESS.TXT)
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!!inizio espansione
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73 |
fafa1971 |
sethi %hi(0), %g1
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77 |
fafa1971 |
sethi %hi(0x4c000), %g2
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73 |
fafa1971 |
mov %g1, %g1
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mov %g2, %g2
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sllx %g1, 0x20, %g1
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or %g2, %g1, %g2
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77 |
fafa1971 |
!!fine espansione
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32 |
fafa1971 |
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35 |
fafa1971 |
sllx %l1, 3, %l1 !! offset - partition list
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ldx [%g2 + %l1], %g2 !! %g2 contains partition ID
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| 219 |
32 |
fafa1971 |
mov 0x80, %g1
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77 |
fafa1971 |
stxa %g2, [%g1] 0x58 !!I/DMMU Partition ID=g2
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32 |
fafa1971 |
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35 |
fafa1971 |
!! Set Hypervisor Trap Base Address
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| 223 |
77 |
fafa1971 |
!!setx HV_TRAP_BASE_PA, %l0, %l7 !!sostituita con la sua espansione e HV_TRAP_BASE_PA=0x80000(!!sethi %hi(0x80000), %l7)
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!!inizio espansione
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73 |
fafa1971 |
sethi %hh(0x80000),%g1
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or %g1,%hm(0x80000),%g1
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| 227 |
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sllx %g1,32,%g1
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| 228 |
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sethi %hi(0x80000),%l1
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| 229 |
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or %l1,%g1,%l1
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or %l1,%lo(0x80000),%l1
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| 231 |
77 |
fafa1971 |
!!fine espansione
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| 232 |
73 |
fafa1971 |
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77 |
fafa1971 |
wrhpr %l7, %g0, %htba !!i bit da 63-14 servono a selezionare il trap vector per un trap servito in Hyperprivileged mode
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| 234 |
32 |
fafa1971 |
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| 235 |
35 |
fafa1971 |
!! Load TSB config/base from memory and write to corresponding ASI's
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| 236 |
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!! set tsb-reg (4 at present) for one partition
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| 237 |
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!! 2 i-config, 2-dconfig
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| 238 |
32 |
fafa1971 |
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| 239 |
77 |
fafa1971 |
!!setx tsb_config_base_list, %l0, %g1
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| 240 |
35 |
fafa1971 |
!! this instructions expands as
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| 241 |
73 |
fafa1971 |
sethi %hi(0), %l0
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| 242 |
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sethi %hi(0x4c000), %g1
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| 243 |
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mov %l0, %l0
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| 244 |
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or %g1, 0x140, %g1
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| 245 |
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sllx %l0, 0x20, %l0
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| 246 |
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or %g1, %l0, %g1
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| 247 |
77 |
fafa1971 |
!!fine espansione
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| 248 |
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| 249 |
35 |
fafa1971 |
sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list
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| 250 |
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add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list
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| 251 |
32 |
fafa1971 |
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| 252 |
35 |
fafa1971 |
!! IMMU_CXT_Z_CONFIG (0x37, VA=0x00)
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| 253 |
32 |
fafa1971 |
ldx [%g1], %l1
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| 254 |
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stxa %l1, [%g0] 0x37
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| 255 |
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| 256 |
35 |
fafa1971 |
!! IMMU_CXT_NZ_CONFIG (0x3f, VA=0x00)
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| 257 |
32 |
fafa1971 |
ldx [%g1+8], %l1
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| 258 |
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stxa %l1, [%g0] 0x3f
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| 259 |
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| 260 |
35 |
fafa1971 |
!! IMMU_CXT_Z_PS0_TSB (0x35, VA=0x0)
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| 261 |
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!! IMMU_CXT_Z_PS1_TSB (0x36, VA=0x0)
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| 262 |
32 |
fafa1971 |
ldx [%g1+16], %l1
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| 263 |
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stxa %l1, [%g0] 0x35
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| 264 |
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ldx [%g1+32], %l1
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| 265 |
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stxa %l1, [%g0] 0x36
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| 266 |
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| 267 |
35 |
fafa1971 |
!! IMMU_CXT_NZ_PS0_TSB (0x3d, VA=0x00)
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| 268 |
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!! IMMU_CXT_NZ_PS1_TSB (0x3e, VA=0x00)
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| 269 |
32 |
fafa1971 |
ldx [%g1+24], %l1
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| 270 |
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stxa %l1, [%g0] 0x3d
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| 271 |
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ldx [%g1+40], %l1
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| 272 |
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stxa %l1, [%g0] 0x3e
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| 273 |
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| 274 |
35 |
fafa1971 |
!! DMMU_CXT_Z_CONFIG (0x33, VA=0x00)
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| 275 |
32 |
fafa1971 |
ldx [%g1+64], %l1
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| 276 |
|
|
stxa %l1, [%g0] 0x33
|
| 277 |
|
|
|
| 278 |
35 |
fafa1971 |
!! DMMU_CXT_NZ_CONFIG (0x3b, VA=0x00)
|
| 279 |
32 |
fafa1971 |
ldx [%g1+72], %l1
|
| 280 |
|
|
stxa %l1, [%g0] 0x3b
|
| 281 |
|
|
|
| 282 |
35 |
fafa1971 |
!! DMMU_CXT_Z_PS0_TSB (0x31, VA=0x00)
|
| 283 |
|
|
!! DMMU_CXT_Z_PS1_TSB (0x32, VA=0x00)
|
| 284 |
32 |
fafa1971 |
ldx [%g1+80], %l1
|
| 285 |
|
|
stxa %l1, [%g0] 0x31
|
| 286 |
|
|
ldx [%g1+96], %l1
|
| 287 |
|
|
stxa %l1, [%g0] 0x32
|
| 288 |
|
|
|
| 289 |
35 |
fafa1971 |
!! DMMU_CXT_NZ_PS0_TSB (0x39, VA=0x00)
|
| 290 |
|
|
!! DMMU_CXT_NZ_PS0_TSB (0x3a, VA=0x00)
|
| 291 |
32 |
fafa1971 |
ldx [%g1+88], %l1
|
| 292 |
|
|
stxa %l1, [%g0] 0x39
|
| 293 |
|
|
ldx [%g1+104], %l1
|
| 294 |
|
|
stxa %l1, [%g0] 0x3a
|
| 295 |
|
|
|
| 296 |
35 |
fafa1971 |
!! Demap all itlb and dtlb
|
| 297 |
32 |
fafa1971 |
mov 0x80, %o2
|
| 298 |
77 |
fafa1971 |
stxa %g0, [%o2] 0x57 !!registro ASI_IMMU_DEMAP=0 (IMMU TLB demap)
|
| 299 |
|
|
stxa %g0, [%o2] 0x5f !!registro ASI_DMMU_DEMAP=0 (DMMU TLB demap)
|
| 300 |
32 |
fafa1971 |
|
| 301 |
73 |
fafa1971 |
|
| 302 |
|
|
|
| 303 |
35 |
fafa1971 |
!! Initialize primary context register
|
| 304 |
32 |
fafa1971 |
mov 0x8, %l1
|
| 305 |
|
|
stxa %g0, [%l1] 0x21
|
| 306 |
|
|
|
| 307 |
35 |
fafa1971 |
!! Initialize secondary context register
|
| 308 |
32 |
fafa1971 |
mov 0x10, %l1
|
| 309 |
|
|
stxa %g0, [%l1] 0x21
|
| 310 |
|
|
|
| 311 |
35 |
fafa1971 |
!! Initialize dtsb entry for i context zero ps0, ps1
|
| 312 |
36 |
fafa1971 |
/*
|
| 313 |
35 |
fafa1971 |
!! Set LSU Control Register to enable icache, dcache, immu, dmmu
|
| 314 |
|
|
setx cregs_lsu_ctl_reg_r64, %g1, %l1 !! aka "mov 0xf, %l1"
|
| 315 |
36 |
fafa1971 |
*/
|
| 316 |
|
|
!! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache
|
| 317 |
|
|
mov 0xc, %l1
|
| 318 |
77 |
fafa1971 |
stxa %l1, [%g0] (69) !!Load/Store Unit Control Register=1100 (aka "stxa %l1, [%g0] ASI_LSU_CTL_REG")
|
| 319 |
|
|
!!l''effetto dovrebbe essere:
|
| 320 |
|
|
!! .dm=1 (DMMU ENABLE)
|
| 321 |
|
|
!! .Im=1 (IMMU ENABLE)
|
| 322 |
|
|
!! .dc=0 (dcache not enabled)
|
| 323 |
|
|
|| .ic=0 (icache not enabled)
|
| 324 |
73 |
fafa1971 |
!!setx HPriv_Reset_Handler, %g1, %g2
|
| 325 |
35 |
fafa1971 |
!! this instructions expands as
|
| 326 |
73 |
fafa1971 |
sethi %hi(0), %g1
|
| 327 |
|
|
sethi %hi(0x144000), %g2
|
| 328 |
|
|
mov %g1, %g1
|
| 329 |
|
|
mov %g2, %g2
|
| 330 |
|
|
sllx %g1, 0x20, %g1
|
| 331 |
|
|
or %g2, %g1, %g2
|
| 332 |
77 |
fafa1971 |
!! fine espansione
|
| 333 |
32 |
fafa1971 |
|
| 334 |
|
|
rdhpr %hpstate, %g3
|
| 335 |
77 |
fafa1971 |
wrpr 1, %tl !!livello trap corrente=1
|
| 336 |
|
|
|
| 337 |
|
|
!!setx cregs_htstate_r64, %g1, %g4
|
| 338 |
|
|
!! this instructions expands as !!sostituita con la successive istruzioni (da manuale) (!! aka "clr %g4")
|
| 339 |
|
|
!! inizio espansione
|
| 340 |
73 |
fafa1971 |
sethi %hh(0x0),%g1
|
| 341 |
|
|
or %g1,%hm(0x0),%g1
|
| 342 |
|
|
sllx %g1,32,%g1
|
| 343 |
|
|
sethi %hi(0x0),%l1
|
| 344 |
|
|
or %l1,%g1,%l1
|
| 345 |
|
|
or %l1,%lo(0x0),%l1
|
| 346 |
77 |
fafa1971 |
!!fine espansione
|
| 347 |
73 |
fafa1971 |
|
| 348 |
77 |
fafa1971 |
wrhpr %g4, %g0, %htstate !! dovrebbe resettare il registro HTSTATE che mantiene lo stato hyperpriviliged dopo un trap
|
| 349 |
|
|
wrpr 0, %tl !! trap level corrente=0 (No Trap)
|
| 350 |
35 |
fafa1971 |
mov 0x0, %o0 !! aka "clr %o0", don't delete since used in customized IMMU miss trap
|
| 351 |
32 |
fafa1971 |
jmp %g2
|
| 352 |
77 |
fafa1971 |
wrhpr %g0, 0x800, %hpstate !!assicura il bit 11 del registro HPSTATE al valore 1 (per evitare comportamenti non previsti)
|
| 353 |
32 |
fafa1971 |
nop
|
| 354 |
|
|
nop
|
| 355 |
|
|
|
| 356 |
|
|
|
