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[/] [s1_core/] [trunk/] [tools/] [src/] [build_dc.cmd] - Blame information for rev 66

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/* If you modify this file remember to run update_filelist so that filelist.dc gets updated!!! */
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elaborate s1_top
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link
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uniquify
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/* check_design */
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create_clock -period 2.0 -name sys_clock_i find(port, "sys_clock_i")
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set_input_delay  -max -clock sys_clock_i 1 all_inputs () find (port, "sys_clock_i")
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set_output_delay 1 -max -clock sys_clock_i all_outputs()
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compile -map_effort high
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write -output s1_top.db  -format ddc  -hierarchy
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write -output s1_top.v  -format verilog  -hierarchy
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report_area > report_area.txt
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report_timing > report_timing.txt
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report_constraint -all_violators > report_constraint.txt
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quit
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