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[/] [s1_core/] [trunk/] [tools/] [src/] [build_dc.cmd] - Blame information for rev 73

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1 73 fafa1971
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
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# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!
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elaborate s1_top
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link
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uniquify
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check_design
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# Constraints
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create_clock -name "sys_clock_i" -period 2.0 -waveform {0 1.0} [get_ports "sys_clock_i"]
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set_dont_touch_network [get_clocks "sys_clock_i"]
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set_input_delay 1.25 -max -rise -clock "sys_clock_i" [get_ports "sys_reset_i"]
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set_input_delay 1.25 -max -fall -clock "sys_clock_i" [get_ports "sys_reset_i"]
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set_output_delay 1.25 -clock sys_clock_i -max -rise [all_outputs]
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set_output_delay 1.25 -clock sys_clock_i -max -fall [all_outputs]
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set_wire_load_mode "enclosed"
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# Compile
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compile
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# Export
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write -format db -hierarchy -output "s1_top.db"
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write -format verilog -hierarchy -output "s1_top.v"
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# Report
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report_area > report_area.txt
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report_timing > report_timing.txt
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report_constraint -all_violators > report_constraint.txt
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quit
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