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dgisselq |
///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: spiflashsim.cpp
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//
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// Project: Wishbone Controlled Quad SPI Flash Controller
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//
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// Purpose: This library simulates the operation of a Quad-SPI commanded
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// flash, such as the S25FL032P used on the Basys-3 development
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// board by Digilent. As such, it is defined by 32 Mbits of
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// memory (4 Mbyte).
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//
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// This simulator is useful for testing in a Verilator/C++
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// environment, where this simulator can be used in place of
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// the actual hardware.
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//
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// Creator: Dan Gisselquist
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include <stdlib.h>
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dgisselq |
#include "regdefs.h"
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dgisselq |
#include "qspiflashsim.h"
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dgisselq |
#define MEMBYTES (FLASHWORDS<<2)
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2 |
dgisselq |
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static const unsigned DEVID = 0x0115,
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DEVESD = 0x014,
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MICROSECONDS = 100,
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MILLISECONDS = MICROSECONDS * 1000,
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SECONDS = MILLISECONDS * 1000,
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tW = 50 * MICROSECONDS, // write config cycle time
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tBE = 32 * SECONDS,
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tDP = 10 * SECONDS,
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tRES = 30 * SECONDS,
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// Shall we artificially speed up this process?
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tPP = 12 * MICROSECONDS,
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tSE = 15 * MILLISECONDS;
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// or keep it at the original speed
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// tPP = 1200 * MICROSECONDS,
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// tSE = 1500 * MILLISECONDS;
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QSPIFLASHSIM::QSPIFLASHSIM(void) {
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m_mem = new char[MEMBYTES];
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m_pmem = new char[256];
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m_state = QSPIF_IDLE;
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m_last_sck = 1;
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m_write_count = 0;
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m_ireg = m_oreg = 0;
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m_sreg = 0x01c;
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m_creg = 0x001; // Iinitial creg on delivery
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m_quad_mode = false;
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m_mode_byte = 0;
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memset(m_mem, 0x0ff, MEMBYTES);
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}
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void QSPIFLASHSIM::load(const unsigned addr, const char *fname) {
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FILE *fp;
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size_t len;
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if (addr >= MEMBYTES)
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return;
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len = MEMBYTES-addr*4;
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if (NULL != (fp = fopen(fname, "r"))) {
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int nr = 0;
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nr = fread(&m_mem[addr], sizeof(char), len, fp);
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fclose(fp);
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if (nr == 0) {
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fprintf(stderr, "SPI-FLASH: Could not read %s\n", fname);
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perror("O/S Err:");
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}
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} else {
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fprintf(stderr, "SPI-FLASH: Could not open %s\n", fname);
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perror("O/S Err:");
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}
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}
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dgisselq |
void QSPIFLASHSIM::write(const unsigned addr, const unsigned len, const uint32_t *buf) {
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char *ptr;
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dgisselq |
if ((addr+len < SPIFLASH)||(addr >= SPIFLASH+MEMBYTES/4))
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return;
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dgisselq |
printf("FLASH: Copying into memory at S6Add4 %08x, my addr %08x, %d values\n",
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addr, (addr-SPIFLASH)<<2, len<<2);
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ptr = &m_mem[(addr-SPIFLASH)<<2];
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memcpy(ptr, buf, len<<2);
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printf("%02x %02x %02x %02x\n", ptr[0]&0x0ff, ptr[1]&0x0ff, ptr[2]&0x0ff, ptr[3]&0x0ff);
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}
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dgisselq |
#define QOREG(A) m_oreg = ((m_oreg & (~0x0ff))|(A&0x0ff))
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int QSPIFLASHSIM::operator()(const int csn, const int sck, const int dat) {
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// Keep track of a timer to determine when page program and erase
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// cycles complete.
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if (m_write_count > 0) {
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if (0 == (--m_write_count)) {// When done with erase/page pgm,
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m_sreg &= 0x0fc; // Clear the write in progress bit
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if (m_debug) printf("Write complete, clearing WIP (inside SIM)\n");
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}
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}
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if (csn) {
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m_last_sck = 1;
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m_ireg = 0; m_oreg = 0;
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m_count= 0;
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if ((QSPIF_PP == m_state)||(QSPIF_QPP == m_state)) {
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// Start a page program
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if (m_debug) printf("QSPI: Page Program write cycle begins\n");
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if (m_debug) printf("CK = %d & 7 = %d\n", m_count, m_count & 0x07);
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if (m_debug) printf("QSPI: pmem = %08lx\n", (unsigned long)m_pmem);
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m_write_count = tPP;
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m_state = QSPIF_IDLE;
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m_sreg &= (~QSPIF_WEL_FLAG);
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m_sreg |= (QSPIF_WIP_FLAG);
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for(int i=0; i<256; i++) {
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/*
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if (m_debug) printf("%02x: m_mem[%02x] = %02x &= %02x = %02x\n",
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i, (m_addr&(~0x0ff))+i,
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m_mem[(m_addr&(~0x0ff))+i]&0x0ff, m_pmem[i]&0x0ff,
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m_mem[(m_addr&(~0x0ff))+i]& m_pmem[i]&0x0ff);
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*/
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m_mem[(m_addr&(~0x0ff))+i] &= m_pmem[i];
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}
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m_quad_mode = false;
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} else if (m_state == QSPIF_SECTOR_ERASE) {
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if (m_debug) printf("Actually Erasing sector, from %08x\n", m_addr);
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m_write_count = tSE;
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m_state = QSPIF_IDLE;
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m_sreg &= (~QSPIF_WEL_FLAG);
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m_sreg |= (QSPIF_WIP_FLAG);
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m_addr &= (-1<<16);
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for(int i=0; i<(1<<16); i++)
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m_mem[m_addr + i] = 0x0ff;
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if (m_debug) printf("Now waiting %d ticks delay\n", m_write_count);
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} else if (QSPIF_WRSR == m_state) {
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if (m_debug) printf("Actually writing status register\n");
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m_write_count = tW;
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m_state = QSPIF_IDLE;
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m_sreg &= (~QSPIF_WEL_FLAG);
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m_sreg |= (QSPIF_WIP_FLAG);
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} else if (QSPIF_CLSR == m_state) {
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if (m_debug) printf("Actually clearing the status register bits\n");
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m_state = QSPIF_IDLE;
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m_sreg &= 0x09f;
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} else if (m_state == QSPIF_BULK_ERASE) {
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m_write_count = tBE;
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m_state = QSPIF_IDLE;
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m_sreg &= (~QSPIF_WEL_FLAG);
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m_sreg |= (QSPIF_WIP_FLAG);
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for(int i=0; i<MEMBYTES; i++)
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m_mem[i] = 0x0ff;
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} else if (m_state == QSPIF_DEEP_POWER_DOWN) {
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m_write_count = tDP;
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m_state = QSPIF_IDLE;
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} else if (m_state == QSPIF_RELEASE) {
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m_write_count = tRES;
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m_state = QSPIF_IDLE;
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} else if (m_state == QSPIF_QUAD_READ_CMD) {
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if ((m_mode_byte & 0x0f0)!=0x0a0)
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m_quad_mode = false;
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else
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m_state = QSPIF_QUAD_READ_IDLE;
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} else if (m_state == QSPIF_QUAD_READ) {
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if ((m_mode_byte & 0x0f0)!=0x0a0)
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m_quad_mode = false;
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else
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m_state = QSPIF_QUAD_READ_IDLE;
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} else if (m_state == QSPIF_QUAD_READ_IDLE) {
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}
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m_oreg = 0x0fe;
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return dat;
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} else if ((!m_last_sck)||(sck == m_last_sck)) {
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// Only change on the falling clock edge
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// printf("SFLASH-SKIP, CLK=%d -> %d\n", m_last_sck, sck);
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m_last_sck = sck;
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if (m_quad_mode)
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return (m_oreg>>8)&0x0f;
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else
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// return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
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return (m_oreg & 0x0100)?2:0;
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}
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// We'll only get here if ...
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// last_sck = 1, and sck = 0, thus transitioning on the
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// negative edge as with everything else in this interface
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if (m_quad_mode) {
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m_ireg = (m_ireg << 4) | (dat & 0x0f);
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m_count+=4;
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m_oreg <<= 4;
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} else {
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m_ireg = (m_ireg << 1) | (dat & 1);
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m_count++;
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m_oreg <<= 1;
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}
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// printf("PROCESS, COUNT = %d, IREG = %02x\n", m_count, m_ireg);
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if (m_state == QSPIF_QUAD_READ_IDLE) {
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assert(m_quad_mode);
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if (m_count == 24) {
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if (m_debug) printf("QSPI: Entering from Quad-Read Idle to Quad-Read\n");
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if (m_debug) printf("QSPI: QI/O Idle Addr = %02x\n", m_ireg&0x0ffffff);
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m_addr = (m_ireg) & 0x0ffffff;
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assert((m_addr & 0xfc00000)==0);
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m_state = QSPIF_QUAD_READ;
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} m_oreg = 0;
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} else if (m_count == 8) {
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QOREG(0x0a5);
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// printf("SFLASH-CMD = %02x\n", m_ireg & 0x0ff);
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// Figure out what command we've been given
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if (m_debug) printf("SPI FLASH CMD %02x\n", m_ireg&0x0ff);
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| 243 |
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switch(m_ireg & 0x0ff) {
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case 0x01: // Write status register
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if (2 !=(m_sreg & 0x203)) {
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if (m_debug) printf("QSPI: WEL not set, cannot write status reg\n");
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m_state = QSPIF_INVALID;
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} else
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| 249 |
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m_state = QSPIF_WRSR;
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break;
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| 251 |
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case 0x02: // Page program
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| 252 |
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if (2 != (m_sreg & 0x203)) {
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| 253 |
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if (m_debug) printf("QSPI: Cannot program at this time, SREG = %x\n", m_sreg);
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| 254 |
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m_state = QSPIF_INVALID;
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} else {
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| 256 |
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m_state = QSPIF_PP;
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| 257 |
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if (m_debug) printf("PAGE-PROGRAM COMMAND ACCEPTED\n");
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| 258 |
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}
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| 259 |
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break;
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| 260 |
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case 0x03: // Read data bytes
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| 261 |
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// Our clock won't support this command, so go
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| 262 |
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// to an invalid state
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| 263 |
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if (m_debug) printf("QSPI INVALID: This sim does not support slow reading\n");
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| 264 |
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m_state = QSPIF_INVALID;
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| 265 |
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break;
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| 266 |
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case 0x04: // Write disable
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| 267 |
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m_state = QSPIF_IDLE;
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| 268 |
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m_sreg &= (~QSPIF_WEL_FLAG);
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| 269 |
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break;
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| 270 |
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case 0x05: // Read status register
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| 271 |
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m_state = QSPIF_RDSR;
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| 272 |
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if (m_debug) printf("QSPI: READING STATUS REGISTER: %02x\n", m_sreg);
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| 273 |
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QOREG(m_sreg);
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| 274 |
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break;
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| 275 |
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case 0x06: // Write enable
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| 276 |
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m_state = QSPIF_IDLE;
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| 277 |
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m_sreg |= QSPIF_WEL_FLAG;
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| 278 |
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if (m_debug) printf("QSPI: WRITE-ENABLE COMMAND ACCEPTED\n");
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| 279 |
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break;
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| 280 |
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case 0x0b: // Here's the read that we support
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| 281 |
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if (m_debug) printf("QSPI: FAST-READ (single-bit)\n");
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| 282 |
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m_state = QSPIF_FAST_READ;
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| 283 |
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break;
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| 284 |
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case 0x30:
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| 285 |
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if (m_debug) printf("QSPI: CLEAR STATUS REGISTER COMMAND\n");
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| 286 |
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m_state = QSPIF_CLSR;
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| 287 |
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break;
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| 288 |
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case 0x32: // QUAD Page program, 4 bits at a time
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| 289 |
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if (2 != (m_sreg & 0x203)) {
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| 290 |
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if (m_debug) printf("QSPI: Cannot program at this time, SREG = %x\n", m_sreg);
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| 291 |
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m_state = QSPIF_INVALID;
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| 292 |
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} else {
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| 293 |
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m_state = QSPIF_QPP;
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| 294 |
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if (m_debug) printf("QSPI: QUAD-PAGE-PROGRAM COMMAND ACCEPTED\n");
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| 295 |
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if (m_debug) printf("QSPI: pmem = %08lx\n", (unsigned long)m_pmem);
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| 296 |
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}
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| 297 |
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break;
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| 298 |
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case 0x35: // Read configuration register
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| 299 |
|
|
m_state = QSPIF_RDCR;
|
| 300 |
|
|
if (m_debug) printf("QSPI: READING CONFIGURATION REGISTER: %02x\n", m_creg);
|
| 301 |
|
|
QOREG(m_creg);
|
| 302 |
|
|
break;
|
| 303 |
|
|
case 0x9f: // Read ID
|
| 304 |
|
|
m_state = QSPIF_RDID;
|
| 305 |
|
|
if (m_debug) printf("QSPI: READING ID, %02x\n", (DEVID>>24)&0x0ff);
|
| 306 |
|
|
QOREG(0xfe);
|
| 307 |
|
|
break;
|
| 308 |
|
|
case 0xab: // Release from DEEP POWER DOWN
|
| 309 |
|
|
if (m_sreg & QSPIF_DEEP_POWER_DOWN_FLAG) {
|
| 310 |
|
|
if (m_debug) printf("QSPI: Release from deep power down\n");
|
| 311 |
|
|
m_sreg &= (~QSPIF_DEEP_POWER_DOWN_FLAG);
|
| 312 |
|
|
m_write_count = tRES;
|
| 313 |
|
|
} m_state = QSPIF_RELEASE;
|
| 314 |
|
|
break;
|
| 315 |
|
|
case 0xb9: // DEEP POWER DOWN
|
| 316 |
|
|
if (0 != (m_sreg & 0x01)) {
|
| 317 |
|
|
if (m_debug) printf("QSPI: Cannot enter DEEP POWER DOWN, in middle of write/erase\n");
|
| 318 |
|
|
m_state = QSPIF_INVALID;
|
| 319 |
|
|
} else {
|
| 320 |
|
|
m_sreg |= QSPIF_DEEP_POWER_DOWN_FLAG;
|
| 321 |
|
|
m_state = QSPIF_IDLE;
|
| 322 |
|
|
}
|
| 323 |
|
|
break;
|
| 324 |
|
|
case 0xc7: // Bulk Erase
|
| 325 |
|
|
if (2 != (m_sreg & 0x203)) {
|
| 326 |
|
|
if (m_debug) printf("QSPI: WEL not set, cannot erase device\n");
|
| 327 |
|
|
m_state = QSPIF_INVALID;
|
| 328 |
|
|
} else
|
| 329 |
|
|
m_state = QSPIF_BULK_ERASE;
|
| 330 |
|
|
break;
|
| 331 |
|
|
case 0xd8: // Sector Erase
|
| 332 |
|
|
if (2 != (m_sreg & 0x203)) {
|
| 333 |
|
|
if (m_debug) printf("QSPI: WEL not set, cannot erase sector\n");
|
| 334 |
|
|
m_state = QSPIF_INVALID;
|
| 335 |
|
|
} else {
|
| 336 |
|
|
m_state = QSPIF_SECTOR_ERASE;
|
| 337 |
|
|
if (m_debug) printf("QSPI: SECTOR_ERASE COMMAND\n");
|
| 338 |
|
|
}
|
| 339 |
|
|
break;
|
| 340 |
|
|
case 0x0eb: // Here's the (other) read that we support
|
| 341 |
|
|
// printf("QSPI: QUAD-I/O-READ\n");
|
| 342 |
|
|
m_state = QSPIF_QUAD_READ_CMD;
|
| 343 |
|
|
m_quad_mode = true;
|
| 344 |
|
|
break;
|
| 345 |
|
|
default:
|
| 346 |
|
|
printf("QSPI: UNRECOGNIZED SPI FLASH CMD: %02x\n", m_ireg&0x0ff);
|
| 347 |
|
|
m_state = QSPIF_INVALID;
|
| 348 |
|
|
assert(0 && "Unrecognized command\n");
|
| 349 |
|
|
break;
|
| 350 |
|
|
}
|
| 351 |
|
|
} else if ((0 == (m_count&0x07))&&(m_count != 0)) {
|
| 352 |
|
|
QOREG(0);
|
| 353 |
|
|
switch(m_state) {
|
| 354 |
|
|
case QSPIF_IDLE:
|
| 355 |
|
|
printf("TOO MANY CLOCKS, SPIF in IDLE\n");
|
| 356 |
|
|
break;
|
| 357 |
|
|
case QSPIF_WRSR:
|
| 358 |
|
|
if (m_count == 16) {
|
| 359 |
|
|
m_sreg = (m_sreg & 0x061) | (m_ireg & 0x09c);
|
| 360 |
|
|
if (m_debug) printf("Request to set sreg to 0x%02x\n",
|
| 361 |
|
|
m_ireg&0x0ff);
|
| 362 |
|
|
} else if (m_count == 24) {
|
| 363 |
|
|
m_creg = (m_creg & 0x0fd) | (m_ireg & 0x02);
|
| 364 |
|
|
if (m_debug) printf("Request to set creg to 0x%02x\n",
|
| 365 |
|
|
m_ireg&0x0ff);
|
| 366 |
|
|
} else {
|
| 367 |
|
|
printf("TOO MANY CLOCKS FOR WRR!!!\n");
|
| 368 |
|
|
exit(-2);
|
| 369 |
|
|
m_state = QSPIF_IDLE;
|
| 370 |
|
|
}
|
| 371 |
|
|
break;
|
| 372 |
|
|
case QSPIF_CLSR:
|
| 373 |
|
|
assert(0 && "Too many clocks for CLSR command!!\n");
|
| 374 |
|
|
break;
|
| 375 |
|
|
case QSPIF_RDID:
|
| 376 |
|
|
if (m_count == 32) {
|
| 377 |
|
|
m_addr = m_ireg & 0x0ffffff;
|
| 378 |
|
|
if (m_debug) printf("READID, ADDR = %08x\n", m_addr);
|
| 379 |
|
|
QOREG((DEVID>>8));
|
| 380 |
|
|
if (m_debug) printf("QSPI: READING ID, %02x\n", (DEVID>>8)&0x0ff);
|
| 381 |
|
|
} else if (m_count > 32) {
|
| 382 |
|
|
if (((m_count-32)>>3)&1)
|
| 383 |
|
|
QOREG((DEVID));
|
| 384 |
|
|
else
|
| 385 |
|
|
QOREG((DEVID>>8));
|
| 386 |
|
|
if (m_debug) printf("QSPI: READING ID, %02x -- DONE\n", 0x00);
|
| 387 |
|
|
}
|
| 388 |
|
|
// m_oreg = (DEVID >> (2-(m_count>>3)-1)) & 0x0ff;
|
| 389 |
|
|
break;
|
| 390 |
|
|
case QSPIF_RDSR:
|
| 391 |
|
|
// printf("Read SREG = %02x, wait = %08x\n", m_sreg,
|
| 392 |
|
|
// m_write_count);
|
| 393 |
|
|
QOREG(m_sreg);
|
| 394 |
|
|
break;
|
| 395 |
|
|
case QSPIF_RDCR:
|
| 396 |
|
|
if (m_debug) printf("Read CREG = %02x\n", m_creg);
|
| 397 |
|
|
QOREG(m_creg);
|
| 398 |
|
|
break;
|
| 399 |
|
|
case QSPIF_FAST_READ:
|
| 400 |
|
|
if (m_count == 32) {
|
| 401 |
|
|
m_addr = m_ireg & 0x0ffffff;
|
| 402 |
|
|
if (m_debug) printf("FAST READ, ADDR = %08x\n", m_addr);
|
| 403 |
|
|
QOREG(0x0c3);
|
| 404 |
|
|
assert((m_addr & 0xfc00000)==0);
|
| 405 |
|
|
} else if ((m_count >= 40)&&(0 == (m_sreg&0x01))) {
|
| 406 |
|
|
//if (m_count == 40)
|
| 407 |
|
|
//printf("DUMMY BYTE COMPLETE ...\n");
|
| 408 |
|
|
QOREG(m_mem[m_addr++]);
|
| 409 |
|
|
// if (m_debug) printf("SPIF[%08x] = %02x\n", m_addr-1, m_oreg);
|
| 410 |
|
|
} else m_oreg = 0;
|
| 411 |
|
|
break;
|
| 412 |
|
|
case QSPIF_QUAD_READ_CMD:
|
| 413 |
|
|
// The command to go into quad read mode took 8 bits
|
| 414 |
|
|
// that changes the timings, else we'd use quad_Read
|
| 415 |
|
|
// below
|
| 416 |
|
|
if (m_count == 32) {
|
| 417 |
|
|
m_addr = m_ireg & 0x0ffffff;
|
| 418 |
|
|
// printf("FAST READ, ADDR = %08x\n", m_addr);
|
| 419 |
|
|
// printf("QSPI: QUAD READ, ADDR = %06x\n", m_addr);
|
| 420 |
|
|
assert((m_addr & 0xfc00000)==0);
|
| 421 |
|
|
} else if (m_count == 32+24) {
|
| 422 |
|
|
m_mode_byte = (m_ireg>>16) & 0x0ff;
|
| 423 |
|
|
// printf("QSPI: MODE BYTE = %02x\n", m_mode_byte);
|
| 424 |
|
|
} else if ((m_count > 32+24)&&(0 == (m_sreg&0x01))) {
|
| 425 |
|
|
QOREG(m_mem[m_addr++]);
|
| 426 |
|
|
// printf("QSPIF[%08x]/QR = %02x\n",
|
| 427 |
|
|
// m_addr-1, m_oreg);
|
| 428 |
|
|
} else m_oreg = 0;
|
| 429 |
|
|
break;
|
| 430 |
|
|
case QSPIF_QUAD_READ:
|
| 431 |
|
|
if (m_count == 32) {
|
| 432 |
|
|
m_mode_byte = (m_ireg & 0x0ff);
|
| 433 |
|
|
// printf("QSPI/QR: MODE BYTE = %02x\n", m_mode_byte);
|
| 434 |
|
|
} else if ((m_count >= 32+16)&&(0 == (m_sreg&0x01))) {
|
| 435 |
|
|
QOREG(m_mem[m_addr++]);
|
| 436 |
|
|
// printf("QSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
|
| 437 |
|
|
} else m_oreg = 0;
|
| 438 |
|
|
break;
|
| 439 |
|
|
case QSPIF_PP:
|
| 440 |
|
|
if (m_count == 32) {
|
| 441 |
|
|
m_addr = m_ireg & 0x0ffffff;
|
| 442 |
|
|
if (m_debug) printf("QSPI: PAGE-PROGRAM ADDR = %06x\n", m_addr);
|
| 443 |
|
|
assert((m_addr & 0xfc00000)==0);
|
| 444 |
|
|
// m_page = m_addr >> 8;
|
| 445 |
|
|
for(int i=0; i<256; i++)
|
| 446 |
|
|
m_pmem[i] = 0x0ff;
|
| 447 |
|
|
} else if (m_count >= 40) {
|
| 448 |
|
|
m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
|
| 449 |
|
|
// printf("QSPI: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
|
| 450 |
|
|
m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
|
| 451 |
|
|
} break;
|
| 452 |
|
|
case QSPIF_QPP:
|
| 453 |
|
|
if (m_count == 32) {
|
| 454 |
|
|
m_addr = m_ireg & 0x0ffffff;
|
| 455 |
|
|
m_quad_mode = true;
|
| 456 |
|
|
if (m_debug) printf("QSPI/QR: PAGE-PROGRAM ADDR = %06x\n", m_addr);
|
| 457 |
|
|
assert((m_addr & 0xfc00000)==0);
|
| 458 |
|
|
// m_page = m_addr >> 8;
|
| 459 |
|
|
for(int i=0; i<256; i++)
|
| 460 |
|
|
m_pmem[i] = 0x0ff;
|
| 461 |
|
|
} else if (m_count >= 40) {
|
| 462 |
|
|
m_pmem[m_addr & 0x0ff] = m_ireg & 0x0ff;
|
| 463 |
|
|
// printf("QSPI/QR: PMEM[%02x] = 0x%02x -> %02x\n", m_addr & 0x0ff, m_ireg & 0x0ff, (m_pmem[(m_addr & 0x0ff)]&0x0ff));
|
| 464 |
|
|
m_addr = (m_addr & (~0x0ff)) | ((m_addr+1)&0x0ff);
|
| 465 |
|
|
} break;
|
| 466 |
|
|
case QSPIF_SECTOR_ERASE:
|
| 467 |
|
|
if (m_count == 32) {
|
| 468 |
|
|
m_addr = m_ireg & 0x0ffc000;
|
| 469 |
|
|
if (m_debug) printf("SECTOR_ERASE ADDRESS = %08x\n", m_addr);
|
| 470 |
|
|
assert((m_addr & 0xfc00000)==0);
|
| 471 |
|
|
} break;
|
| 472 |
|
|
case QSPIF_RELEASE:
|
| 473 |
|
|
if (m_count >= 32) {
|
| 474 |
|
|
QOREG(DEVESD);
|
| 475 |
|
|
} break;
|
| 476 |
|
|
default:
|
| 477 |
|
|
break;
|
| 478 |
|
|
}
|
| 479 |
|
|
} // else printf("SFLASH->count = %d\n", m_count);
|
| 480 |
|
|
|
| 481 |
|
|
m_last_sck = sck;
|
| 482 |
|
|
if (m_quad_mode)
|
| 483 |
|
|
return (m_oreg>>8)&0x0f;
|
| 484 |
|
|
else
|
| 485 |
|
|
// return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
|
| 486 |
|
|
return (m_oreg & 0x0100)?2:0;
|
| 487 |
|
|
}
|
| 488 |
|
|
|
