OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [bench/] [cpp/] [uartsim.cpp] - Blame information for rev 33

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
//
2
//
3
// Filename:    uartsim.cpp
4
//
5
// Project:     FPGA library development (S6 development board)
6
//
7
// Purpose:     To emulate the external parameters of a UART device, providing
8
//              the UART output to, and input from, the command
9
//              console/terminal while also providing the controller with
10
//              appropriate busy lines as necessary.
11
//
12
// Creator:     Dan Gisselquist
13
//              Gisselquist Tecnology, LLC
14
//
15
// Copyright:   2016
16
//
17
//
18
#include <unistd.h>
19
#include <fcntl.h>
20
#include <stdio.h>
21
 
22
#include "uartsim.h"
23
 
24
UARTSIM::UARTSIM(int baud_counts, int fdin, int fdout) {
25
        int fctl_flags;
26
 
27
        m_fdin = fdin;
28
        m_fdout = fdout;
29
        m_baud_counts = baud_counts;
30
 
31
        m_tx_busy_count = 0;
32
        m_rx_busy_count = -1;
33
 
34
        // Set the linux O_NONBLOCK on fdin
35
        fctl_flags = fcntl(fdin, F_GETFL, 0);
36
        fcntl(fdin, F_SETFL, fctl_flags | O_NONBLOCK);
37
}
38
 
39
int     UARTSIM::rx(unsigned char &data) {
40
        if (m_rx_busy_count >= 0) {
41
                if (m_rx_busy_count-- == 0) {
42
                        data = (unsigned char)m_rx_next;
43
                        return 1;
44
                }
45
        }
46
 
47
        if (read(m_fdin, &m_rx_next, 1) > 0)
48
                m_rx_busy_count = m_baud_counts;
49
 
50
        return 0;
51
}
52
 
53
int     UARTSIM::tx(int stb, char data) {
54
        if (m_tx_busy_count > 0) {
55
 
56
                // This write may block--if so, we don't care.  Just write it.
57
                if (--m_tx_busy_count == 0)
58
                        if (write(m_fdout, &m_tx_data, 1) != 1)
59
                                perror("O/S Write Err:");
60
                return 1;
61
        } else if (stb) {
62
                m_tx_data = data;
63
                m_tx_busy_count = m_baud_counts;
64
        }
65
 
66
        return 0;
67
}
68
 
69
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.