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\documentclass{gqtekspec}

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%% Filename:    spec.tex

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%% Project:     CMod S6 System on a Chip, ZipCPU demonstration project

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%% Purpose:

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%% Creator:     Dan Gisselquist, Ph.D.

%%              Gisselquist Technology, LLC

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%% Copyright (C) 2015-2016, Gisselquist Technology, LLC

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%% This program is free software (firmware): you can redistribute it and/or

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%% by the Free Software Foundation, either version 3 of the License, or (at

%% your option) any later version.

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%% This program is distributed in the hope that it will be useful, but WITHOUT

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%% for more details.

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%% You should have received a copy of the GNU General Public License along

%% with this program.  (It's in the $(ROOT)/doc directory, run make with no

%% target there if the PDF file isn't present.)  If not, see

%% <http://www.gnu.org/licenses/> for a copy.

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%% License:     GPL, v3, as defined and found on www.gnu.org,

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\usepackage{import}

\usepackage{bytefield}

\usepackage{listings}

\project{CMod S6 SoC}

\title{Specification}

\author{Dan Gisselquist, Ph.D.}

\email{dgisselq (at) ieee.org}

\revision{Rev.~0.4}

\begin{document}

\pagestyle{gqtekspecplain}

\titlepage

\begin{license}

Copyright (C) \theyear\today, Gisselquist Technology, LLC

This project is free software (firmware): you can redistribute it and/or

modify it under the terms of  the GNU General Public License as published

by the Free Software Foundation, either version 3 of the License, or (at

your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT

ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

for more details.

You should have received a copy of the GNU General Public License along

with this program.  If not, see \texttt{http://www.gnu.org/licenses/} for a copy.

\end{license}

\begin{revisionhistory}

0.4 & 3/22/2017 & Gisselquist & Updated to support the 8-bit byte ZipCPU

                \\\hline

0.3 & 5/23/2016 & Gisselquist & Draft for comment, includes ZipOS and PMod

                pin mapping\\\hline

0.2 & 5/14/2016 & Gisselquist & Updated Draft, still not complete \\\hline

0.1 & 4/22/2016 & Gisselquist & First Draft \\\hline

\end{revisionhistory}

% Revision History

% Table of Contents, named Contents

\tableofcontents

\listoffigures

\listoftables

\begin{preface}

The ZipCPU was built with the express purpose of being an area optimized,

32--bit FPGA soft processor.

The S6~SoC is designed to prove that the ZipCPU has met this goal.

There are two side--effects to this.  First, the project proves how capable a

very small FPGA, such as the Spartan~6/LX4 on the CMod--S6, can be and second,

this project provides demonstration implementations of how to interact with a

variety of PMod devices: the audio amplifier, the serial 2--line LCD display,

the USBUART, and the 16--character numeric keypad.

\end{preface}

\chapter{Introduction}

\pagenumbering{arabic}

\setcounter{page}{1}

% What is old

The ZipCPU is a soft core Central Processing Unit (CPU) designed to fit within

an FPGA, to use a minimum amount of the FPGA's resources, and yet to still

provide the services of a fully capable 32--bit computer.  It is based upon a

Von~Neumann architecture and so a single 32--bit wishbone bus provides it with

access to both peripherals and memory.

% What does the old lack?

Previous demonstrations of the ZipCPU have focused on larger FPGAs, such as

the Spartan--6 LX9 and LX25 and the Artix--7 35T.  On these FPGA's,

the ZipCPU runs in a pipelined configuration where it is tightly integrated

with a prefetch/instruction cache.  While these demonstrations have shown that

the ZipCPU can act as a very simple CPU in these environments, they really

haven't demonstrated the ability of the ZipCPU to use only a minimum amount

of the FPGA's resources.

% What is new

The CMod~S6 board provides the opportunity for that demonstration rather nicely.

% What does the new have that the old lacks

\begin{enumerate}

\item The Spartan--6 LX4 FPGA is very limited in its resources:

        It only has 2,400 look--up tables (LUTs), and can only support

        a 16~kB RAM memory.

\item With only 16kB RAM, the majority of any program will need to be placed

        into and run from the flash.

\item While the chip has enough area for the CPU, it doesn't have enough area

        to include the CPU and \ldots write access to the flash, debug access,

        wishbone command access from the UART, pipelined CPU operations,

        a prefetch cache and more.  Other solutions will need to be found as

        part of this project.

\end{enumerate}

Of course, if someone just wants the functionality of a small, cheap, CPU,

this project does not fit that role very well.  While the S6 is not very

expensive at nearly \$70, it is still an order of magnitude greater than it's

CPU competitors in price.  This includes such CPU's as the Raspberry Pi Zero

(\$5), or even the TeensyLC (\$12).

% What performance gain can be expected?

If, on the other hand, what you want is a small, cheap, CPU that can be

embedded within an FPGA without using too much of the FPGA's resources, this

project will demonstrate that possibility as well as showing that the CPU even

has some utility.  Alternatively, if you wish to study how to get a CPU to

work in a small, constrained environment, this project may be what you are

looking for.  Likewise, if you are a software developer forced to get something

running on an FPGA, such as the CMod-S6, you may have just found your answer.

Finally, because the ZipCPU and the included ZipOS are as small and simple as

they are, the code base found here will be simpler to understand than the

code bases for some of these other projects.  For example, the ZipCPU

instruction set is very simple.  With only 29~instructions, it is much

easier to understand and learn than the ARM instruction set.  Further, unlike

the ARM, the entire specification for and description of the ZipCPU is

publicly available.  Likewise, an operating system such as the ZipOS that has

less than \hbox{3,000} lines of code will be much easier to understand than any

Linux operating system--even if it has much less functionality.\footnote{I'm

still entertaining thoughts of placing Linux onto this device.}

\chapter{Architecture}

Fig.~\ref{fig:architecture}

\begin{figure}\begin{center}

\includegraphics[width=5in]{../gfx/s6bones.eps}

\caption{CMod S6 SoC Architecture: ZipCPU and

        Peripherals}\label{fig:architecture}

\end{center}\end{figure}

shows the basic internal architecture of the S6~SoC.  In summary, it consists

of a CPU

coupled with a variety of peripherals for the purpose of controlling the

external peripherals of the S6~SoC: flash, LEDs, buttons, and GPIO.  External

devices may also be added on, and have been added on as part of this project,

such as an audio device, an external serial port, an external keypad, and an

external display.  All of these devices are then available for the CPU to

interact with.

If you are familiar with the ZipCPU, you'll notice this architecture provides

no access to the ZipCPU debug port.  There simply wasn't enough room on the

device.  Debugging the ZipCPU will instead need to take place via other means,

such as dumping all registers and/or memory to the serial port on any reboot,

and making judicious use of the internal scope.

Further, the read/write flash controller couldn't fit in the design along

with the ZipCPU, leaving the ZipCPU with a simpler read--only flash controller

and no ability to write to flash memory.  For this reason, there exists an

alternate CMod S6~SoC architecture, shown in Fig.~\ref{fig:altarchitecture}.

\begin{figure}\begin{center}

\includegraphics[width=5in]{../gfx/altbones.eps}

\caption{Alternate CMod S6 SoC Architecture: Peripherals, with no

        CPU}\label{fig:altarchitecture}

\end{center}\end{figure}

Using this alternate architecture, it is be possible to test the peripherals

and program the flash memory.

The basic approach to loading the board is actually quite simple.  Using the

Digilent ADEPT JTAG configuration program, {\tt djtgcfg}, the alternate

configuration may be written directly to the device.  Once this alternate

configuration has been loaded, the flash may be examined and programmed using

the {\tt zipload} utility.  This utility uses Digilent's Asynchronous Parallel

Port interface (DEPP) to communicate with the device, and in particular to

tell the device what to write to the flash.  When writing to the flash,

the {\tt zipload} utility can program the FPGA configuration into the

configuration section of the flash, as well as computer code into the rest of

the flash.  Once complete, the system may then be reloaded, either by power

down/up or via {\tt djtgcfg}, with the primary configuration file which will

contain an image of the CPU.  The CPU will then begin following the

instructions found in flash memory.

\chapter{Getting Started}

\section{Building the Xilinx BIT file(s)}

The S6SoC nearly fills the CMod-S6 part, so building the BIT files can be a

little tricky, and there are a couple steps to doing this.

The first step is to built a Xilinx project, such as in Fig.~\ref{fig:new-prj}.

\begin{figure}

\begin{center}

\includegraphics[width=6in]{../gfx/newprj.eps}

\caption{Create a New Project}\label{fig:new-prj}

\end{center}\end{figure}

So, once you've downloaded the

repository, create a new project.  We'll call it ``s6soc'', and declare

the working directory of this project and the xilinx project directory to

be in a {\tt xilinx} subdirectory of the main repository.  (You may notice

that bit files already exist in that directory.  You can use those, or

continue here.)

As this is a new project, you'll need to configure your project as in

Fig.~\ref{fig:projopts}

\begin{figure}

\begin{center}

\includegraphics[width=6in]{../gfx/projopts.eps}

\caption{Create a New Project}\label{fig:projopts}

\end{center}\end{figure}

so as to configure for the proper part.  In this case, the proper part comes

from the CMod--S6 schematic, and is shown in the figure.

At this point, you'll want to include the Verilog files into the ISE project.

These files can be found in the {\tt rtl/} project subdirectory.  While not

all Verilog files are used in all configurations, including unused files is

not a problem.  I recommend just including all of them.

Once these Verilog files have been included, there are two possible top level

files.  The first is the main {\tt toplevel.v} file, used by the SoC itself.

This file includes the ZipCPU as the master of all the peripherals.  The

second top level module is found in the {\tt alttop.v} file.  This second file

can be used both to test the CMod--S6 hardware as well as to program the flash

with any programs we wish to run in the S6--SoC.

Two more files need to be included: {\tt cmod.ucf} and {\tt cmodtop.ucf}.  The

first of these, {\tt cmod.ucf}, is the constraint file for the alternate top

file, {\tt alttop.v}.  The latter file, {\tt cmodtop.v}, is the constraint file

for the main top level file, {\tt toplevel.v}.  You'll want to associate these

two files with their respected top level at this time.

Once you have these files included, the next step will be to configure how the

project will be synthesized.  To set these options, first select one of the

two top levels to be the top level, and then right click on the

``Synthesize--XST'' to bring up a process properties menu.  This menu contains

three sub--screens.  If you look at

Figures~\ref{fig:xstopts},

\begin{figure}

\begin{center}

\includegraphics[width=6in]{../gfx/xstopts.eps}

\caption{Synthesis options for low area}\label{fig:xstopts}

\end{center}\end{figure}

%

\ref{fig:hdlopts},

%

\begin{figure}

\begin{center}

\includegraphics[width=6in]{../gfx/hdlopts.eps}

\caption{HDL optimization options for the S6SoC}\label{fig:hdlopts}

\end{center}\end{figure}

%

and~\ref{fig:xpropts},

%

\begin{figure}

\begin{center}

\includegraphics[width=6in]{../gfx/xpropts.eps}

\caption{Xilinx specific options}\label{fig:xpropts}

\end{center}\end{figure}

you can see how I have made these choices to guarantee a minimum LUT count.

%

%

%

Once you finish configuring the synthesizer, it's time to configure the map

process.  This particular menu is within the Implement Design menu, Process

Properties option.  Selecting this menu option brings up a dialog, such as

Fig.~\ref{fig:mapopts}.

\begin{figure}

\begin{center}

\includegraphics[width=6in]{../gfx/mapopts.eps}

\caption{Map parameters necessary to optimize the S6SoC}\label{fig:mapopts}

\end{center}\end{figure}

From Fig.~\ref{fig:mapopts}, you can see what optimization settings were

necessary for getting the S6SoC to fit within the CMod--S6 device.

Two configuration screens remain.  The first, shown in

Fig.~\ref{fig:configopts},

\begin{figure}

\begin{center}

\includegraphics[width=6in]{../gfx/configopts.eps}

\caption{Configuration Options}\label{fig:configopts}

\end{center}\end{figure}

controls how the FPGA will be configured.  Important on this screen is the

fact that the CMod--S6 has a Quad SPI flash, and that it can be run from a

clock as fast as 108~MHz.  Here, we choose 16~MHz although I know of no reason

why the clock speed could not be made faster.

As a final configuration screen, there are options for generating the

programming (bit) file.  These are shown in Fig.~\ref{fig:bitfopts}.

\begin{figure}

\begin{center}

\includegraphics[width=6in]{../gfx/bitfopts.eps}

\caption{Programming file (Bit-File) generation options}\label{fig:bitfopts}

\end{center}\end{figure}

From the standpoint of the CMod--S6, the important configuration item here is

that we would like to compress the bit file, so that we can pack as much

information into our flash device as possible.

Having gone through all of your configuration options, you may now build the

two configurations, {\tt toplevel.bit} and {\tt alttop.bit} which are used in

this distribution.

{\tt make axload} in the main directory (assuming the Digilent ADEPT utilities

are installed) will load the alternate configuration into the flash, while

{\tt make xload} will load the main configuration into the flash.  For our

purposes, and until you have a compiled program to run, you will want to load

the alternate configuration into the flash.

\section{Building the Compiler}

The ZipCPU compiler comes as source from the ZipCPU distribution.  To build

this compiler, clone the ZipCPU distribution and follow the build and

installation instructions within it.  Ever afterwards, you'll want the ZipCPU

toolchain, {\tt zip-gcc}, {\tt zip-as}, {\tt zip-ld}, etc., in your

path.\footnote{You may need to install several packages to do this, such as:

flex, bison, libbison-dev, libgmp10, libgmp-dev, libmpfr-dev, libmpc-dev,

libelf-dev, ncurses-dev, libelf-dev, and verilator.}

%% git clone

%% Setting zip_param_cis to zero

%% Setting ZIP_DIVIDE to zero

%% Setting ZIP_PIPELINED to zero        -- Disables the ZIP_ATOMIC instructions

%% Setting ZIP_THUMB to zero            -- Disables the CIS instructions

\section{Building the ADEPT Utilities}

You will also need a copy of Digilent's ADEPT software installed on your

system in order to use the CMod--S6.  This includes not only the ADEPT

utilities, but also ADEPT software development kit and it's runtime environment.

We'll need these pieces of software to provide both the {\tt djtgcfg} program

to load the FPGA with our designs, as well as the {\tt DEPP} port, provided by

both the SDK and the runtime environment, necessary to communicate with our

board.

% Install the Digilent ADEPT utilities

%   Expand the tar file

%   tar -xvzf digilent.adept.utilities_2.2.1-x86_64.tar.gz

%   Install them

%   cd digilent.adept.utilities_2.2.1-x86_64.tar.gz

%   sudo ./install.sh

%       Answer Y to install the binaries into /usr/local/bin, and again

%       to place the manual pages into /usr/local/man.

% Install the Digilent ADEPT Runtime

% Answer Y to store the libraries into /usr/local/lib64/digilent/adept

% Answer Y to install system binaries into /usr/sbin

% Answer Y to install data into /usr/share/digilent/adept/data

% Answer Y to install runtime configuration data files into /etc

%

\section{Building and Running the Host Software}

Once you have the ADEPT utilities installed, you may then build the software

in the {\tt sw/host} project subdirectory.  The makefile in this directory

has a reference to the location of ADEPT include files, which you may need to

update according to where you have installed ADEPT.  You may also need to

adjust the library path, so that it properly references the ADEPT libraries.

(The library path is currently hard coded into the Makefile.)

\section{Building the ZipCPU Software}

Once you have the ZipCPU toolchain built, you may then build the ZipCPU software

which will be placed onto the board.  This software may be found in the

{\tt sw/dev} directory.  The ZipOS example can be found in the {\tt sw/zipos}

directory.  A {\tt make} command executed in each of these directories should

build the ZipCPU software for the board.

\section{Connecting the PMods to your board}

The S6~SoC supports four PMods: The PModUSBUART, the PModAMP2 pwm to audio

amplifier, the PModCLS two line LCD display, and the PModKYPD sixteen

character keypad.  These need to be wired up to the CMod~S6 as shown in

Fig.~\ref{fig:pmodplaces} on page~\pageref{fig:pmodplaces}.

\section{Loading Software onto your SoC}

Once you have all the software loaded, you may wish to try a simple LED

program.  You may find the {\tt sw/dev/blinky.c} program suitable for this

purpose.  To run this program, you will need to follow a series of steps:

\begin{enumerate}

\item Build the {\tt sw/dev/blinky} program.

\item Build both Xilinx configurations, {\tt alttop.bit} and {\tt toplevel.bit}.

        The main makefile will look for these files in the {\tt xilinx/}

        project subdirectory that you made when you created the project.

\item From the main project subdirectory, run {\tt make axload} to load

        the alternate configuration onto your board.  (You do have your board

        plugged in, right?)

\item Then you can run the {\tt zipload} program found in the {\tt sw/host}

        directory.  {\tt zipload} takes one or two arguments.  In this

        example, we'll give it a first argument of the {\tt xilinx/toplevel.bit}

        file, and a second argument of the program we would like to run,

        {\tt sw/dev/blinky}.

\item Assuming {\tt zipload} completed successfully, you can then either run

        {\tt make xload} from the main directory, or you may remove and

        reconnect power to your board.

\item A blinking light demonstration should now be running on your board.

\end{enumerate}

\chapter{Software}

This chapter provides an overview of the software that is available to support

the S6~SoC.  This includes not only the RTL, the Makefiles, and the software

that will run on the ZipCPU within the S6~SoC, but also the support software

necessary for communicating with the S6~SoC in its alternate configuration.

\section{Directory Structure}

\begin{itemize}

\item[{\tt sim/verilator/}] Contains software for emulating the S6~SoC

        without the S6 present.

        All of the bench testing software is written in C++, so it is found in

        this directory.  Primary among these programs is the {\tt zip\_sim}

        program which will simulate the ZipCPU within the S6~SoC.  Specifically,

        it simulates everything at or below the {\tt busmaster.v} level.

        Some, although not all, of the peripherals have been simulated and

        made a part of this simulation.  These include the Quad--SPI flash,

        the UART, the LED's and the GPIOs.

\item[{\tt doc/}] All of the documentation for the S6~SoC project may be

        found in this documentation directory.  Specifically, I would commend

        your attention to anything with a {\tt .pdf} extension, as these

        are the completed documents.  Among these you should find a copy of the

        GPL copyright under which this software is released, as well as a

        pre--built copy of this document.

  \begin{itemize}

        \item[{\tt doc/gfx/}] Here is where the graphics are located in

                support of this specification document.

        \item[{\tt doc/src/}] And here is where the \LaTeX files are

                kept that were used in building both this document as well as

                the GPL copyright.

  \end{itemize}

\item[{\tt rtl/}] Verilog files.  The two top--level files are

        {\tt toplevel.v} for the primary top level module, and {\tt alttop.v}

        for the alternate load.

  \begin{itemize}

        \item[{\tt rtl/cpu}] Verilog files containing the ZipCPU core and

                peripherals.  The toplevel file here is the {\tt zipbones.v}

                file, although some of the peripherals, such as the

                {\tt ziptimer.v} are referenced independently.

  \end{itemize}

\item[{\tt sw/}] The main software directory, primarily a repository

        for software subdirectories beneath it.

  \begin{itemize}

        \item[{\tt sw/dev/}]  This directory holds a variety of

                simple programs for the ZipCPU, such as {\tt blinky},

                {\tt helloworld}, {\tt doorbell} and {\tt doorbell2}, as well

                as software drivers for various peripherals, such as the

                real--time clock simulator, and the keypad and display device

                drivers.

                One key file in this directory is the {\tt cputest.c} file,

                which provides a basic test of the CPU and its capabilities.

        \item[{\tt sw/host/}]  This directory holds support software which

                can be built on and run on the host machine.  Building this

                software will involve adjusting the Makefile so that it knows

                where your local ADEPT installation directory is.  Once built,

                you will find a variety of very useful programs within here.

        \item[{\tt sw/zipos/}]  This directory contains the source code for

                a rudimentary, very basic, pre-emptive multitasking operating

                system that I call the ZipOS.

  \end{itemize}

\end{itemize}

\section{ZipCPU Tool Chain}

To build programs for the ZipCPU, you will need the ZipCPU toolchain.  You

can find this as part of the ZipCPU project, available at OpenCores.  Building

the ZipCPU project should result in a set of binaries in the

\hbox{\tt sw/install/cross-tools/bin/} subdirectory of your ZipCPU project

directory.  Make this

directory a part of your path, and you should be able to build the CMod S6

ZipCPU software.  Specifically, you will need to use {\tt zip-gcc},

{\tt zip-as}, {\tt zip-ld}, and {\tt zip-cpp}.  Other tools, such as

{\tt zip-objdump} and {\tt zip-readelf}, may also prove to be very useful when

trying to debug what is going on within the SoC.

\section{Bench Test Software}

Bench testing software currently consists of the {\tt zip\_sim} program found

within {\tt sim/verilator}.  This program requires Verilator to run, and

simulates in a cycle accurate fashion, the entire S6~SoC from {\tt busmaster.v}

on down.  Further, the external Quad--SPI flash memory, UART, and LED's are

also simulated, although the 2--line display, audio, and keypad are not.

\section{Host Software}

Several software programs have been built to support the S6~SoC from a nearby

host.  These programs include:

\begin{itemize}

\item {\tt dumpuart}: My current approach to debugging involves dumping the

        state of the registers and memory to the UART upon reboot.  The

        dumpuart command found here is designed to make certain that the UART

        is first set up correctly at 9600~Baud, and second that everything

        read from the UART is directly sent to both a file and to the screen.

        In this fashion, it is similar to the UNIX {\tt tee} program, save for

        its serial port attachment.

\item {\tt readflash}: As I am loathe to remove anything from a device that

        came factory installed, the {\tt readflash} program reads the original

        installed configuration from the flash and dumps it to a file.

        This program is only useful when the alternate configuration is loaded.

\item {\tt wbregs}: This program offers a capability very similar to the

        PEEK and POKE capability Apple user's may remember from before the

        days of Macintosh.  {\tt wbregs <address>} will read from the

        Wishbone bus the value at the given address.  Likewise

        {\tt wbregs <address> <value>} will write the given value into the

        given address.  While both address and value have the semantics of

        numbers acceptable to {\tt strtoul()}, the address can also be a named

        address.  Supported names can be found in {\tt regdefs.cpp}, and their

        register mapping in {\tt regdefs.h}.

        As examples, {\tt wbregs version}, will return the build date, or

        version of the RTL.  {\tt wbregs spio} reads the special purpose

        I/O register, and {\tt wbregs gpio 0xffffffff} will set all output

        GPIO ports high while {\tt wbregs gpio 0xffff0000} will set all

        output GPIO ports to ground.

        This program is only useful when the alternate configuration is loaded.

        When the primary {\tt toplevel.v} configuration is loaded, the ZipCPU

        will be able to read and write these registers in a similar fashion.

\item {\tt zipload}: This is the primary program you will need to get your

        software loaded on the CMod.  It takes two arguments.  The first is

        the name of the primary Xilinx configuration file, and the second is

        the name of the ZipCPU program you wish to write to Flash memory.

        Each of these arguments is optional.  For example, if a configuration

        file is given, the loader will load the primary configuration.  If

        a ZipCPU program is given, the program will be loaded into the program

        memory area and the configuration file areas will be left untouched.

        As with {\tt wbregs}, this program is only useful when the alternate

        configuration is loaded.

\end{itemize}

\section{ZipCPU Programs}

The following are a list of simple, independent, single-task example programs

that will run on the S6~SoC:

\begin{itemize}

\item {\tt blinky}: This is a very simple program similar to hello world, with

        the difference that the lights have a bit of a different response, the

        hello world message is written slower, and interrupts are used to

        accomplish this purpose.

\item {\tt helloworld}: The first program any programmer should build,

        ``Hello, world!''  This program sends the string, ``Hello, world!''

        over the UART connection once per second.  It is a very valuable

        program because, if you can get this program running, you know you have

        a lot of things working and working correctly.  For example, running

        this program means you can run the {\tt zip-gcc} compiler, load

        the auxiliary configuration, load the program info flash memory, load

        the primary configuration, and read from the UART port.  It also means

        that you must have the UART port properly configured and wired to your

        CMod board.

        Unlike other versions of Hello World that you may be familiar with,

        this one does not use the C--library.  It programs the hardware

        directly.

\item {\tt cputest}: This is a simple test of the CPU and all of its

        functionality.

        The functionality proven is primarily assembly

        level, but it does require the C compiler to put its framework

        together.

        {\tt cputest} is actually one of two programs built from the same

        source.  The other is named {\tt cputestcis}, and specifically

        allows the complex instruction set (CIS) instructions whereas

        {\tt cputest} specifically disallows them.  The difference, therefore,

        is in the command line parameters given to the assembler (via the

        compiler).

\item {\tt doorbell}: This annoying program verifies the functionality of the

        audio device by playing a doorbell sound to the audio port.  It will

        then wait ten seconds, and play the doorbell sound again (and again,

        and again).  (It gets old after a while ...)

\item {\tt doorbell2}: This adds to the functionality of the {\tt doorbell}

        program a wait for keypress, and a display of the current time on the

        2--line display.  While almost our fully functional ZipOS program, this

        does not include any menus to configure the device or set time, since

        it doesn't include any keypad functionality.

\item {\tt kptest}: A test of whether or not they keypad driver works.  When

        run, anytime a key is pressed, the key's associated printable character

        will be sent to the UART.  Further, pressing an `F' on the keypad will

        also send a newline over the UART, in case you wish to keep your lines

        from getting too long.

\end{itemize}

\section{ZipOS}

The ZipOS is a brand new operating system, specifically designed to run on the

ZipCPU.  It is both pre--emptive and multitasking, although with many

limitations.  Those familiar with the internals of other operating systems, such

as Linux, may laugh that I call this an Operating System at all: it has no

memory management unit, no paging, no virtual memory, no file I/O access, no

network stack, no ability to dynamically add or remove tasks, indeed it hardly

has any of the things most often associated with an Operating System.  It does,

however, handle interrupts, support multiple pre--emptive tasks in a

multitasking, timesharing fashion, and it supports some very basic and

rudimentary system calls.  In a similar fashion, it does contain just about all

of the functionality necessary for a multi--tasking microcontroller built

around a do--forever loop.  For its size, I consider it an impressive

achievement.  You are welcome to disagree with me.

This version of the ZipOS starts in the {\tt resetdump.s} code, so that upon

any startup the ZipOS will dump register contents, the BusError register, and

any scope contents to the UART--assuming that the scope had been triggered.

This can take some time, so you may wish to configure what you really wish to

send--if anything.  If desired, {\tt resetdump} can be configured to also

dump the entire memory as well while only using ten memory locations in its own

support.  All of this is quite useful in case the

ZipCPU encounters a bus error or other sort of error that causes it to hang,

stall, or reboot, as the CPU registers are very carefully not touched prior to

being sent to the UART output port.  This extends to all registers save the

supervisor PC and CC registers, which would've been reset by a reboot anyway.

{\tt resetdump.s} then calls a rudimentary bootloader, to load the parts of

the ZipOS that need to run faster into Block RAM.  The choice of what parts

to load into Block RAM is made on a file by file basis, and found within

the linker script, {\tt cmodram.ld}.

Upon completion, {\tt resetdump.s} calls the entry routine for the O/S,

{\tt kernel\_entry()} found in {\tt kernel.c}.  This is the main task loop for

the entire O/S, and worth studying if you are interested in understanding how

the O/S works.

The user tasks are found (mostly) within {\tt doorbell.c}, also found in the

ZipOS directory.  This file contains two kernel entry points, {\tt kntasks()},

which returns the number of user tasks the kernel needs to know about, and

{\tt kinit()}, which builds each of the tasks and connects their file

descriptors to the various devices they will be referencing.

\subsection{System Calls}

The ZipOS supports a variety of system calls, listed here:

\begin{itemize}

\item {\tt int wait(unsigned event\_mask, int timeout)}

        Halts the execution of a process until an event matching the

        {\tt event\_mask} takes place, or a {\tt timeout} (in milliseconds)

        has been reached.  The events that can take place are a

        bitmask of the various interrupts the CPU supports, together with a

        bitmask of the software interrupt values found in {\tt swint.h}.

        The {\tt timeout} value can either be zero, to return immediately with

        the list of events that have taken place, negative, to wait

        indefinitely, or a positive number of milliseconds in order to wait at

        least that time for the event of interest to take place.

        Waiting on a zero event mask allows a process to sleep for any number

        of requested milliseconds.

        When wait returns, any events returned by the wait have been cleared.

        The other thing to be aware of is that events may accumulate before the

        wait system call.  Nothing within the wait system call clears prior

        events.  These prior events be returned and cleared, though, if

        the wait call indicates an interest in those events.

        Upon return, the a bitmask of events that have taken place will be

        returned to the process.

\item {\tt int clear(unsigned event\_mask, int timeout)}

        This system call works closely with the wait system call.  Indeed,

        when the timeout given is zero, the two function nearly identically.

        It clears any of the requested events which may be pending, and returns

        a bit mask of the events that were pending and cleared.

        However, if the timeout is given (and is positive), then {\tt clear()}

        starts a timer.  Once the timer has completed, a timeout event,

        {\tt SWINT\_TIMEOUT}, will be generated and made available to the task

        to wait upon it.

        In a similar fashion, if the timeout is negative, then any pending

        timeout is cleared.

\item {\tt void post(unsigned event\_mask)}

        Certain software devices, such as the real--time clock and the doorbell

        reader, need the ability of being able to post events to any listener

        within the O/S.  The POST system call allows them to POST events in

        this manner.

        Were the ZipOS to be closer to a secure O/S, it might restrict what

        events each process could post.  Right now, however, any process can

        post any event--whether it be a hardware or a software generated event.

\item {\tt void yield(void) }

        This is simply a way of being nice to other processes.  This system

        call takes no arguments and simply asks the scheduler to schedule the

        next process.  It does not take this process off of the ready to run

        list, so the next process may be this one.  However, since the scheduler

        is a round--robin scheduler, it will only return to this process once

        it has gone through all other available processes checking whether or

        not they are available to be run.

\item {\tt int read(int fid, void *buf, int len)}

        This is roughly the same system call as the POSIX read() system

        call.  It reads some number of words (not octets) from the file

        descriptor (device) specified by {\tt fid} into the memory address

        range starting at {\tt buf} and {\tt len} words long.  If the memory

        requested is unavailable,

        the read will wait until it is available, possibly indefinitely.

        Upon return, the {\tt read()} function call returns the number of

        words actually read, or a negative value on error.

        As a future feature, a {\tt read()} system call should be able to be

        interrupted by a timeout.  This feature has not (yet) been implemented,

        but will likely be implemented via a combination of the {\tt clear()}

        system calls ability to set timeouts together with the {\tt read()}

        functions ability to wait for available data.

\item {\tt int write(int fid, void *buf, int len)}

        This is roughly the same system call as the POSIX {\tt write()} system

        call.  It writes some number of memory addresses (words, not octets),

        to the given file descriptor.  If there is no reader task or device

        associated with the file descriptor, then the {\tt write()} system

        call will block forever once the internal pipe fills up.  Otherwise,

        if something is reading from the file descriptor's pipe, the writing

        task will only stall until the data is either written to the receiving

        task, or copied into a memory buffer.

        Upon return, the {\tt write()} system call returns the number of words

        actually written to the system pipe (not necessarily the number that

        have been read), or a negative value on error.

\item {\tt unsigned time(void) }

        Returns the number of seconds since startup.  Eventually, this will

        return the number of seconds since January 1, 1970, and be identical

        to the UNIX system time() command, but that may not happen on this

        project.

% \item SEMGET

% \item SEMPUT

\item {\tt void *malloc(void)}

        Allocates memory from the system/kernel heap.  This is a very low

        overhead memory allocator that, while it does allocate memory, cannot

        free it later.  It is nearly 100\% efficient since only one memory

        address, the top of the heap, is used to determine what memory has

        been allocated.

\item {\tt void free(void *buf)}

        This function is a do--nothing stub.

\end{itemize}

\subsection{Scheduler}

The ZipOS currently supports only a round--robin scheduler.  Tasks are executed

in the order they were created, as long as they are available to be executed.

If no tasks are available to be run, the Scheduler will run the idle task which

puts the CPU to sleep while waiting for an interrupt.

\chapter{Operation}

The {\tt doorbell} program found in {\tt sw/zipos|} has been built to

illustrate the operation of both the ZipCPU the ZipOS, as well as showing off

how all of the various peripherals work.  It was envisioned after my family

and I experienced an unexpected visitor during the wee hours of the morning.

The {\tt doorbell} program is designed to couple the doorbell and the exterior

lights to a single button.  Hence, when the doorbell to the house is pressed,

the exterior light (an LED in the demo) is turned on for a half an hour.  This,

then, would make it difficult for someone to see inside during this time.

This chapter will present a discussion of how that {\tt doorbell} program works.

To run the {\tt doorbell} program, you will first need to build the various

RTL and software support programs just to get the {\tt doorbell} program on

the device:

\begin{enumerate}

\item First build the primary and alternate .bit files by building with

        {\tt toplevel.v} and then {\tt alttop.v} as your top--level RTL files.

        I like to place my Xilinx work directory into a {\tt xilinx/} project

        subdirectory, and if you do the same the load scripts that are

        referenced next will work.

        Before going on, double check that both configuration .bit files were

        created, and that they each fit within the device (there would be errors

        if they did not), and that they met their respective timing

        requirements.

\item Then, load the alternate bit file into the S6~SoC.  You will need

        the Digilent tools installed in order to do this.  Having done so,

        you may run {\tt make axload} from the main project directory.

        If you didn't run the Xilinx ISE from within a {\tt xilinx/} project

        subdirectory,

        you may need to find your .bit files and adjust where they load

        from, but this should be fairly straight--forward from the instructions

        within the Makefile.

\item Build the software found in the host directory.  This software depends

        upon Digilent's ADEPT toolsuite, so you will need to adjust the

        Makefile so that it references the toolsuite.

\item Using {\tt wbregs}, you may now test your configuration.  {\tt wbregs}

        works like the peek and poke programs from a generation ago.

        {\tt wbregs <address>} will return the value of the memory (or

        peripheral) found at the {\tt <address>}.  Some addresses have names,

        such as {\tt UART}, {\tt SPIO}, {\tt GPIO}, {\tt PIC}, and so forth.

        These names are found in {\tt sw/host/regdefs.cpp}, and their

        mappings in {\tt sw/host/regdefs.h}.

        As examples, if you type {\tt wbregs version} you should be able

        to read the version (a.k.a. build date) from the currently installed

        .bit file.  Likewise if you type {\tt wbregs uart 65}, you should see

        an `A' (i.e. a 65) sent from the S6~SoC over the serial port.

        {\tt wbregs uart} by itself will read a single character from the

        serial port and so on.

        You should be able to test all of your peripherals by hand using

        {\tt wbregs}: GPIO, Flash, UART, keypad, buttons, LEDs, Interrupt

        controller, timer, etc.\footnote{The display and audio devices may be

        more difficult since these require multiple interactions over the

        course of a short period of time to work.}  This should give you some

        confidence in how these peripherals work, should you need it.  You

        may also use this time to verify that your wiring is properly set up.

\item If you wish to make certain you keep track of the original Flash bitfile

        that came with your device, you may read it out using {\tt readflash}.

        This will dump the contents of you flash onto {\tt qspiflash.bin}.

        You may then wish to change the name of this file, lest you overwrite

        it by running {\tt readflash} again later.

        If you wish to restore this bitfile later, load the alternate

        configuration and run {\tt zipload qspiflash.bin}.

\item At this point, it's time to build the programs for the ZipCPU.  To do

        this, you will first need to download the ZipCPU project.  When

        building that project, it will create a directory of programs

        (including its compiler) in the {\tt sw/install/cross-tools/bin/}

        subdirectory of the ZipCPU project directory.

        Include this directory into your path.

\item Change into the {\tt sw/dev} project subdirectory to build some device

        testing files.  {\tt make} by itself should build some of these.

        You should now be ready to run some basic tests on the S6~SoC.

\item Let's test the UART first: back out to the main project directory,

        and run\break

        {\tt sw/host/zipload sw/dev/helloworld} and then {\tt make xload}.

        Now, examine your UART port.  (You do have the PModUSBUART installed

        and connected, right?)  You should see ``Hello, World!'' printed

        over and over again once each second.

\item You may try other test files in a similar manner, such as

        {\tt sw/dev/doorbell} and\break

        {\tt sw/dev/doorbell2}.  The first of these will just play the

        doorbell over and over again, whereas the second one will wait for a

        button press before playing the doorbell sound.

\item Now let's go and build the ZipOS together with it's user files.  To do

        this, enter into the {\tt sw/zipos/} directory and type

        {\tt make}.  If all goes well, you should now have a program named

        {\tt sw/zipos/doorbell} which you can load into your S6~SoC as

        well.

\item A final load, and we'll be done.  To do this, make {\tt axload} again,

        and this time

        {\tt sw/host/zipload xilinx/toplevel.bit sw/zipos/doorbell}.

        When you power on your device the next time, or after you

        {\tt make xload}, you'll find the ZipOS running on the ZipCPU.

\item To test the doorbell, press one of the buttons.  You should hear a

        doorbell coming out of the PModAMP2 audio port.

\item You should also be able to read the time on the LCD display.  It will be

        the wrong time (the number of seconds since power on \ldots) initially.

        To set the correct time, press `A' on the keypad and then type in the

        6--digit time: HHMMSS.

        If you make a mistake, the `C' key can be used for a backspace.

\item You can also set the time of ``dawn'' by pressing a `B' on the keypad

        and then typing in the time ``dawn'' should be at.  The same is

        true for dusk, only you'll need to start that by pressing a `C' on the

        keypad.

\item Now, when the doorbell rings, the LCD will show the time the doorbell

        was pressed.  If the time is at night, the outdoor light (oops, I

        mean LED\#3) will turn on for a half an hour (currently set to

        30~seconds, since I don't have the patience to wait a half hour while

        testing).

\end{enumerate}

Now that you've made it this far, you can go back and examine what was done

along the way, and perhaps even modify it for your own personal application.

\chapter{Registers}

There are several address regions on the S6~SoC, as shown in

Tbl.~\ref{tbl:memregions}.

\begin{table}[htbp]

\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline

\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline