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dgisselq |
///////////////////////////////////////////////////////////////////////////////
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//
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// Filename: idecode.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: This RTL file specifies how instructions are to be decoded
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// into their underlying meanings. This is specifically a version
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// designed to support a "Next Generation", or "Version 2" instruction
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// set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
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// in cpudefs.v.
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//
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// I expect to (eventually) retire the old instruction set, at which point
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// this will become the default instruction set decoder.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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`define CPU_CC_REG 4'he
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`define CPU_PC_REG 4'hf
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//
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`include "cpudefs.v"
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//
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//
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//
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module idecode(i_clk, i_rst, i_ce, i_stalled,
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i_instruction, i_gie, i_pc, i_pf_valid,
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i_illegal,
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o_phase, o_illegal,
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o_pc, o_gie,
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o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
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o_cond, o_wF,
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o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
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o_wR, o_rA, o_rB,
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o_early_branch, o_branch_pc, o_ljmp,
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o_pipe
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);
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parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
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IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
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input i_clk, i_rst, i_ce, i_stalled;
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input [31:0] i_instruction;
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input i_gie;
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input [(AW-1):0] i_pc;
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input i_pf_valid, i_illegal;
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output wire o_phase;
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output reg o_illegal;
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output reg [(AW-1):0] o_pc;
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output reg o_gie;
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output reg [6:0] o_dcdR, o_dcdA, o_dcdB;
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output wire [31:0] o_I;
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output reg o_zI;
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output reg [3:0] o_cond;
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output reg o_wF;
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output reg [3:0] o_op;
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output reg o_ALU, o_M, o_DV, o_FP, o_break, o_lock;
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output reg o_wR, o_rA, o_rB;
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output wire o_early_branch;
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output wire [(AW-1):0] o_branch_pc;
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output wire o_ljmp;
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output reg o_pipe;
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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wire o_dcd_early_branch;
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wire [(AW-1):0] o_dcd_branch_pc;
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reg o_dcdI, o_dcdIz;
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wire [4:0] w_op;
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wire w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire [3:0] w_cond;
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wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
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wire w_wR, w_rA, w_rB, w_wR_n;
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wire w_ljmp;
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generate
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if (EARLY_BRANCHING != 0)
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assign w_ljmp = (iword == 32'h7c87c000);
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else
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assign w_ljmp = 1'b0;
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endgenerate
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wire [31:0] iword;
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`ifdef OPT_VLIW
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reg [16:0] r_nxt_half;
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assign iword = (o_phase)
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// set second half as a NOOP ... but really
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// shouldn't matter
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? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 }
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: i_instruction;
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`else
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assign iword = { 1'b0, i_instruction[30:0] };
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`endif
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assign w_op= iword[26:22];
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assign w_mov = (w_op == 5'h0f);
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assign w_ldi = (w_op[4:1] == 4'hb);
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assign w_cmptst = (w_op[4:1] == 4'h8);
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assign w_ldixx = (w_op[4:1] == 4'h4);
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assign w_ALU = (~w_op[4]);
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// 4 LUTs
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assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
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iword[30:27] };
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// 4 LUTs
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assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
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iword[17:14] };
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// 0 LUTs
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assign w_dcdA = w_dcdR;
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// 2 LUTs, 1 delay each
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assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
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assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
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// 0 LUTs
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assign w_dcdA_pc = w_dcdR_pc;
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assign w_dcdA_cc = w_dcdR_cc;
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// 2 LUTs, 1 delays each
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assign w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG);
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assign w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG);
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// Under what condition will we execute this
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// instruction? Only the load immediate instruction
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// is completely unconditional.
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//
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// 3+4 LUTs
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assign w_cond = (w_ldi) ? 4'h8 :
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(iword[31])?{(iword[20:19]==2'b00),
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1'b0,iword[20:19]}
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: { (iword[21:19]==3'h0), iword[21:19] };
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// 1 LUT
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assign w_dcdM = (w_op[4:1] == 4'h9);
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// 1 LUT
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assign w_dcdDV = (w_op[4:1] == 4'ha);
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// 1 LUT
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assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
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// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
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// Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV
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assign w_rA = (w_dcdFP)
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// Divide's read A
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||(w_dcdDV)
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// ALU read's A, unless it's a MOV to A
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// This includes LDIHI/LDILO
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||((~w_op[4])&&(w_op[3:0]!=4'hf))
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// STO's read A
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||((w_dcdM)&&(w_op[0]))
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// Test/compares
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||(w_op[4:1]== 4'h8);
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// 1 LUTs -- do we read a register for operand B? Specifically, do
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// we need to stall if the register is not (yet) ready?
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assign w_rB = (w_mov)||((iword[18])&&((~w_ldi)&&(~w_ldixx)));
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// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
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assign w_wR_n = ((w_dcdM)&&(w_op[0]))
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||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
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||(w_cmptst);
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assign w_wR = ~w_wR_n;
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//
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// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
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//
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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// and writes to the PC/CC register(s).
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assign w_wF = (w_cmptst)
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||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
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||((w_ALU)&&(~w_mov)&&(~w_ldixx)
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&&(iword[30:28] != 3'h7))));
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// Bottom 13 bits: no LUT's
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// w_dcd[12: 0] -- no LUTs
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// w_dcd[ 13] -- 2 LUTs
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// w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
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// w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
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reg [22:0] r_I;
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wire [22:0] w_I, w_fullI;
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wire w_Iz;
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assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI
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:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move
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:((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
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: { {(23-14){iword[13]}}, iword[13:0] }
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));
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`ifdef OPT_VLIW
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wire [5:0] w_halfI;
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assign w_halfI = (w_ldi) ? iword[5:0]
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:((iword[5]) ? 6'h00 : {iword[4],iword[4:0]});
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assign w_I = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI;
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`else
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assign w_I = w_fullI;
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`endif
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assign w_Iz = (w_I == 0);
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`ifdef OPT_VLIW
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//
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// The o_phase parameter is special. It needs to let the software
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// following know that it cannot break/interrupt on an o_phase asserted
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// instruction, lest the break take place between the first and second
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// half of a VLIW instruction. To do this, o_phase must be asserted
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// when the first instruction half is valid, but not asserted on either
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// a 32-bit instruction or the second half of a 2x16-bit instruction.
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reg r_phase;
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initial r_phase = 1'b0;
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always @(posedge i_clk)
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if (i_rst) // When no instruction is in the pipe, phase is zero
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r_phase <= 1'b0;
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else if (i_ce)
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r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
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// Phase is '1' on the first instruction of a two-part set
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// But, due to the delay in processing, it's '1' when our output is
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// valid for that first part, but that'll be the same time we
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// are processing the second part ... so it may look to us like a '1'
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// on the second half of processing.
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assign o_phase = r_phase;
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`else
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assign o_phase = 1'b0;
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`endif
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initial o_illegal = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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o_illegal <= 1'b0;
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else if (i_ce)
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begin
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`ifdef OPT_VLIW
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o_illegal <= (i_illegal);
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`else
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o_illegal <= ((i_illegal) || (i_instruction[31]));
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`endif
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if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5))
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o_illegal <= 1'b1;
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if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
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o_illegal <= 1'b1;
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else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
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o_illegal <= 1'b1;
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if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7))
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o_illegal <= 1'b1;
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else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
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o_illegal <= 1'b1;
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if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
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&&(
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(w_op[2:0] != 3'h2) // LOCK
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&&(w_op[2:0] != 3'h1) // BREAK
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&&(w_op[2:0] != 3'h0))) // NOOP
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o_illegal <= 1'b1;
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end
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always @(posedge i_clk)
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if (i_ce)
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begin
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`ifdef OPT_VLIW
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if (~o_phase)
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begin
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o_gie<= i_gie;
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// i.e. dcd_pc+1
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o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
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end
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`else
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o_gie<= i_gie;
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o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
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`endif
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// Under what condition will we execute this
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// instruction? Only the load immediate instruction
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// is completely unconditional.
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o_cond <= w_cond;
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// Don't change the flags on conditional instructions,
|
| 301 |
|
|
// UNLESS: the conditional instruction was a CMP
|
| 302 |
|
|
// or TST instruction.
|
| 303 |
|
|
o_wF <= w_wF;
|
| 304 |
|
|
|
| 305 |
|
|
// Record what operation/op-code (4-bits) we are doing
|
| 306 |
|
|
// Note that LDI magically becomes a MOV
|
| 307 |
|
|
// instruction here. That way it's a pass through
|
| 308 |
|
|
// the ALU. Likewise, the two compare instructions
|
| 309 |
|
|
// CMP and TST becomes SUB and AND here as well.
|
| 310 |
|
|
// We keep only the bottom four bits, since we've
|
| 311 |
|
|
// already done the rest of the decode necessary to
|
| 312 |
|
|
// settle between the other instructions. For example,
|
| 313 |
|
|
// o_FP plus these four bits uniquely defines the FP
|
| 314 |
|
|
// instruction, o_DV plus the bottom of these defines
|
| 315 |
|
|
// the divide, etc.
|
| 316 |
|
|
o_op <= (w_ldi)? 4'hf:w_op[3:0];
|
| 317 |
|
|
|
| 318 |
|
|
// Default values
|
| 319 |
|
|
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
|
| 320 |
|
|
o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
|
| 321 |
|
|
o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
|
| 322 |
|
|
o_wR <= w_wR;
|
| 323 |
|
|
o_rA <= w_rA;
|
| 324 |
|
|
o_rB <= w_rB;
|
| 325 |
|
|
r_I <= w_I;
|
| 326 |
|
|
o_zI <= w_Iz;
|
| 327 |
|
|
|
| 328 |
|
|
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst); // 1 LUT
|
| 329 |
|
|
o_M <= w_dcdM;
|
| 330 |
|
|
o_DV <= w_dcdDV;
|
| 331 |
|
|
o_FP <= w_dcdFP;
|
| 332 |
|
|
|
| 333 |
|
|
o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
|
| 334 |
|
|
o_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
|
| 335 |
|
|
`ifdef OPT_VLIW
|
| 336 |
|
|
r_nxt_half <= { iword[31], iword[13:5],
|
| 337 |
|
|
((iword[21])? iword[20:19] : 2'h0),
|
| 338 |
|
|
iword[4:0] };
|
| 339 |
|
|
`endif
|
| 340 |
|
|
end
|
| 341 |
|
|
|
| 342 |
|
|
generate
|
| 343 |
|
|
if (EARLY_BRANCHING!=0)
|
| 344 |
|
|
begin
|
| 345 |
|
|
reg r_early_branch, r_ljmp;
|
| 346 |
|
|
reg [(AW-1):0] r_branch_pc;
|
| 347 |
|
|
|
| 348 |
|
|
initial r_ljmp = 1'b0;
|
| 349 |
|
|
always @(posedge i_clk)
|
| 350 |
|
|
if (i_rst)
|
| 351 |
|
|
r_ljmp <= 1'b0;
|
| 352 |
|
|
else if ((i_ce)&&(i_pf_valid))
|
| 353 |
|
|
r_ljmp <= (w_ljmp);
|
| 354 |
|
|
assign o_ljmp = r_ljmp;
|
| 355 |
|
|
|
| 356 |
|
|
always @(posedge i_clk)
|
| 357 |
|
|
if (i_rst)
|
| 358 |
|
|
r_early_branch <= 1'b0;
|
| 359 |
|
|
else if ((i_ce)&&(i_pf_valid))
|
| 360 |
|
|
begin
|
| 361 |
|
|
if (r_ljmp)
|
| 362 |
|
|
// LOD (PC),PC
|
| 363 |
|
|
r_early_branch <= 1'b1;
|
| 364 |
|
|
else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
|
| 365 |
|
|
begin
|
| 366 |
|
|
if (w_op[4:1] == 4'hb) // LDI to PC
|
| 367 |
|
|
// LDI x,PC
|
| 368 |
|
|
r_early_branch <= 1'b1;
|
| 369 |
|
|
else if ((w_op[4:0]==5'h02)&&(~iword[18]))
|
| 370 |
|
|
// Add x,PC
|
| 371 |
|
|
r_early_branch <= 1'b1;
|
| 372 |
|
|
else begin
|
| 373 |
|
|
r_early_branch <= 1'b0;
|
| 374 |
|
|
end
|
| 375 |
|
|
end else
|
| 376 |
|
|
r_early_branch <= 1'b0;
|
| 377 |
|
|
end else if (i_ce)
|
| 378 |
|
|
r_early_branch <= 1'b0;
|
| 379 |
|
|
|
| 380 |
|
|
always @(posedge i_clk)
|
| 381 |
|
|
if (i_ce)
|
| 382 |
|
|
begin
|
| 383 |
|
|
if (r_ljmp)
|
| 384 |
|
|
r_branch_pc <= iword[(AW-1):0];
|
| 385 |
|
|
else if (w_op[4:1] == 4'hb) // LDI
|
| 386 |
|
|
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
|
| 387 |
|
|
else // Add x,PC
|
| 388 |
|
|
r_branch_pc <= i_pc
|
| 389 |
|
|
+ {{(AW-17){iword[17]}},iword[16:0]}
|
| 390 |
|
|
+ {{(AW-1){1'b0}},1'b1};
|
| 391 |
|
|
end
|
| 392 |
|
|
|
| 393 |
|
|
assign o_early_branch = r_early_branch;
|
| 394 |
|
|
assign o_branch_pc = r_branch_pc;
|
| 395 |
|
|
end else begin
|
| 396 |
|
|
assign o_early_branch = 1'b0;
|
| 397 |
|
|
assign o_branch_pc = {(AW){1'b0}};
|
| 398 |
|
|
assign o_ljmp = 1'b0;
|
| 399 |
|
|
end endgenerate
|
| 400 |
|
|
|
| 401 |
|
|
|
| 402 |
|
|
// To be a pipeable operation there must be ...
|
| 403 |
|
|
// 1. Two valid adjacent instructions
|
| 404 |
|
|
// 2. Both must be memory operations, of the same time (both lods
|
| 405 |
|
|
// or both stos)
|
| 406 |
|
|
// 3. Both must use the same register base address
|
| 407 |
|
|
// 4. Both must be to the same address, or the address incremented
|
| 408 |
|
|
// by one
|
| 409 |
|
|
// Note that we're not using iword here ... there's a lot of logic
|
| 410 |
|
|
// taking place, and it's only valid if the new word is not compressed.
|
| 411 |
|
|
//
|
| 412 |
|
|
reg r_valid;
|
| 413 |
|
|
always @(posedge i_clk)
|
| 414 |
|
|
if (i_ce)
|
| 415 |
|
|
o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
|
| 416 |
|
|
&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
|
| 417 |
|
|
&&(i_instruction[17:14] == o_dcdB[3:0])
|
| 418 |
|
|
&&(i_gie == o_gie)
|
| 419 |
|
|
&&((i_instruction[21:19]==o_cond[2:0])
|
| 420 |
|
|
||(o_cond[2:0] == 3'h0))
|
| 421 |
|
|
&&((i_instruction[13:0]==r_I[13:0])
|
| 422 |
|
|
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
|
| 423 |
|
|
always @(posedge i_clk)
|
| 424 |
|
|
if (i_rst)
|
| 425 |
|
|
r_valid <= 1'b0;
|
| 426 |
|
|
else if ((i_ce)&&(o_ljmp))
|
| 427 |
|
|
r_valid <= 1'b0;
|
| 428 |
|
|
else if ((i_ce)&&(i_pf_valid))
|
| 429 |
|
|
r_valid <= 1'b1;
|
| 430 |
|
|
else if (~i_stalled)
|
| 431 |
|
|
r_valid <= 1'b0;
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
|
| 435 |
|
|
|
| 436 |
|
|
endmodule
|
