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[/] [s6soc/] [trunk/] [rtl/] [llqspi.v] - Blame information for rev 47

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    llqspi.v
4
//
5
// Project:     Wishbone Controlled Quad SPI Flash Controller
6
//
7
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
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//              to/from a Quad SPI port.  The port is understood to be 
9
//              a normal SPI port unless the driver requests four bit mode.
10
//              When not in use, unlike our previous SPI work, no bits will
11
//              toggle.
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//
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// Creator:     Dan Gisselquist
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//              Gisselquist Technology, LLC
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//
16
///////////////////////////////////////////////////////////////////////////
17
//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
30
// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
40
`define QSPI_IDLE       3'h0
41
`define QSPI_START      3'h1
42
`define QSPI_BITS       3'h2
43
`define QSPI_READY      3'h3
44
`define QSPI_HOLDING    3'h4
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`define QSPI_STOP       3'h5
46
`define QSPI_STOP_B     3'h6
47
 
48
// Modes
49
`define QSPI_MOD_SPI    2'b00
50
`define QSPI_MOD_QOUT   2'b10
51
`define QSPI_MOD_QIN    2'b11
52
 
53
module  llqspi(i_clk,
54
                // Module interface
55
                i_wr, i_hold, i_word, i_len, i_spd, i_dir,
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                        o_word, o_valid, o_busy,
57
                // QSPI interface
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                o_sck, o_cs_n, o_mod, o_dat, i_dat);
59
        input                   i_clk;
60
        // Chip interface
61
        //      Can send info
62
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
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        //                      i_word = { 1'b0, 32'info to send },
64
        //                      i_len = # of bytes in word-1
65
        input                   i_wr, i_hold;
66
        input           [31:0]   i_word;
67
        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
68
        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
69
        input                   i_dir; // 0 -> read, 1 -> write to SPI
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        output  reg     [31:0]   o_word;
71
        output  reg             o_valid, o_busy;
72
        // Interface with the QSPI lines
73
        output  reg             o_sck;
74
        output  reg             o_cs_n;
75
        output  reg     [1:0]    o_mod;
76
        output  reg     [3:0]    o_dat;
77
        input           [3:0]    i_dat;
78
 
79
        // output       wire    [22:0]  o_dbg;
80
        // assign       o_dbg = { state, spi_len,
81
                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
82
 
83
        // Timing:
84
        //
85
        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
86
        //       0      1       0/0     1        -      
87
        //       1      1       0/1     1        -
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        //       2      1       1/0     0         -      QSPI_START
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        //       3      0        1/0     0         -      QSPI_START
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        //       4      0        1/0     0         0      QSPI_BITS
91
        //       5      1       1/0     0         0      QSPI_BITS
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        //       6      0        1/0     0         1      QSPI_BITS
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        //       7      1       1/0     0         1      QSPI_BITS
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        //       8      0        1/0     0         2      QSPI_BITS
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        //       9      1       1/0     0         2      QSPI_BITS
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        //      10      0        1/0     0         3      QSPI_BITS
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        //      11      1       1/0     0         3      QSPI_BITS
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        //      12      0        1/0     0         4      QSPI_BITS
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        //      13      1       1/0     0         4      QSPI_BITS
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        //      14      0        1/0     0         5      QSPI_BITS
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        //      15      1       1/0     0         5      QSPI_BITS
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        //      16      0        1/0     0         6      QSPI_BITS
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        //      17      1       1/1     0         6      QSPI_BITS
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        //      18      0        1/1     0         7      QSPI_READY
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        //      19      1       0/1     0         7      QSPI_READY
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        //      20      0        1/0/V   0         8      QSPI_BITS
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        //      21      1       1/0     0         8      QSPI_BITS
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        //      22      0        1/0     0         9      QSPI_BITS
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        //      23      1       1/0     0         9      QSPI_BITS
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        //      24      0        1/0     0        10      QSPI_BITS
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        //      25      1       1/0     0        10      QSPI_BITS
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        //      26      0        1/0     0        11      QSPI_BITS
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        //      27      1       1/0     0        11      QSPI_BITS
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        //      28      0        1/0     0        12      QSPI_BITS
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        //      29      1       1/0     0        12      QSPI_BITS
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        //      30      0        1/0     0        13      QSPI_BITS
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        //      31      1       1/0     0        13      QSPI_BITS
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        //      32      0        1/0     0        14      QSPI_BITS
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        //      33      1       1/0     0        14      QSPI_BITS
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        //      34      0        1/0     0        15      QSPI_READY
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        //      35      1       1/0     0        15      QSPI_READY
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        //      36      1       1/0/V   0         -      QSPI_STOP
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        //      37      1       1/0     0         -      QSPI_STOPB
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        //      38      1       1/0     1        -      QSPI_IDLE
125
        //      39      1       0/0     1        -
126
        // Now, let's switch from single bit to quad mode
127
        //      40      1       0/0     1        -      QSPI_IDLE
128
        //      41      1       0/1     1        -      QSPI_IDLE
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        //      42      1       1/0     0         -      QSPI_START
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        //      43      0        1/0     0         -      QSPI_START
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        //      44      0        1/0     0         0      QSPI_BITS
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        //      45      1       1/0     0         0      QSPI_BITS
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        //      46      0        1/0     0         1      QSPI_BITS
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        //      47      1       1/0     0         1      QSPI_BITS
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        //      48      0        1/0     0         2      QSPI_BITS
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        //      49      1       1/0     0         2      QSPI_BITS
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        //      50      0        1/0     0         3      QSPI_BITS
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        //      51      1       1/0     0         3      QSPI_BITS
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        //      52      0        1/0     0         4      QSPI_BITS
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        //      53      1       1/0     0         4      QSPI_BITS
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        //      54      0        1/0     0         5      QSPI_BITS
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        //      55      1       1/0     0         5      QSPI_BITS
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        //      56      0        1/0     0         6      QSPI_BITS
144
        //      57      1       1/1/QR  0         6      QSPI_BITS
145
        //      58      0        1/1/QR  0         7      QSPI_READY
146
        //      59      1       0/1/QR  0         7      QSPI_READY
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        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
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        //      61      1       1/0/?   0         8-11   QSPI_BITS
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        //      62      0        1/0/?   0         12-15  QSPI_BITS
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        //      63      1       1/0/?   0         12-15  QSPI_BITS
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        //      64      1       1/0/?/V 0        -       QSPI_STOP
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        //      65      1       1/0/?   0        -       QSPI_STOPB
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        //      66      1       1/0/?   1       -       QSPI_IDLE
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        //      67      1       0/0     1       -       QSPI_IDLE
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        // Now let's try something entirely in Quad read mode, from the
156
        // beginning
157
        //      68      1       0/1/QR  1       -       QSPI_IDLE
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        //      69      1       1/0     0        -       QSPI_START
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        //      70      0        1/0     0        -       QSPI_START
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        //      71      0        1/0     0        0-3     QSPI_BITS
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        //      72      1       1/0     0        0-3     QSPI_BITS
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        //      73      0        1/1/QR  0        4-7     QSPI_BITS
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        //      74      1       0/1/QR  0        4-7     QSPI_BITS
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        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
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        //      76      1       1/?/?   0        8-11    QSPI_BITS
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        //      77      0        1/1/QR  0        12-15   QSPI_BITS
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        //      78      1       0/1/QR  0        12-15   QSPI_BITS
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        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
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        //      80      1       1/0     0        16-19   QSPI_BITS
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        //      81      0        1/0     0        20-23   QSPI_BITS
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        //      82      1       1/0     0        20-23   QSPI_BITS
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        //      83      1       1/0/V   0        -       QSPI_STOP
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        //      84      1       1/0     0        -       QSPI_STOPB
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        //      85      1       1/0     1       -       QSPI_IDLE
175
        //      86      1       0/0     1       -       QSPI_IDLE
176
 
177
        wire    i_miso;
178
        assign  i_miso = i_dat[1];
179
 
180
        reg             r_spd, r_dir;
181
        reg     [5:0]    spi_len;
182
        reg     [31:0]   r_word;
183
        reg     [30:0]   r_input;
184
        reg     [2:0]    state;
185
        initial state = `QSPI_IDLE;
186
        initial o_sck   = 1'b1;
187
        initial o_cs_n  = 1'b1;
188
        initial o_dat   = 4'hd;
189
        initial o_valid = 1'b0;
190
        initial o_busy  = 1'b0;
191
        initial r_input = 31'h000;
192 46 dgisselq
        initial o_mod   = `QSPI_MOD_SPI;
193 2 dgisselq
        always @(posedge i_clk)
194
                if ((state == `QSPI_IDLE)&&(o_sck))
195
                begin
196
                        o_cs_n <= 1'b1;
197
                        o_valid <= 1'b0;
198
                        o_busy  <= 1'b0;
199
                        o_mod <= `QSPI_MOD_SPI;
200 46 dgisselq
                        r_word <= i_word;
201
                        r_spd <= i_spd;
202
                        r_dir <= i_dir;
203 2 dgisselq
                        if (i_wr)
204
                        begin
205
                                state <= `QSPI_START;
206
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
207
                                o_cs_n <= 1'b0;
208 46 dgisselq
                                // o_sck <= 1'b1;
209 2 dgisselq
                                o_busy <= 1'b1;
210
                        end
211
                end else if (state == `QSPI_START)
212
                begin // We come in here with sck high, stay here 'til sck is low
213
                        o_sck <= 1'b0;
214
                        if (o_sck == 1'b0)
215
                        begin
216
                                state <= `QSPI_BITS;
217
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
218
                                if (r_spd)
219
                                        r_word <= { r_word[27:0], 4'h0 };
220
                                else
221
                                        r_word <= { r_word[30:0], 1'b0 };
222
                        end
223
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
224
                        o_cs_n <= 1'b0;
225
                        o_busy <= 1'b1;
226
                        o_valid <= 1'b0;
227
                        if (r_spd)
228
                                o_dat <= r_word[31:28];
229 46 dgisselq
                        else
230 2 dgisselq
                                o_dat <= { 3'b110, r_word[31] };
231
                end else if (~o_sck)
232
                begin
233
                        o_sck <= 1'b1;
234
                        o_busy <= ((state != `QSPI_READY)||(~i_wr));
235
                        o_valid <= 1'b0;
236
                end else if (state == `QSPI_BITS)
237
                begin
238
                        // Should enter into here with at least a spi_len
239
                        // of one, perhaps more
240
                        o_sck <= 1'b0;
241
                        o_busy <= 1'b1;
242
                        if (r_spd)
243
                        begin
244
                                o_dat <= r_word[31:28];
245
                                r_word <= { r_word[27:0], 4'h0 };
246
                                spi_len <= spi_len - 6'h4;
247
                                if (spi_len == 6'h4)
248
                                        state <= `QSPI_READY;
249
                        end else begin
250
                                o_dat <= { 3'b110, r_word[31] };
251
                                r_word <= { r_word[30:0], 1'b0 };
252
                                spi_len <= spi_len - 6'h1;
253
                                if (spi_len == 6'h1)
254
                                        state <= `QSPI_READY;
255
                        end
256
 
257
                        o_valid <= 1'b0;
258
                        if (~o_mod[1])
259
                                r_input <= { r_input[29:0], i_miso };
260
                        else if (o_mod[1])
261
                                r_input <= { r_input[26:0], i_dat };
262
                end else if (state == `QSPI_READY)
263
                begin
264
                        o_valid <= 1'b0;
265
                        o_cs_n <= 1'b0;
266
                        o_busy <= 1'b1;
267
                        // This is the state on the last clock (both low and
268
                        // high clocks) of the data.  Data is valid during
269
                        // this state.  Here we chose to either STOP or
270
                        // continue and transmit more.
271
                        o_sck <= (i_hold); // No clocks while holding
272 46 dgisselq
                        r_spd <= i_spd;
273
                        r_dir <= i_dir;
274
                        if (i_spd)
275
                        begin
276
                                r_word <= { i_word[27:0], 4'h0 };
277
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h4;
278
                        end else begin
279
                                r_word <= { i_word[30:0], 1'b0 };
280
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h1;
281
                        end
282 2 dgisselq
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
283
                        begin
284
                                state <= `QSPI_BITS;
285
                                o_busy <= 1'b1;
286
                                o_sck <= 1'b0;
287
 
288
                                // Read the new request off the bus
289
                                // Set up the first bits on the bus
290
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
291
                                if (i_spd)
292
                                        o_dat <= i_word[31:28];
293 46 dgisselq
                                else
294 2 dgisselq
                                        o_dat <= { 3'b110, i_word[31] };
295
 
296
                        end else begin
297
                                o_sck <= 1'b1;
298
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
299
                                o_busy <= (~i_hold);
300 46 dgisselq
                        end
301 2 dgisselq
 
302 46 dgisselq
                        // Read a bit upon any transition
303
                        o_valid <= 1'b1;
304
                        if (~o_mod[1])
305
                        begin
306
                                r_input <= { r_input[29:0], i_miso };
307
                                o_word  <= { r_input[30:0], i_miso };
308
                        end else if (o_mod[1])
309
                        begin
310
                                r_input <= { r_input[26:0], i_dat };
311
                                o_word  <= { r_input[27:0], i_dat };
312 2 dgisselq
                        end
313
                end else if (state == `QSPI_HOLDING)
314
                begin
315
                        // We need this state so that the o_valid signal
316
                        // can get strobed with our last result.  Otherwise
317
                        // we could just sit in READY waiting for a new command.
318
                        //
319
                        // Incidentally, the change producing this state was
320
                        // the result of a nasty race condition.  See the
321
                        // commends in wbqspiflash for more details.
322
                        //
323
                        o_valid <= 1'b0;
324
                        o_cs_n <= 1'b0;
325
                        o_busy <= 1'b0;
326 46 dgisselq
                        r_spd <= i_spd;
327
                        r_dir <= i_dir;
328
                        if (i_spd)
329
                        begin
330
                                r_word <= { i_word[27:0], 4'h0 };
331
                                spi_len<= { 1'b0, i_len, 3'b100 };
332
                        end else begin
333
                                r_word <= { i_word[30:0], 1'b0 };
334
                                spi_len<= { 1'b0, i_len, 3'b111 };
335
                        end
336 2 dgisselq
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
337
                        begin
338
                                state  <= `QSPI_BITS;
339
                                o_busy <= 1'b1;
340
                                o_sck  <= 1'b0;
341
 
342
                                // Read the new request off the bus
343
                                // Set up the first bits on the bus
344
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
345
                                if (i_spd)
346
                                        o_dat <= i_word[31:28];
347 46 dgisselq
                                else
348 2 dgisselq
                                        o_dat <= { 3'b110, i_word[31] };
349
                        end else begin
350
                                o_sck <= 1'b1;
351
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
352
                                o_busy <= (~i_hold);
353
                        end
354
                end else if (state == `QSPI_STOP)
355
                begin
356
                        o_sck   <= 1'b1; // Stop the clock
357
                        o_valid <= 1'b0; // Output may have just been valid, but no more
358
                        o_busy  <= 1'b1; // Still busy till port is clear
359
                        state <= `QSPI_STOP_B;
360
                        o_mod <= `QSPI_MOD_SPI;
361
                end else if (state == `QSPI_STOP_B)
362
                begin
363
                        o_cs_n <= 1'b1;
364
                        o_sck <= 1'b1;
365
                        // Do I need this????
366
                        // spi_len <= 3; // Minimum CS high time before next cmd
367
                        state <= `QSPI_IDLE;
368
                        o_valid <= 1'b0;
369
                        o_busy <= 1'b1;
370
                        o_mod <= `QSPI_MOD_SPI;
371
                end else begin // Invalid states, should never get here
372
                        state   <= `QSPI_STOP;
373
                        o_valid <= 1'b0;
374
                        o_busy  <= 1'b1;
375
                        o_cs_n  <= 1'b1;
376
                        o_sck   <= 1'b1;
377
                        o_mod   <= `QSPI_MOD_SPI;
378
                        o_dat   <= 4'hd;
379
                end
380
 
381
endmodule
382
 

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