OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [rxuart.v] - Blame information for rev 31

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    rxuart.v
4
//
5 4 dgisselq
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6 2 dgisselq
//
7
// Purpose:     Receive and decode inputs from a single UART line.
8
//
9
//
10
//      To interface with this module, connect it to your system clock,
11
//      pass it the 32 bit setup register (defined below) and the UART
12
//      input.  When data becomes available, the o_wr line will be asserted
13
//      for one clock cycle.  On parity or frame errors, the o_parity_err
14
//      or o_frame_err lines will be asserted.  Likewise, on a break 
15
//      condition, o_break will be asserted.  These lines are self clearing.
16
//
17
//      There is a synchronous reset line, logic high.
18
//
19
//      Now for the setup register.  The register is 32 bits, so that this
20
//      UART may be set up over a 32-bit bus.
21
//
22
//      i_setup[29:28]  Indicates the number of data bits per word.  This will
23
//      either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
24
//      for a six bit word, or 2'b11 for a five bit word.
25
//
26
//      i_setup[27]     Indicates whether or not to use one or two stop bits.
27
//              Set this to one to expect two stop bits, zero for one.
28
//
29
//      i_setup[26]     Indicates whether or not a parity bit exists.  Set this
30
//              to 1'b1 to include parity.
31
//
32
//      i_setup[25]     Indicates whether or not the parity bit is fixed.  Set
33
//              to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
34
//              parity to be set based upon data.  (Both assume the parity
35
//              enable value is set.)
36
//
37
//      i_setup[24]     This bit is ignored if parity is not used.  Otherwise,
38
//              in the case of a fixed parity bit, this bit indicates whether
39
//              mark (1'b1) or space (1'b0) parity is used.  Likewise if the
40
//              parity is not fixed, a 1'b1 selects even parity, and 1'b0
41
//              selects odd.
42
//
43
//      i_setup[23:0]   Indicates the speed of the UART in terms of clocks.
44
//              So, for example, if you have a 200 MHz clock and wish to
45
//              run your UART at 9600 baud, you would take 200 MHz and divide
46
//              by 9600 to set this value to 24'd20834.  Likewise if you wished
47
//              to run this serial port at 115200 baud from a 200 MHz clock,
48
//              you would set the value to 24'd1736
49
//
50
//      Thus, to set the UART for the common setting of an 8-bit word, 
51
//      one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
52
//      would want to set the setup value to:
53
//
54
//      32'h0006c8              // For 115,200 baud, 8 bit, no parity
55
//      32'h005161              // For 9600 baud, 8 bit, no parity
56
//      
57
//
58
//
59
// Creator:     Dan Gisselquist, Ph.D.
60
//              Gisselquist Technology, LLC
61
//
62 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
63 2 dgisselq
//
64 4 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
65 2 dgisselq
//
66 4 dgisselq
// This program is free software (firmware): you can redistribute it and/or
67
// modify it under the terms of  the GNU General Public License as published
68
// by the Free Software Foundation, either version 3 of the License, or (at
69
// your option) any later version.
70 2 dgisselq
//
71 4 dgisselq
// This program is distributed in the hope that it will be useful, but WITHOUT
72
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
73
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
74
// for more details.
75 2 dgisselq
//
76 4 dgisselq
// You should have received a copy of the GNU General Public License along
77
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
78
// target there if the PDF file isn't present.)  If not, see
79
// <http://www.gnu.org/licenses/> for a copy.
80 2 dgisselq
//
81 4 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
82
//              http://www.gnu.org/licenses/gpl.html
83
//
84
//
85
////////////////////////////////////////////////////////////////////////////////
86
//
87
//
88 2 dgisselq
// States: (@ baud counter == 0)
89
//      0        First bit arrives
90
//      ..7     Bits arrive
91
//      8       Stop bit (x1)
92
//      9       Stop bit (x2)
93
///     c       break condition
94
//      d       Waiting for the channel to go high
95
//      e       Waiting for the reset to complete
96
//      f       Idle state
97
`define RXU_BIT_ZERO            4'h0
98
`define RXU_BIT_ONE             4'h1
99
`define RXU_BIT_TWO             4'h2
100
`define RXU_BIT_THREE           4'h3
101
`define RXU_BIT_FOUR            4'h4
102
`define RXU_BIT_FIVE            4'h5
103
`define RXU_BIT_SIX             4'h6
104
`define RXU_BIT_SEVEN           4'h7
105
`define RXU_PARITY              4'h8
106
`define RXU_STOP                4'h9
107
`define RXU_SECOND_STOP         4'ha
108
// Unused 4'hb
109
// Unused 4'hc
110
`define RXU_BREAK               4'hd
111
`define RXU_RESET_IDLE          4'he
112
`define RXU_IDLE                4'hf
113
 
114
module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
115
                        o_parity_err, o_frame_err, o_ck_uart);
116
        //  parameter // CLOCKS_PER_BAUD = 25'd004340,
117
                        //  BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
118
                        //  CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
119
        // 8 data bits, no parity, (at least 1) stop bit
120
        input                   i_clk, i_reset;
121
        input           [29:0]   i_setup;
122
        input                   i_uart;
123
        output  reg             o_wr;
124
        output  reg     [7:0]    o_data;
125
        output  reg             o_break;
126
        output  reg             o_parity_err, o_frame_err;
127
        output  wire            o_ck_uart;
128
 
129
 
130
        wire    [27:0]   clocks_per_baud, break_condition, half_baud;
131
        wire    [1:0]    data_bits;
132
        wire            use_parity, parity_even, dblstop, fixd_parity;
133
        reg     [29:0]   r_setup;
134
        assign  clocks_per_baud = { 4'h0, r_setup[23:0] };
135
        assign  data_bits   = r_setup[29:28];
136
        assign  dblstop     = r_setup[27];
137
        assign  use_parity  = r_setup[26];
138
        assign  fixd_parity = r_setup[25];
139
        assign  parity_even = r_setup[24];
140
        assign  break_condition = { r_setup[23:0], 4'h0 };
141
        assign  half_baud = { 5'h00, r_setup[23:1] };
142
 
143
        reg     q_uart, qq_uart, ck_uart;
144
        initial q_uart  = 1'b0;
145
        initial qq_uart = 1'b0;
146
        initial ck_uart = 1'b0;
147
        always @(posedge i_clk)
148
        begin
149
                q_uart <= i_uart;
150
                qq_uart <= q_uart;
151
                ck_uart <= qq_uart;
152
        end
153
        assign  o_ck_uart = ck_uart;
154
 
155
        reg     [27:0]   chg_counter;
156
        initial chg_counter = 28'h00;
157
        always @(posedge i_clk)
158
                if (i_reset)
159
                        chg_counter <= 28'h00;
160
                else if (qq_uart != ck_uart)
161
                        chg_counter <= 28'h00;
162
                else if (chg_counter < break_condition)
163
                        chg_counter <= chg_counter + 1;
164
 
165
        always @(posedge i_clk)
166
                o_break <=((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
167
 
168
        reg     [3:0]    state;
169
        reg     [27:0]   baud_counter;
170
        reg     [7:0]    data_reg;
171
        reg             calc_parity;
172
        initial o_wr = 1'b0;
173
        initial state = `RXU_RESET_IDLE;
174
        initial o_parity_err = 1'b0;
175
        initial o_frame_err  = 1'b0;
176
        // initial      baud_counter = clocks_per_baud;
177
        always @(posedge i_clk)
178
        begin
179
                if (i_reset)
180
                begin
181
                        o_wr <= 1'b0;
182
                        o_data <= 8'h00;
183
                        state <= `RXU_RESET_IDLE;
184
                        baud_counter <= clocks_per_baud; // Set, not reset
185
                        data_reg <= 8'h00;
186
                        calc_parity <= 1'b0;
187
                        o_parity_err <= 1'b0;
188
                        o_frame_err <= 1'b0;
189
                end else if (state == `RXU_RESET_IDLE)
190
                begin
191
                        r_setup <= i_setup;
192
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
193
                        baud_counter <= clocks_per_baud-28'h01;// Set, not reset
194
                        if ((ck_uart)&&(chg_counter >= break_condition))
195
                                // Goto idle state from a reset
196
                                state <= `RXU_IDLE;
197
                        else // Otherwise, stay in this condition 'til reset
198
                                state <= `RXU_RESET_IDLE;
199
                        calc_parity <= 1'b0;
200
                        o_parity_err <= 1'b0;
201
                        o_frame_err <= 1'b0;
202
                end else if ((~ck_uart)&&(chg_counter >= break_condition))
203
                begin // We are in a break condition
204
                        state <= `RXU_BREAK;
205
                        o_wr <= 1'b0;
206
                        o_data <= 8'h00;
207
                        baud_counter <= clocks_per_baud-28'h01;// Set, not reset
208
                        data_reg <= 8'h00;
209
                        calc_parity <= 1'b0;
210
                        o_parity_err <= 1'b0;
211
                        o_frame_err <= 1'b0;
212
                        r_setup <= i_setup;
213
                end else if (state == `RXU_BREAK)
214
                begin // Goto idle state following return ck_uart going high
215
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
216
                        baud_counter <= clocks_per_baud - 28'h01;
217
                        if (ck_uart)
218
                                state <= `RXU_IDLE;
219
                        else
220
                                state <= `RXU_BREAK;
221
                        calc_parity <= 1'b0;
222
                        o_parity_err <= 1'b0;
223
                        o_frame_err <= 1'b0;
224
                        r_setup <= i_setup;
225
                end else if (state == `RXU_IDLE)
226
                begin // Idle state, independent of baud counter
227
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
228
                        baud_counter <= clocks_per_baud - 28'h01;
229
                        if ((ck_uart == 1'b0)&&(chg_counter > half_baud))
230
                        begin
231
                                // We are in the center of a valid start bit
232
                                case (data_bits)
233
                                2'b00: state <= `RXU_BIT_ZERO;
234
                                2'b01: state <= `RXU_BIT_ONE;
235
                                2'b10: state <= `RXU_BIT_TWO;
236
                                2'b11: state <= `RXU_BIT_THREE;
237
                                endcase
238
                        end else // Otherwise, just stay here in idle
239
                                state <= `RXU_IDLE;
240
                        calc_parity <= 1'b0;
241
                        o_parity_err <= 1'b0;
242
                        o_frame_err <= 1'b0;
243
                end else if (baud_counter == 0)
244
                begin
245
                        baud_counter <= clocks_per_baud-28'h1;
246
                        if (state < `RXU_BIT_SEVEN)
247
                        begin
248
                                // Data arrives least significant bit first.
249
                                // By the time this is clocked in, it's what
250
                                // you'll have.
251
                                data_reg <= { ck_uart, data_reg[7:1] };
252
                                calc_parity <= calc_parity ^ ck_uart;
253
                                o_data <= 8'h00;
254
                                o_wr <= 1'b0;
255
                                state <= state + 1;
256
                                o_parity_err <= 1'b0;
257
                                o_frame_err <= 1'b0;
258
                        end else if (state == `RXU_BIT_SEVEN)
259
                        begin
260
                                data_reg <= { ck_uart, data_reg[7:1] };
261
                                calc_parity <= calc_parity ^ ck_uart;
262
                                o_data <= 8'h00;
263
                                o_wr <= 1'b0;
264
                                state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
265
                                o_parity_err <= 1'b0;
266
                                o_frame_err <= 1'b0;
267
                        end else if (state == `RXU_PARITY)
268
                        begin
269
                                if (fixd_parity)
270
                                        o_parity_err <= (ck_uart ^ parity_even);
271
                                else
272
                                        o_parity_err <= ((parity_even && (calc_parity != ck_uart))
273
                                                ||((~parity_even)&&(calc_parity==ck_uart)));
274
                                state <= `RXU_STOP;
275
                                o_frame_err <= 1'b0;
276
                        end else if (state == `RXU_STOP)
277
                        begin // Stop (or parity) bit(s)
278
                                case (data_bits)
279
                                2'b00: o_data <= data_reg;
280
                                2'b01: o_data <= { 1'b0, data_reg[7:1] };
281
                                2'b10: o_data <= { 2'b0, data_reg[7:2] };
282
                                2'b11: o_data <= { 3'b0, data_reg[7:3] };
283
                                endcase
284
                                o_wr <= 1'b1; // Pulse the write
285
                                o_frame_err <= (~ck_uart);
286
                                if (~ck_uart)
287
                                        state <= `RXU_RESET_IDLE;
288
                                else if (dblstop)
289
                                        state <= `RXU_SECOND_STOP;
290
                                else
291
                                        state <= `RXU_IDLE;
292
                                // o_parity_err <= 1'b0;
293
                        end else // state must equal RX_SECOND_STOP
294
                        begin
295
                                if (~ck_uart)
296
                                begin
297
                                        o_frame_err <= 1'b1;
298
                                        state <= `RXU_RESET_IDLE;
299
                                end else begin
300
                                        state <= `RXU_IDLE;
301
                                        o_frame_err  <= 1'b0;
302
                                end
303
                                o_parity_err <= 1'b0;
304
                        end
305
                end else begin
306
                        o_wr <= 1'b0;   // data_reg = data_reg
307
                        baud_counter <= baud_counter - 28'd1;
308
                        o_parity_err <= 1'b0;
309
                        o_frame_err  <= 1'b0;
310
                end
311
        end
312
 
313
endmodule
314
 
315
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.