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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: spio.v
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//
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose: To provide a bare minimum level of access to the two on-board
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// buttons, the 4 LED's, and the external 4x4 keypad. This
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// routine does *nothing* to debounce either buttons or keypad. Any such
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// debouncing *must* be done in software. As with the rest of the S6
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// project, the goal is to keep the logic small and simple, and this
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// module is no different.
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//
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// With the USB cord on top, the board facing you, LED[0] is on the left.
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//
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dgisselq |
// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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dgisselq |
module spio(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, o_wb_data,
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o_kp_col, i_kp_row, i_btn, o_led,
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o_kp_int, o_btn_int);
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//
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input i_clk;
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//
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [31:0] i_wb_data;
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output wire [31:0] o_wb_data;
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//
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output reg [3:0] o_kp_col;
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input [3:0] i_kp_row;
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input [1:0] i_btn;
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output reg [3:0] o_led;
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output reg o_kp_int, o_btn_int;
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initial o_kp_col = 4'h0;
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initial o_led = 4'h0;
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always @(posedge i_clk)
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if ((i_wb_stb)&&(i_wb_we))
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begin
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o_kp_col <= ((o_kp_col)&(~i_wb_data[11:8]))
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|((i_wb_data[15:12])&(i_wb_data[11:8]));
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// o_led <= ((o_led)&(~i_wb_data[7:4]))
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// |((i_wb_data[3:0])&(i_wb_data[7:4]));
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o_led[0] <= (i_wb_data[4])?i_wb_data[0]:o_led[0];
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o_led[1] <= (i_wb_data[5])?i_wb_data[1]:o_led[1];
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o_led[2] <= (i_wb_data[6])?i_wb_data[2]:o_led[2];
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o_led[3] <= (i_wb_data[7])?i_wb_data[3]:o_led[3];
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end
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reg [3:0] x_kp_row, r_kp_row;
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reg [1:0] x_btn, r_btn;
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initial x_kp_row = 4'h0;
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initial r_kp_row = 4'b0;
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initial x_btn = 2'b0;
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initial r_btn = 2'b0;
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initial o_kp_int = 1'b0;
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initial o_btn_int = 1'b0;
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always @(posedge i_clk)
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begin
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x_kp_row <= i_kp_row;
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x_btn <= i_btn;
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r_kp_row <= x_kp_row;
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r_btn <= x_btn;
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o_kp_int <= ~(&r_kp_row);
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o_btn_int <= |(r_btn);
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end
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assign o_wb_data = { 16'h00, o_kp_col, r_kp_row, 2'b00, r_btn, o_led };
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endmodule
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