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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbdeppsimple.v
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//
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose: This is a very simple DEPP to Wishbone driver. It cannot handle
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// pipeline reads or writes, it cannot compress anything being
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// transmitted, however it can read/write a 32-bit wishbone bus with a
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// proper software driver.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module wbdeppsimple(i_clk,
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i_astb_n, i_dstb_n, i_write_n,i_depp, o_depp, o_wait,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_int);
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input i_clk;
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// DEPP interface
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input i_astb_n, i_dstb_n, i_write_n;
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input [7:0] i_depp;
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output reg [7:0] o_depp;
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output wire o_wait;
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// Wishbone master interface
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output reg o_wb_cyc, o_wb_stb, o_wb_we;
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output reg [31:0] o_wb_addr, o_wb_data;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input i_int;
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// Synchronize the incoming signals
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reg x_dstb_n, x_astb_n, x_write_n,
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r_dstb_n, r_astb_n, r_write_n,
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l_dstb_n, l_astb_n;
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reg [7:0] x_depp, r_depp;
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initial x_dstb_n = 1'b1;
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initial r_dstb_n = 1'b1;
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initial l_dstb_n = 1'b1;
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initial x_astb_n = 1'b1;
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initial r_astb_n = 1'b1;
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initial l_astb_n = 1'b1;
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always @(posedge i_clk)
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begin
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{ x_dstb_n, x_astb_n, x_write_n, x_depp }
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<= { i_dstb_n, i_astb_n, i_write_n, i_depp };
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{ r_dstb_n, r_astb_n, r_write_n, r_depp }
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<= { x_dstb_n, x_astb_n, x_write_n, x_depp };
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{ l_dstb_n, l_astb_n } <= { r_dstb_n, r_astb_n };
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end
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wire w_wait;
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assign w_wait = ~(&{x_dstb_n, x_astb_n,
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r_dstb_n, r_astb_n,
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l_dstb_n, l_astb_n});
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reg [7:0] addr;
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reg [31:0] r_data;
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wire astb, dstb, w_write;
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assign astb = (~r_astb_n)&&(l_astb_n);
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assign dstb = (~r_dstb_n)&&(l_dstb_n);
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assign w_write= (~r_write_n);
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initial o_wb_cyc = 1'b0;
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initial o_wb_stb = 1'b0;
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initial addr = 8'h00;
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always @(posedge i_clk)
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begin
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if ((w_write)&&(astb))
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addr <= r_depp;
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if ((w_write)&&(dstb)&&(addr[7:3]==5'h00))
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begin
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case(addr[2:0])
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//
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3'b000: o_wb_addr[31:24] <= r_depp;
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3'b001: o_wb_addr[23:16] <= r_depp;
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3'b010: o_wb_addr[15: 8] <= r_depp;
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3'b011: o_wb_addr[ 7: 0] <= r_depp;
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//
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3'b100: o_wb_data[31:24] <= r_depp;
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3'b101: o_wb_data[23:16] <= r_depp;
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3'b110: o_wb_data[15: 8] <= r_depp;
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3'b111: o_wb_data[ 7: 0] <= r_depp;
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//
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endcase
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end
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if ((o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we))
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r_data <= i_wb_data;
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// Direct BUS control
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if ((w_write)&&(dstb)&&(|addr[7:3]))
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begin
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o_wb_cyc <= r_depp[0];
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o_wb_stb <= r_depp[0];
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o_wb_we <= r_depp[1];
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end else begin
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o_wb_stb <= 1'b0;
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if ((o_wb_cyc)&&(i_wb_ack))
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o_wb_cyc <= 1'b0;
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end
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end
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assign o_wait = (w_wait);
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reg r_int, r_err;
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initial r_int = 1'b0;
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initial r_err = 1'b0;
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always @(posedge i_clk)
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begin
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if (addr[4])
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o_depp <= { 5'h0, o_wb_cyc, r_int, r_err };
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else case(addr[2:0])
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3'b000: o_depp <= o_wb_addr[31:24];
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3'b001: o_depp <= o_wb_addr[23:16];
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3'b010: o_depp <= o_wb_addr[15: 8];
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3'b011: o_depp <= o_wb_addr[ 7: 0];
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3'b100: o_depp <= r_data[31:24];
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3'b101: o_depp <= r_data[23:16];
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3'b110: o_depp <= r_data[15: 8];
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3'b111: o_depp <= r_data[ 7: 0];
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endcase
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r_int <= (i_int) ||((r_int)&&((~dstb)||(w_write)||(~addr[4])));
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r_err <= (i_wb_err)||((r_err)&&((~dstb)||(w_write)||(~addr[4])));
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end
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endmodule
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