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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbgpio.v
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//
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose: A General Purpose Input/Output controller. This controller
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// allows a user to read the current state of the 16-GPIO input
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// pins, or to set the state of the 16-GPIO output pins. Specific numbers
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// of pins are configurable from 1-16.
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//
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// Unlike other controllers, this controller offers no capability to
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// change input/output direction, or to implement pull-up or pull-down
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// resistors. It simply changes and adjusts the values going out the
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// output pins, while allowing a user to read the values on the input
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// pins.
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//
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// Any change of an input pin value will result in the generation of an
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// interrupt signal.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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dgisselq |
module wbgpio(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, o_wb_data,
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i_gpio, o_gpio, o_int);
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parameter NIN=16, NOUT=16, DEFAULT=16'h00;
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input i_clk;
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//
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [31:0] i_wb_data;
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output wire [31:0] o_wb_data;
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//
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input [(NIN-1):0] i_gpio;
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output reg [(NOUT-1):0] o_gpio;
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//
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output reg o_int;
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// 9LUT's, 16 FF's
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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o_gpio <= ((o_gpio)&(~i_wb_data[(NOUT+16-1):16]))
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|((i_wb_data[(NOUT-1):0])&(i_wb_data[(NOUT+16-1):16]));
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reg [(NIN-1):0] x_gpio, r_gpio;
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// 3 LUTs, 33 FF's
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always @(posedge i_clk)
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begin
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x_gpio <= i_gpio;
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r_gpio <= x_gpio;
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o_int <= (x_gpio != r_gpio);
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end
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assign o_wb_data = { {(16-NIN){1'b0}}, r_gpio,
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{(16-NOUT){1'b0}}, o_gpio };
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endmodule
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