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[/] [s6soc/] [trunk/] [sw/] [dev/] [board.h] - Blame information for rev 31

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1 12 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    board.h
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//
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// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose:     To define the interfaces to the peripherals on the board, as
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//              given by the ZipCPU's view of the board.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#ifndef BOARD_H
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#define BOARD_H
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// GPIO PINS
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//   first the outputs ...
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#define GPO_SDA         0x000001
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#define GPO_SCL         0x000002
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#define GPO_MOSI        0x000004
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#define GPO_SCK         0x000008
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#define GPO_SS          0x000010
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//   then the inputs.
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#define GPI_SDA         0x010000
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#define GPI_SCL         0x020000
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#define GPI_MISO        0x040000
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#define GPOSETV(PINS)   ((PINS)|((PINS)<<16))
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#define GPOCLRV(PINS)   ((PINS)<<16)
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// Interrupts
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#define INT_ENABLE      0x80000000
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#define INT_BUTTON      0x001
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#define INT_BUSERR      0x002 // Kind of useless, a buserr will kill us anyway
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#define INT_SCOPE       0x004
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#define INT_RTC         0x008 // May not be available, due to lack of space
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#define INT_TIMA        0x010
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#define INT_TIMB        0x020
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#define INT_UARTRX      0x040
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#define INT_UARTTX      0x080
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#define INT_KEYPAD      0x100
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#define INT_AUDIO       0x200
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#define INT_GPIO        0x400
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// #define      INT_FLASH       0x800   // Not available due to lack of space
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#define INT_ENABLEV(IN)         (INT_ENABLE|((IN)<<16))
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#define INT_DISABLEV(IN)        (INT_ENABLE|((IN)<<16))
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#define INT_CLEAR(IN)           (IN)
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// Clocks per second, for use with the timer
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#define TM_ONE_SECOND   80000000
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#define TM_REPEAT       0x80000000
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typedef struct  {
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        volatile int            io_pic;
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        volatile unsigned       *io_buserr;
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        volatile int            io_tima, io_timb;
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        volatile unsigned       io_pwm_audio;
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        volatile unsigned       io_spio; // aka keypad, buttons, and keyboard
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        volatile unsigned       io_gpio;
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        volatile unsigned       io_uart;
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        volatile unsigned       io_version;
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} IOSPACE;
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typedef struct {
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        volatile unsigned       s_control, s_data;
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} SCOPE;
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typedef struct  {
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        volatile unsigned       f_crc, f_far_maj, f_far_min, f_fdri,
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                        f_fdro, f_cmd, f_ctl, f_mask,
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                        f_stat, f_lout, f_cor1, f_cor2,
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                        f_pwrdn, f_flr, f_idcode, f_cwdt,
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                        f_hcopt, f_csbo, f_gen1, f_gen2,
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                        f_gen3, f_gen4, f_gen5, f_mode,
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                        f_gwe, f_mfwr, f_cclk, f_seu, f_exp, f_rdbk,
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                        f_bootsts, f_eye, f_cbc;
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} FPGACONFIG;
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typedef struct  {
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        volatile unsigned       c_clock, c_timer, c_stopwatch, c_alarm;
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} RTCCLOCK;
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#define IOADDR          0x000100
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#define SCOPEADDR       0x000200
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// #define FCTLADDR     0x000300 // Flash control, depends upon write capability
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#define CONFIGADDR      0x000400
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// #define RTCADDR      0x000800 // Disabled for lack of space on device
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#define RAMADDR         0x002000
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#define FLASHADDR       0x400000
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#define RESET_ADDR      0x480000
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#endif

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