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[/] [s6soc/] [trunk/] [sw/] [host/] [regdefs.h] - Blame information for rev 22

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1 8 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    regdefs.h
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//
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// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose:     
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#ifndef REGDEFS_H
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#define REGDEFS_H
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#define R_VERSION       0x00000108
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#define R_ICONTROL      0x00000100
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#define R_BUSERR        0x00000101
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#define R_ITIMERA       0x00000102
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#define R_ITIMERB       0x00000103
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#define R_PWM           0x00000104
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#define R_SPIO          0x00000105
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#define R_GPIO          0x00000106
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#define R_UART          0x00000107
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// WB Scope registers
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#define R_SCOPE         0x00000200
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#define R_SCOPED        0x00000201
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//
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// And because the flash driver needs these constants defined ...
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#define R_QSPI_EREG     0x0000030c
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#define R_QSPI_CREG     0x0000030d
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#define R_QSPI_SREG     0x0000030e
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#define R_QSPI_IDREG    0x0000030f
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//
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// FPGA CONFIG/ICAP REGISTERS
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#define R_CFG_CRC       0x00000400
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#define R_CFG_FAR_MAJ   0x00000401
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#define R_CFG_FAR_MIN   0x00000402
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#define R_CFG_FDRI      0x00000403
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#define R_CFG_FDRO      0x00000404
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#define R_CFG_CMD       0x00000405
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#define R_CFG_CTL       0x00000406
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#define R_CFG_MASK      0x00000407
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#define R_CFG_STAT      0x00000408
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#define R_CFG_LOUT      0x00000409
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#define R_CFG_COR1      0x0000040a
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#define R_CFG_COR2      0x0000040b
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#define R_CFG_PWRDN     0x0000040c
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#define R_CFG_FLR       0x0000040d
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#define R_CFG_IDCODE    0x0000040e
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#define R_CFG_CWDT      0x0000040f
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#define R_CFG_HCOPT     0x00000410
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#define R_CFG_CSBO      0x00000412
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#define R_CFG_GEN1      0x00000413
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#define R_CFG_GEN2      0x00000414
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#define R_CFG_GEN3      0x00000415
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#define R_CFG_GEN4      0x00000416
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#define R_CFG_GEN5      0x00000417
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#define R_CFG_MODE      0x00000418
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#define R_CFG_GWE       0x00000419
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#define R_CFG_GTS       0x0000041a
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#define R_CFG_MFWR      0x0000041b
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#define R_CFG_CCLK      0x0000041c
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#define R_CFG_SEU       0x0000041d
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#define R_CFG_EXP       0x0000041e
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#define R_CFG_RDBK      0x0000041f
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#define R_CFG_BOOTSTS   0x00000420
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#define R_CFG_EYE       0x00000421
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#define R_CFG_CBC       0x00000422
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// RTC clock control
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#define R_CLOCK         0x00000800
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#define R_TIMER         0x00000801
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#define R_STOPWATCH     0x00000802
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#define R_CKALARM       0x00000803
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// RAM memory space
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#define RAMBASE         0x00002000
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#define MEMWORDS        (1<<12)
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#define RAMLEN          MEMWORDS
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// Flash memory space
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#define SPIFLASH        0x00400000
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#define FLASHWORDS      (1<<22)
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#define CONFIG_ADDRESS  0x00400000 // Main Xilinx configuration (ZipCPU)
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#define ALTCONFIG_ADDRESS 0x440000 // Alternate Xilinx configuration (Debug)
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#define RESET_ADDRESS   0x00480000 // ZipCPU Reset address
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// Interrupt control constants
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#define GIE             0x80000000      // Enable all interrupts
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#define SCOPEN          0x80040004      // Enable WBSCOPE interrupts
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#define ISPIF_EN        0x88000800      // Enable SPI Flash interrupts
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#define ISPIF_DIS       0x08000000      // Disable SPI Flash interrupts
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#define ISPIF_CLR       0x08000800      // Clear pending SPI Flash interrupt
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// Flash control constants
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#define ERASEFLAG       0x80000000
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#define DISABLEWP       0x10000000
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// Sectors are defined as 64 kB (16 kW)
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#define SZPAGE          64      // 256 bytes
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#define PGLEN           64      // 256 bytes
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#define NPAGES          256     // 64 kB sectors / 256 bytes is ...
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#define SECTORSZ        (NPAGES * SZPAGE)
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#define NSECTORS        (FLASHWORDS/SECTORSZ)   // 256 sectors
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#define SECTOROF(A)     ((A) & (-1<<14))        // 64 kB ea
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#define PAGEOF(A)       ((A) & (-1<<6))
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// Scop definition/sequences
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#define SCOPE_NO_RESET  0x80000000
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#define SCOPE_TRIGGER   (0x08000000|SCOPE_NO_RESET)
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#define SCOPE_DISABLE   (0x04000000)
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typedef struct {
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        unsigned        m_addr;
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        const char      *m_name;
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} REGNAME;
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extern  const   REGNAME *bregs;
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extern  const   int     NREGS;
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// #define      NREGS   (sizeof(bregs)/sizeof(bregs[0]))
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extern  unsigned        addrdecode(const char *v);
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extern  const   char *addrname(const unsigned v);
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// #include "ttybus.h"
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// #include "portbus.h"
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// #include "deppbus.h"
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// typedef      DEPPBUS FPGA;
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#include "ttybus.h"
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typedef TTYBUS  FPGA;
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#endif

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