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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
;;
;; Filename:    resetdump.s
;;
;; Project:     CMod S6 System on a Chip, ZipCPU demonstration project
;;
;; Purpose:     While most of my ZipCPU programs to date have started with a
;;              simple assembly script to load the stack and call the program
;;      entry point, this is different.  This is a very complicated startup
;;      script designed to dump all of the internal information to the CPU
;;      to a UART output port.  This is on purpose.  Indeed, this may be my
;;      only means of debugging the device once it goes bad:
;;
;;      - To set a breakpoint
;;              at the location desired call kpanic(), the CPU will dump its
;;                      variables and restart.
;;              sometime before the desired clock, set the watchdog timer
;;                      (currently TIMER_B).  When the watchdog expires,
;;                      the CPU will restart.  Adjusting the watchdog will
;;                      adjust how long the CPU waits before restarting, and
;;                      may also adjust what instructions you find going on
;;
;;      - In hardware, you can set the scope.  On boot up, this resetdump
;;              startup will dump the value of the scope to the UART.
;;
;;      Of course, this all depends upon someone listening on the uart.  That's
;;      the purpose of the dumpuart.cpp program in the sw/host directory.
;;      That file will capture the dump so it can be examined later.
;;
;; Creator:     Dan Gisselquist, Ph.D.
;;              Gisselquist Technology, LLC
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
;;
;; Copyright (C) 2015-2017, Gisselquist Technology, LLC
;;
;; This program is free software (firmware): you can redistribute it and/or
;; modify it under the terms of  the GNU General Public License as published
;; by the Free Software Foundation, either version 3 of the License, or (at
;; your option) any later version.
;;
;; This program is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
;; for more details.
;;
;; You should have received a copy of the GNU General Public License along
;; with this program.  (It's in the $(ROOT)/doc directory, run make with no
;; target there if the PDF file isn't present.)  If not, see
;; <http://www.gnu.org/licenses/> for a copy.
;;
;; License:     GPL, v3, as defined and found on www.gnu.org,
;;              http://www.gnu.org/licenses/gpl.html
;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
;;
;;
        .section        .start
        .global         _start
        .type           _start,@function
_start:
; Upon reset, we must output our registers to the UART, lest we reset because
; of a crash
        SW      R0,(DBG)
        JSR     internal_kpanic
        LDI     _top_of_stack,SP
        LDI     kernel_entry,R0
        BRA     _bootloader
 
        .global         kpanic
        .type           kpanic,@function
kpanic:
        SW      R0,(DBG)
        SW      R1,4(DBG)
        SW      R2,8(DBG)
        LDI     panicstr, R1
        JSR     raw_put_string
        LW      4(DBG),R1
        LW      8(DBG),R2
        JSR     internal_kpanic
kpanic_wait_for_button_release:
        LW      (SPIO),R0
        TEST    0x010,R0
        BNZ     kpanic_wait_for_button_release
kpanic_wait_for_button:
        LW      (SPIO),R0
        TEST    0x010,R0
        BZ      kpanic_wait_for_button
        BRA     _start
        HALT
 
internal_kpanic:
        ; The original R0 is stored in (DBG)
        SW      R1,4(DBG)
        SW      R2,8(DBG)
        SW      R0,12(DBG)      ; Our return address
 
        ; R0
        LDI     0,R1
        LW      (DBG),R2
        JSR     uart_put_reg_value
 
        ; R1
        LDI     1,R1
        LW      4(DBG),R2
        JSR     uart_put_reg_value
        ; R2
        LDI     2,R1
        LW      8(DBG),R2
        JSR     uart_put_reg_value
        ; R3
        LDI     3,R1
        MOV     R3,R2
        JSR     uart_put_reg_value
 
        ; R4
        LDI     4,R1
        MOV     R4,R2
        JSR     uart_put_reg_value
 
        ; R5
        LDI     5,R1
        MOV     R5,R2
        JSR     uart_put_reg_value
 
        ; R6
        LDI     6,R1
        MOV     R6,R2
        JSR     uart_put_reg_value
 
        ; R7
        LDI     7,R1
        MOV     R7,R2
        JSR     uart_put_reg_value
 
        ; R8
        LDI     8,R1
        MOV     R8,R2
        JSR     uart_put_reg_value
 
        ; R9
        LDI     9,R1
        MOV     R9,R2
        JSR     uart_put_reg_value
 
        ; R10
        LDI     10,R1
        MOV     R10,R2
        JSR     uart_put_reg_value
 
        ; R11
        LDI     11,R1
        MOV     R11,R2
        JSR     uart_put_reg_value
 
        ; R12
        LDI     12,R1
        MOV     R12,R2
        JSR     uart_put_reg_value
 
        ; SP
        LDI     13,R1
        MOV     R13,R2
        JSR     uart_put_reg_value
 
        ; uR0
        LDI     16,R1
        MOV     uR0,R2
        JSR     uart_put_reg_value
 
        ; uR1
        LDI     17,R1
        MOV     uR1,R2
        JSR     uart_put_reg_value
 
        LDI     18,R1
        MOV     uR2,R2
        JSR     uart_put_reg_value
 
        LDI     19,R1
        MOV     uR3,R2
        JSR     uart_put_reg_value
 
        LDI     20,R1
        MOV     uR4,R2
        JSR     uart_put_reg_value
 
        LDI     21,R1
        MOV     uR5,R2
        JSR     uart_put_reg_value
 
        LDI     22,R1
        MOV     uR6,R2
        JSR     uart_put_reg_value
 
        LDI     23,R1
        MOV     uR7,R2
        JSR     uart_put_reg_value
 
        LDI     24,R1
        MOV     uR8,R2
        JSR     uart_put_reg_value
 
        LDI     25,R1
        MOV     uR9,R2
        JSR     uart_put_reg_value
 
        LDI     26,R1
        MOV     uR10,R2
        JSR     uart_put_reg_value
 
        LDI     27,R1
        MOV     uR11,R2
        JSR     uart_put_reg_value
 
        LDI     28,R1
        MOV     uR12,R2
        JSR     uart_put_reg_value
 
        ; uSP
        LDI     29,R1
        MOV     uSP,R2
        JSR     uart_put_reg_value
 
        ; uCC
        LDI     30,R1
        MOV     uCC,R2
        JSR     uart_put_reg_value
 
        ; uPC
        LDI     31,R1
        MOV     uPC,R2
        JSR     uart_put_reg_value
 
;stack_mem_dump:
;       LDI     0,R4
;       LDI     _top_of_stack,R5
;stack_mem_dump_loop:
;       MOV     R4,R1
;       LW      (R5),R2
;       JSR     uart_put_stack_value
;       ADD     4,R4
;       SUB     4,R5
;       CMP     256,R4
;       BLT     stack_mem_dump_loop
 
; Get prepared for a proper start by setting our stack register
        LDI     _top_of_stack,SP
 
        BRA     dump_scope
        ; BRA   end_internal_panic
 
; Now, do a full dump of all memory--all registers are available to us
dump_memory:
        LDI     RAM,R5
        LDI     0x0fff,R6
        LDI     0x0f8,R7
        SW      R7,(SPIO)
full_mem_dump_loop:
        MOV     R5,R1
        LW      (R5),R2
        JSR     uart_dump_mem_value
        LDI     0x0f2,R7
        SW      R7,(SPIO)
 
        ADD     4,R5
        SUB     1,R6
        BGE     full_mem_dump_loop
 
        LDI     0x0f5,R7
        SW      R7,(SPIO)
 
dump_scope:
; Finally, do a full dump of the scope--if it had triggered
;   First, dump the scope control word
        LDI     SCOPE,R7        ; R7 = Debugging scope address
        MOV     R7,R1
        LW      (R7),R2
        MOV     R2,R5           ; R5 will not be changed by a subroutine
        JSR     uart_dump_mem_value
;   Then test whether or not the scope has stopped
        LDI     0x40000000,R1
        TEST    R1,R5
;   If not, start our kernel.
        BZ      dump_buserr
;   Otherwise, calculate the size of the scope
        LSR     20,R5
        AND     0x1f,R5
        LDI     1,R6
        LSL     R5,R6   ; R6 is now the size (number of words) of the scope
        SUB     1,R6    ; Now it is one less than the size,2 support the BGE l8r
;   And start dumping
        ADD     4,R7    ; Get the scope data address
dump_scope_loop:
        MOV     R7,R1
        LW      (R7),R2
        JSR     uart_dump_mem_value
        SUB     1,R6
        BGE     dump_scope_loop
 
dump_buserr:
; Dump a bus error address, if used
        LDI     buserr_header, R1
        JSR     raw_put_string
        LDI     BUSERR,R1
        LW      (R1),R2
        JSR     uart_dump_mem_value
 
end_internal_panic:
        LDI     doublenewline,R1
        JSR     raw_put_string
        LDI     0x0ff,R7
        SW      R7,(SPIO)
        LW      12(DBG),PC
        JMP     R0
 
; R0 is return address
; R1 is register ID
; R2 is register value to output
uart_put_reg_value:
        SW      R0,16(DBG)
        SW      R2,20(DBG)
        SW      R3,24(DBG)
        MOV     R1,R2
        LDI     'u',R1
        CMP     16,R2
        LDILO.LT 's',R1
        SUB.GE  16,R2
        JSR     raw_put_uart
        LDI     '0',R1
        CMP     10,R2
        LDILO.GE '1',R1
        SUB.GE  10,R2
        JSR     raw_put_uart
        MOV     R2,R1
        AND     15,R1
        JSR     get_hex
        JSR     raw_put_uart
        LDI     ':',R1
        JSR     raw_put_uart
        LW      20(DBG),R2
        LDI     8,R3
uart_put_loop:
        MOV     R2,R1
        LSR     28,R1
        LSL     4,R2
        JSR     get_hex
        JSR     raw_put_uart
        SUB     1,R3
        BNZ     uart_put_loop
        LDI     newline, R1
        JSR     raw_put_string
        LW      16(DBG),R0
        LW      20(DBG),R2
        LW      24(DBG),R3
        JMP     R0
 
uart_dump_mem_value:
;       R0 = return address
;       R1 = Memory address
;       R2 = Memory Value
; Local: R3 = working value
        SW      R0,28(DBG)
        MOV     R1,R3           ; R3 = Memory address
        MOV     R2,R4           ; R4 = Memory Value
        LDI     memopenstr,R1
        JSR     raw_put_string
        ; Set up a loop to dump things
        LSL     16,R3           ; Ignore the first 16 bits
        LDI     4,R2            ; We're going to do four hex digits here
        ;
uart_put_mem_address_loop:
        MOV     R3,R1
        LSR     28,R1
        LSL     4,R3
        JSR     get_hex
        JSR     raw_put_uart
        SUB     1,R2
        BNZ     uart_put_mem_address_loop
        ; Put some transition characters
        LDI     memmidstr,R1
        JSR     raw_put_string
 
        ; Set up a loop to dump the memory value now
        LDI     8,R2
uart_put_mem_value_loop:
        MOV     R4,R1
        LSR     28,R1
        LSL     4,R4
        JSR     get_hex
        JSR     raw_put_uart
        SUB     1,R2
        BNZ     uart_put_mem_value_loop
        ; Clear the line
        LDI     newline,R1
        JSR     raw_put_string
        ; And return from our subroutine
        LW      28(DBG),R0
        JMP     R0
 
get_hex:
        ADD     0x30,R1
        CMP     0x3a,R1
        ADD.GE  7,R1    ; Add 'A'-'0'-10
        JMP     R0
 
; R0 is the return address
; R1 is the string address
raw_put_string:
        SW      R0,36(DBG)
        SW      R2,40(DBG)
        MOV     R1,R2
raw_put_string_next:
        LB      (R2),R1
        CMP     0,R1
        LW.Z    36(DBG),R0
        LW.Z    40(DBG),R2
        RTN.Z
        ADD     1,R2
        MOV     raw_put_string_next(PC),R0
        BRA     raw_put_uart
 
; R0 is return address,
; R1 is value to transmit
raw_put_uart:
        SW      R2,32(DBG)
        LDI     INT_UARTTX,R2
        SW      R2,(PIC)        ; Clear the PIC, turn off interrupts, etc.
raw_put_uart_retest:
        LW      (PIC),R2
        TEST    INT_UARTTX,R2
        BZ      raw_put_uart_retest
        SW      R1,(UART)
        LW      32(DBG),R2
        JMP     R0
 
        .section        .fixdata
DBG:
.int    0,0,0,0,0,0,0,0,0,0
 
.set    INT_UARTRX, 0x040
.set    INT_UARTTX, 0x080
.set    PIC,     0x0400
.set    BUSERR,  0x0404
.set    TMRA,    0x0408
.set    TMRB,    0x040c
.set    PWM,     0x0410
.set    SPIO,    0x0414
.set    GPIO,    0x0418
.set    UART,    0x041c
.set    VERSION, 0x0420
.set    SCOPE,   0x0800
.set    SCOPED,  0x0804
.set    RAM,     0x8000
        .section        .rodata
doublenewline:
        .ascii  "\r\n"
newline:
        .asciz  "\r\n"
buserr_header:
        .string "BusErr: "
panicstr:
        .string "Panic: \r\n"
memopenstr:
        .string "M[0x"
memmidstr:
        .string "]; "
 

Line No.	Rev	Author	Line
1	22	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//`
2			`;;`
3			`;; Filename: resetdump.s`
4			`;;`
5			`;; Project: CMod S6 System on a Chip, ZipCPU demonstration project`
6			`;;`
7			`;; Purpose: While most of my ZipCPU programs to date have started with a`
8			`;; simple assembly script to load the stack and call the program`
9			`;; entry point, this is different. This is a very complicated startup`
10			`;; script designed to dump all of the internal information to the CPU`
11			`;; to a UART output port. This is on purpose. Indeed, this may be my`
12			`;; only means of debugging the device once it goes bad:`
13			`;;`
14			`;; - To set a breakpoint`
15			`;; at the location desired call kpanic(), the CPU will dump its`
16			`;; variables and restart.`
17			`;; sometime before the desired clock, set the watchdog timer`
18			`;; (currently TIMER_B). When the watchdog expires,`
19			`;; the CPU will restart. Adjusting the watchdog will`
20			`;; adjust how long the CPU waits before restarting, and`
21			`;; may also adjust what instructions you find going on`
22			`;;`
23			`;; - In hardware, you can set the scope. On boot up, this resetdump`
24			`;; startup will dump the value of the scope to the UART.`
25			`;;`
26			`;; Of course, this all depends upon someone listening on the uart. That's`
27			`;; the purpose of the dumpuart.cpp program in the sw/host directory.`
28			`;; That file will capture the dump so it can be examined later.`
29			`;;`
30			`;; Creator: Dan Gisselquist, Ph.D.`
31			`;; Gisselquist Technology, LLC`
32			`;;`
33			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//`
34			`;;`
35	45	dgisselq	`;; Copyright (C) 2015-2017, Gisselquist Technology, LLC`
36	22	dgisselq	`;;`
37			`;; This program is free software (firmware): you can redistribute it and/or`
38			`;; modify it under the terms of the GNU General Public License as published`
39			`;; by the Free Software Foundation, either version 3 of the License, or (at`
40			`;; your option) any later version.`
41			`;;`
42			`;; This program is distributed in the hope that it will be useful, but WITHOUT`
43			`;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
44			`;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
45			`;; for more details.`
46			`;;`
47			`;; You should have received a copy of the GNU General Public License along`
48			`;; with this program. (It's in the $(ROOT)/doc directory, run make with no`
49			`;; target there if the PDF file isn't present.) If not, see`
50			`;; <http://www.gnu.org/licenses/> for a copy.`
51			`;;`
52			`;; License: GPL, v3, as defined and found on www.gnu.org,`
53			`;; http://www.gnu.org/licenses/gpl.html`
54			`;;`
55			`;;`
56			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//`
57			`;;`
58			`;;`
59			`.section .start`
60			`.global _start`
61			`.type _start,@function`
62			`_start:`
63			`; Upon reset, we must output our registers to the UART, lest we reset because`
64			`; of a crash`
65	45	dgisselq	`SW R0,(DBG)`
66			`JSR internal_kpanic`
67	22	dgisselq	`LDI _top_of_stack,SP`
68	27	dgisselq	`LDI kernel_entry,R0`
69	45	dgisselq	`BRA _bootloader`
70	22	dgisselq
71			`.global kpanic`
72			`.type kpanic,@function`
73			`kpanic:`
74	45	dgisselq	`SW R0,(DBG)`
75			`SW R1,4(DBG)`
76			`SW R2,8(DBG)`
77			`LDI panicstr, R1`
78			`JSR raw_put_string`
79			`LW 4(DBG),R1`
80			`LW 8(DBG),R2`
81			`JSR internal_kpanic`
82	27	dgisselq	`kpanic_wait_for_button_release:`
83	45	dgisselq	`LW (SPIO),R0`
84	27	dgisselq	`TEST 0x010,R0`
85			`BNZ kpanic_wait_for_button_release`
86			`kpanic_wait_for_button:`
87	45	dgisselq	`LW (SPIO),R0`
88	27	dgisselq	`TEST 0x010,R0`
89			`BZ kpanic_wait_for_button`
90			`BRA _start`
91	22	dgisselq	`HALT`
92
93			`internal_kpanic:`
94	45	dgisselq	`; The original R0 is stored in (DBG)`
95			`SW R1,4(DBG)`
96			`SW R2,8(DBG)`
97			`SW R0,12(DBG) ; Our return address`
98	22	dgisselq
99			`; R0`
100			`LDI 0,R1`
101	45	dgisselq	`LW (DBG),R2`
102			`JSR uart_put_reg_value`
103	22	dgisselq
104			`; R1`
105			`LDI 1,R1`
106	45	dgisselq	`LW 4(DBG),R2`
107			`JSR uart_put_reg_value`
108	22	dgisselq	`; R2`
109			`LDI 2,R1`
110	45	dgisselq	`LW 8(DBG),R2`
111			`JSR uart_put_reg_value`
112	22	dgisselq	`; R3`
113			`LDI 3,R1`
114			`MOV R3,R2`
115	45	dgisselq	`JSR uart_put_reg_value`
116	22	dgisselq
117			`; R4`
118			`LDI 4,R1`
119			`MOV R4,R2`
120	45	dgisselq	`JSR uart_put_reg_value`
121	22	dgisselq
122			`; R5`
123			`LDI 5,R1`
124			`MOV R5,R2`
125	45	dgisselq	`JSR uart_put_reg_value`
126	22	dgisselq
127			`; R6`
128			`LDI 6,R1`
129			`MOV R6,R2`
130	45	dgisselq	`JSR uart_put_reg_value`
131	22	dgisselq
132			`; R7`
133			`LDI 7,R1`
134			`MOV R7,R2`
135	45	dgisselq	`JSR uart_put_reg_value`
136	22	dgisselq
137			`; R8`
138			`LDI 8,R1`
139			`MOV R8,R2`
140	45	dgisselq	`JSR uart_put_reg_value`
141	22	dgisselq
142			`; R9`
143			`LDI 9,R1`
144			`MOV R9,R2`
145	45	dgisselq	`JSR uart_put_reg_value`
146	22	dgisselq
147			`; R10`
148			`LDI 10,R1`
149			`MOV R10,R2`
150	45	dgisselq	`JSR uart_put_reg_value`
151	22	dgisselq
152			`; R11`
153			`LDI 11,R1`
154			`MOV R11,R2`
155	45	dgisselq	`JSR uart_put_reg_value`
156	22	dgisselq
157			`; R12`
158			`LDI 12,R1`
159			`MOV R12,R2`
160	45	dgisselq	`JSR uart_put_reg_value`
161	22	dgisselq
162			`; SP`
163			`LDI 13,R1`
164			`MOV R13,R2`
165	45	dgisselq	`JSR uart_put_reg_value`
166	22	dgisselq
167			`; uR0`
168			`LDI 16,R1`
169			`MOV uR0,R2`
170	45	dgisselq	`JSR uart_put_reg_value`
171	22	dgisselq
172			`; uR1`
173			`LDI 17,R1`
174			`MOV uR1,R2`
175	45	dgisselq	`JSR uart_put_reg_value`
176	22	dgisselq
177			`LDI 18,R1`
178			`MOV uR2,R2`
179	45	dgisselq	`JSR uart_put_reg_value`
180	22	dgisselq
181			`LDI 19,R1`
182			`MOV uR3,R2`
183	45	dgisselq	`JSR uart_put_reg_value`
184	22	dgisselq
185			`LDI 20,R1`
186			`MOV uR4,R2`
187	45	dgisselq	`JSR uart_put_reg_value`
188	22	dgisselq
189			`LDI 21,R1`
190			`MOV uR5,R2`
191	45	dgisselq	`JSR uart_put_reg_value`
192	22	dgisselq
193			`LDI 22,R1`
194			`MOV uR6,R2`
195	45	dgisselq	`JSR uart_put_reg_value`
196	22	dgisselq
197			`LDI 23,R1`
198			`MOV uR7,R2`
199	45	dgisselq	`JSR uart_put_reg_value`
200	22	dgisselq
201			`LDI 24,R1`
202			`MOV uR8,R2`
203	45	dgisselq	`JSR uart_put_reg_value`
204	22	dgisselq
205			`LDI 25,R1`
206			`MOV uR9,R2`
207	45	dgisselq	`JSR uart_put_reg_value`
208	22	dgisselq
209			`LDI 26,R1`
210			`MOV uR10,R2`
211	45	dgisselq	`JSR uart_put_reg_value`
212	22	dgisselq
213			`LDI 27,R1`
214			`MOV uR11,R2`
215	45	dgisselq	`JSR uart_put_reg_value`
216	22	dgisselq
217			`LDI 28,R1`
218			`MOV uR12,R2`
219	45	dgisselq	`JSR uart_put_reg_value`
220	22	dgisselq
221			`; uSP`
222			`LDI 29,R1`
223			`MOV uSP,R2`
224	45	dgisselq	`JSR uart_put_reg_value`
225	22	dgisselq
226			`; uCC`
227			`LDI 30,R1`
228			`MOV uCC,R2`
229	45	dgisselq	`JSR uart_put_reg_value`
230	22	dgisselq
231			`; uPC`
232			`LDI 31,R1`
233			`MOV uPC,R2`
234	45	dgisselq	`JSR uart_put_reg_value`
235	22	dgisselq
236			`;stack_mem_dump:`
237	45	dgisselq	`; LDI 0,R4`
238			`; LDI _top_of_stack,R5`
239	22	dgisselq	`;stack_mem_dump_loop:`
240	45	dgisselq	`; MOV R4,R1`
241			`; LW (R5),R2`
242			`; JSR uart_put_stack_value`
243			`; ADD 4,R4`
244			`; SUB 4,R5`
245			`; CMP 256,R4`
246			`; BLT stack_mem_dump_loop`
247	22	dgisselq
248			`; Get prepared for a proper start by setting our stack register`
249			`LDI _top_of_stack,SP`
250
251			`BRA dump_scope`
252			`; BRA end_internal_panic`
253
254			`; Now, do a full dump of all memory--all registers are available to us`
255			`dump_memory:`
256			`LDI RAM,R5`
257	45	dgisselq	`LDI 0x0fff,R6`
258	22	dgisselq	`LDI 0x0f8,R7`
259	45	dgisselq	`SW R7,(SPIO)`
260	22	dgisselq	`full_mem_dump_loop:`
261			`MOV R5,R1`
262	45	dgisselq	`LW (R5),R2`
263			`JSR uart_dump_mem_value`
264	22	dgisselq	`LDI 0x0f2,R7`
265	45	dgisselq	`SW R7,(SPIO)`
266	22	dgisselq
267	45	dgisselq	`ADD 4,R5`
268	22	dgisselq	`SUB 1,R6`
269	45	dgisselq	`BGE full_mem_dump_loop`
270	22	dgisselq
271			`LDI 0x0f5,R7`
272	45	dgisselq	`SW R7,(SPIO)`
273	22	dgisselq
274			`dump_scope:`
275			`; Finally, do a full dump of the scope--if it had triggered`
276			`; First, dump the scope control word`
277			`LDI SCOPE,R7 ; R7 = Debugging scope address`
278			`MOV R7,R1`
279	45	dgisselq	`LW (R7),R2`
280	22	dgisselq	`MOV R2,R5 ; R5 will not be changed by a subroutine`
281	45	dgisselq	`JSR uart_dump_mem_value`
282	22	dgisselq	`; Then test whether or not the scope has stopped`
283			`LDI 0x40000000,R1`
284			`TEST R1,R5`
285			`; If not, start our kernel.`
286			`BZ dump_buserr`
287			`; Otherwise, calculate the size of the scope`
288			`LSR 20,R5`
289			`AND 0x1f,R5`
290			`LDI 1,R6`
291	45	dgisselq	`LSL R5,R6 ; R6 is now the size (number of words) of the scope`
292			`SUB 1,R6 ; Now it is one less than the size,2 support the BGE l8r`
293	22	dgisselq	`; And start dumping`
294	45	dgisselq	`ADD 4,R7 ; Get the scope data address`
295	22	dgisselq	`dump_scope_loop:`
296			`MOV R7,R1`
297	45	dgisselq	`LW (R7),R2`
298			`JSR uart_dump_mem_value`
299	22	dgisselq	`SUB 1,R6`
300	45	dgisselq	`BGE dump_scope_loop`
301	22	dgisselq
302			`dump_buserr:`
303			`; Dump a bus error address, if used`
304	45	dgisselq	`LDI buserr_header, R1`
305			`JSR raw_put_string`
306	22	dgisselq	`LDI BUSERR,R1`
307	45	dgisselq	`LW (R1),R2`
308			`JSR uart_dump_mem_value`
309	22	dgisselq
310			`end_internal_panic:`
311	45	dgisselq	`LDI doublenewline,R1`
312			`JSR raw_put_string`
313	22	dgisselq	`LDI 0x0ff,R7`
314	45	dgisselq	`SW R7,(SPIO)`
315			`LW 12(DBG),PC`
316	22	dgisselq	`JMP R0`
317
318			`; R0 is return address`
319			`; R1 is register ID`
320	45	dgisselq	`; R2 is register value to output`
321	22	dgisselq	`uart_put_reg_value:`
322	45	dgisselq	`SW R0,16(DBG)`
323			`SW R2,20(DBG)`
324			`SW R3,24(DBG)`
325	22	dgisselq	`MOV R1,R2`
326			`LDI 'u',R1`
327			`CMP 16,R2`
328			`LDILO.LT 's',R1`
329			`SUB.GE 16,R2`
330	45	dgisselq	`JSR raw_put_uart`
331	22	dgisselq	`LDI '0',R1`
332			`CMP 10,R2`
333			`LDILO.GE '1',R1`
334			`SUB.GE 10,R2`
335	45	dgisselq	`JSR raw_put_uart`
336	22	dgisselq	`MOV R2,R1`
337			`AND 15,R1`
338	45	dgisselq	`JSR get_hex`
339			`JSR raw_put_uart`
340			`LDI ':',R1`
341			`JSR raw_put_uart`
342			`LW 20(DBG),R2`
343	22	dgisselq	`LDI 8,R3`
344			`uart_put_loop:`
345			`MOV R2,R1`
346	45	dgisselq	`LSR 28,R1`
347			`LSL 4,R2`
348			`JSR get_hex`
349			`JSR raw_put_uart`
350	22	dgisselq	`SUB 1,R3`
351			`BNZ uart_put_loop`
352	45	dgisselq	`LDI newline, R1`
353			`JSR raw_put_string`
354			`LW 16(DBG),R0`
355			`LW 20(DBG),R2`
356			`LW 24(DBG),R3`
357	22	dgisselq	`JMP R0`
358
359			`uart_dump_mem_value:`
360			`; R0 = return address`
361			`; R1 = Memory address`
362			`; R2 = Memory Value`
363			`; Local: R3 = working value`
364	45	dgisselq	`SW R0,28(DBG)`
365	22	dgisselq	`MOV R1,R3 ; R3 = Memory address`
366			`MOV R2,R4 ; R4 = Memory Value`
367	45	dgisselq	`LDI memopenstr,R1`
368			`JSR raw_put_string`
369	22	dgisselq	`; Set up a loop to dump things`
370	45	dgisselq	`LSL 16,R3 ; Ignore the first 16 bits`
371	22	dgisselq	`LDI 4,R2 ; We're going to do four hex digits here`
372			`;`
373			`uart_put_mem_address_loop:`
374			`MOV R3,R1`
375	45	dgisselq	`LSR 28,R1`
376			`LSL 4,R3`
377			`JSR get_hex`
378			`JSR raw_put_uart`
379	22	dgisselq	`SUB 1,R2`
380			`BNZ uart_put_mem_address_loop`
381			`; Put some transition characters`
382	45	dgisselq	`LDI memmidstr,R1`
383			`JSR raw_put_string`
384	22	dgisselq
385			`; Set up a loop to dump the memory value now`
386			`LDI 8,R2`
387			`uart_put_mem_value_loop:`
388			`MOV R4,R1`
389	45	dgisselq	`LSR 28,R1`
390			`LSL 4,R4`
391			`JSR get_hex`
392			`JSR raw_put_uart`
393	22	dgisselq	`SUB 1,R2`
394			`BNZ uart_put_mem_value_loop`
395			`; Clear the line`
396	45	dgisselq	`LDI newline,R1`
397			`JSR raw_put_string`
398	22	dgisselq	`; And return from our subroutine`
399	45	dgisselq	`LW 28(DBG),R0`
400	22	dgisselq	`JMP R0`
401
402			`get_hex:`
403			`ADD 0x30,R1`
404	45	dgisselq	`CMP 0x3a,R1`
405			`ADD.GE 7,R1 ; Add 'A'-'0'-10`
406	22	dgisselq	`JMP R0`
407
408	45	dgisselq	`; R0 is the return address`
409			`; R1 is the string address`
410			`raw_put_string:`
411			`SW R0,36(DBG)`
412			`SW R2,40(DBG)`
413			`MOV R1,R2`
414			`raw_put_string_next:`
415			`LB (R2),R1`
416			`CMP 0,R1`
417			`LW.Z 36(DBG),R0`
418			`LW.Z 40(DBG),R2`
419			`RTN.Z`
420			`ADD 1,R2`
421			`MOV raw_put_string_next(PC),R0`
422			`BRA raw_put_uart`
423
424			`; R0 is return address,`
425			`; R1 is value to transmit`
426			`raw_put_uart:`
427			`SW R2,32(DBG)`
428	22	dgisselq	`LDI INT_UARTTX,R2`
429	45	dgisselq	`SW R2,(PIC) ; Clear the PIC, turn off interrupts, etc.`
430	22	dgisselq	`raw_put_uart_retest:`
431	45	dgisselq	`LW (PIC),R2`
432	22	dgisselq	`TEST INT_UARTTX,R2`
433			`BZ raw_put_uart_retest`
434	45	dgisselq	`SW R1,(UART)`
435			`LW 32(DBG),R2`
436	22	dgisselq	`JMP R0`
437
438			`.section .fixdata`
439			`DBG:`
440	45	dgisselq	`.int 0,0,0,0,0,0,0,0,0,0`
441	22	dgisselq
442			`.set INT_UARTRX, 0x040`
443			`.set INT_UARTTX, 0x080`
444	45	dgisselq	`.set PIC, 0x0400`
445			`.set BUSERR, 0x0404`
446			`.set TMRA, 0x0408`
447			`.set TMRB, 0x040c`
448			`.set PWM, 0x0410`
449			`.set SPIO, 0x0414`
450			`.set GPIO, 0x0418`
451			`.set UART, 0x041c`
452			`.set VERSION, 0x0420`
453			`.set SCOPE, 0x0800`
454			`.set SCOPED, 0x0804`
455			`.set RAM, 0x8000`
456			`.section .rodata`
457			`doublenewline:`
458			`.ascii "\r\n"`
459			`newline:`
460			`.asciz "\r\n"`
461			`buserr_header:`
462			`.string "BusErr: "`
463			`panicstr:`
464			`.string "Panic: \r\n"`
465			`memopenstr:`
466			`.string "M[0x"`
467			`memmidstr:`
468			`.string "]; "`
469

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