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jamieiles |
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see .
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module VGARegisters(input logic clk,
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input logic reset,
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// Bus
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input logic cs,
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input logic [19:1] data_m_addr,
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input logic [15:0] data_m_data_in,
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output logic [15:0] data_m_data_out,
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input logic [1:0] data_m_bytesel,
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input logic data_m_wr_en,
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input logic data_m_access,
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output logic data_m_ack,
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// VGA
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input logic vga_vsync,
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input logic vga_hsync,
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output logic cursor_enabled,
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output logic [14:0] cursor_pos,
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output logic [2:0] cursor_scan_start,
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output logic [2:0] cursor_scan_end);
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wire reg_access = cs & data_m_access;
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wire sel_index = reg_access & data_m_addr[3:1] == 3'b010 & data_m_bytesel[0];
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wire sel_value = reg_access & data_m_addr[3:1] == 3'b010 & data_m_bytesel[1];
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wire sel_mode = reg_access & data_m_addr[3:1] == 3'b011 & data_m_bytesel[0];
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wire sel_color = reg_access & data_m_addr[3:1] == 3'b011 & data_m_bytesel[1];
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wire sel_status = reg_access & data_m_addr[3:1] == 3'b101 & data_m_bytesel[0];
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reg [3:0] active_index;
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wire [3:0] index = data_m_wr_en & sel_index ? data_m_data_in[3:0] : active_index;
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wire [7:0] index_value;
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reg [1:0] cursor_mode;
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wire [7:0] status = {7'b0, (~vga_vsync | ~vga_hsync)};
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assign cursor_enabled = cursor_mode != 2'b01;
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always_ff @(posedge clk) begin
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if (data_m_wr_en & sel_value) begin
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case (index)
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4'ha: {cursor_mode, cursor_scan_start} <=
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{data_m_data_in[13:12], data_m_data_in[10:8]};
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4'hb: cursor_scan_end <= data_m_data_in[10:8];
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4'he: cursor_pos[14:8] <= data_m_data_in[14:8];
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4'hf: cursor_pos[7:0] <= data_m_data_in[15:8];
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default: ;
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endcase
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end
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end
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always_ff @(posedge clk)
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if (sel_index & data_m_wr_en)
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active_index <= data_m_data_in[3:0];
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always_comb begin
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case (index)
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4'ha: index_value = {2'b0, cursor_mode, 1'b0, cursor_scan_start};
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4'hb: index_value = {5'b0, cursor_scan_start};
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4'he: index_value = {2'b0, cursor_pos[13:8]};
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4'hf: index_value = cursor_pos[7:0];
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default: index_value = 8'b0;
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endcase
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end
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always_ff @(posedge clk) begin
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data_m_data_out <= 16'b0;
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if (!data_m_wr_en) begin
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if (sel_index)
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data_m_data_out[7:0] <= {4'b0, active_index};
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if (sel_mode)
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data_m_data_out[7:0] <= 8'b0;
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if (sel_status)
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data_m_data_out[7:0] <= status;
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if (sel_value)
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data_m_data_out[15:8] <= index_value;
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if (sel_color)
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data_m_data_out[15:8] <= 8'b0;
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end
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end
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always_ff @(posedge clk)
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data_m_ack <= data_m_access && cs;
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endmodule
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