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[/] [s80186/] [trunk/] [fpga/] [common/] [Top.sv] - Blame information for rev 2

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// Copyright Jamie Iles, 2017
//
// This file is part of s80x86.
//
// s80x86 is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// s80x86 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with s80x86.  If not, see .
 
module Top(input logic clk,
           input logic rst_in_n,
           output logic s_ras_n,
           output logic s_cas_n,
           output logic s_wr_en,
           output logic [1:0] s_bytesel,
           output logic [12:0] s_addr,
           output logic s_cs_n,
           output logic s_clken,
           inout [15:0] s_data,
           output logic [1:0] s_banksel,
           output logic sdr_clk,
           output logic [`CONFIG_NUM_LEDS-1:0] leds,
`ifdef CONFIG_VGA
           output logic vga_hsync,
           output logic vga_vsync,
           output logic [3:0] vga_r,
           output logic [3:0] vga_g,
           output logic [3:0] vga_b,
`endif // CONFIG_VGA
`ifdef CONFIG_PS2
           inout ps2_clk,
           inout ps2_dat,
`endif // CONFIG_PS2
           input logic uart_rx,
           output logic uart_tx,
           output logic spi_sclk,
           output logic spi_mosi,
           input logic spi_miso,
           output logic spi_ncs);
 
reg poweron_reset = 1'b1;
wire sys_clk;
wire reset_n;
wire reset = ~reset_n | debug_reset | poweron_reset;
 
`ifdef CONFIG_VGA
wire vga_clk;
 
wire vga_reg_access;
wire vga_reg_ack;
wire [15:0] vga_reg_data;
 
wire vga_access;
wire vga_ack;
wire [15:0] vga_data;
`endif
 
wire [1:0] ir;
wire tdo;
wire tck;
wire tdi;
wire sdr;
wire cdr;
wire udr;
wire debug_stopped;
wire debug_seize;
wire debug_reset;
wire debug_run;
wire [7:0] debug_addr;
wire [15:0] debug_wr_val;
wire [15:0] debug_val;
wire debug_wr_en;
 
wire [15:0] io_data = sdram_config_data |
    uart_data |
    spi_data |
    timer_data |
    irq_control_data |
    pic_data |
`ifdef CONFIG_VGA
    vga_reg_data |
`endif // CONFIG_VGA
`ifdef CONFIG_PS2
    ps2_data |
`endif // CONFIG_PS2
    bios_control_data;
wire [15:0] mem_data;
 
// Data bus
wire [19:1] data_m_addr;
wire [15:0] data_m_data_in = d_io ? io_data : mem_data;
wire [15:0] data_m_data_out;
wire data_m_access;
wire data_m_ack = data_mem_ack | io_ack;
wire data_m_wr_en;
wire [1:0] data_m_bytesel;
 
// Instruction bus
wire [19:1] instr_m_addr;
wire [15:0] instr_m_data_in;
wire instr_m_access;
wire instr_m_ack;
 
// Multiplexed I/D bus.
wire [19:1] q_m_addr;
wire [15:0] q_m_data_out;
wire [15:0] q_m_data_in = sdram_data |
`ifdef CONFIG_VGA
    vga_data |
`endif // CONFIG_VGA
    bios_data;
wire q_m_ack = sdram_ack |
`ifdef CONFIG_VGA
    vga_ack |
`endif // CONFIG_VGA
    bios_ack;
wire q_m_access;
wire q_m_wr_en;
wire [1:0] q_m_bytesel;
 
wire d_io;
 
wire sdram_access;
wire sdram_ack;
wire [15:0] sdram_data;
 
wire leds_access;
wire leds_ack;
 
wire bios_access;
wire bios_ack;
wire [15:0] bios_data;
 
wire bios_control_access;
wire bios_control_ack;
wire bios_enabled;
wire [15:0] bios_control_data;
 
wire sdram_config_access;
wire sdram_config_ack;
wire sdram_config_done;
wire [15:0] sdram_config_data;
 
`ifdef CONFIG_PS2
wire ps2_access;
wire ps2_ack;
wire [15:0] ps2_data;
wire ps2_intr;
`else
wire ps2_intr = 1'b0;
`endif // CONFIG_PS2
 
wire uart_access;
wire uart_ack;
wire [15:0] uart_data;
 
wire spi_access;
wire spi_ack;
wire [15:0] spi_data;
 
wire nmi;
wire [6:0] intr_test;
wire intr;
wire inta;
wire [7:0] irq;
wire irq_control_access;
wire irq_control_ack;
wire [15:0] irq_control_data;
wire pic_access;
wire pic_ack;
wire [15:0] pic_data;
 
wire [7:0] irqs = {6'b0, ps2_intr, timer_intr} | {1'b0, intr_test};
 
// Timer
wire pit_clk;
wire timer_intr;
wire timer_access;
wire timer_ack;
wire [15:0] timer_data;
 
wire default_io_access;
wire default_io_ack;
 
wire io_ack = sdram_config_ack |
              default_io_ack |
              uart_ack |
              leds_ack |
              spi_ack |
              irq_control_ack |
              pic_ack |
              timer_ack |
`ifdef CONFIG_VGA
              vga_reg_ack |
`endif // CONFIG_VGA
`ifdef CONFIG_PS2
              ps2_ack |
`endif // CONFIG_PS2
              bios_control_ack;
 
always_ff @(posedge clk)
    default_io_ack <= default_io_access;
 
always_comb begin
    leds_access = 1'b0;
    sdram_config_access = 1'b0;
    default_io_access = 1'b0;
    uart_access = 1'b0;
    spi_access = 1'b0;
    irq_control_access = 1'b0;
    pic_access = 1'b0;
    timer_access = 1'b0;
    bios_control_access = 1'b0;
`ifdef CONFIG_VGA
    vga_reg_access = 1'b0;
`endif // CONFIG_VGA
`ifdef CONFIG_PS2
    ps2_access = 1'b0;
`endif // CONFIG_PS2
 
    if (d_io && data_m_access) begin
        casez ({data_m_addr[15:1], 1'b0})
        16'b1111_1111_1111_1110: leds_access = 1'b1;
        16'b1111_1111_1111_1100: sdram_config_access = 1'b1;
        16'b1111_1111_1111_1010: uart_access = 1'b1;
        16'b1111_1111_1111_00z0: spi_access = 1'b1;
        16'b1111_1111_1111_0110: irq_control_access = 1'b1;
        16'b1111_1111_1110_1100: bios_control_access = 1'b1;
        16'b0000_0000_0100_00z0: timer_access = 1'b1;
        16'b0000_0000_0010_0000: pic_access = 1'b1;
`ifdef CONFIG_VGA
        16'b0000_0011_1101_zzzz: vga_reg_access = 1'b1;
`endif // CONFIG_VGA
`ifdef CONFIG_PS2
        16'b0000_0000_0110_0000: ps2_access = 1'b1;
`endif // CONFIG_PS2
        default:  default_io_access = 1'b1;
        endcase
    end
end
 
always_comb begin
    sdram_access = 1'b0;
    bios_access = 1'b0;
`ifdef CONFIG_VGA
    vga_access = 1'b0;
`endif // CONFIG_VGA
 
    if (q_m_access) begin
        casez ({bios_enabled, q_m_addr, 1'b0})
        {1'b1, 20'b1111_11??_????_????_????}: bios_access = 1'b1;
`ifdef CONFIG_VGA
        {1'b?, 20'b1011_1000_????_????_????}: vga_access = 1'b1;
`endif // CONFIG_VGA
        default: sdram_access = 1'b1;
        endcase
    end
end
 
wire data_mem_ack;
 
BitSync         ResetSync(.clk(sys_clk),
                          .d(rst_in_n),
                          .q(reset_n));
 
// verilator lint_off PINMISSING
VirtualJTAG VirtualJTAG(.ir_out(),
                        .tdo(tdo),
                        .ir_in(ir),
                        .tck(tck),
                        .tdi(tdi),
                        .virtual_state_sdr(sdr),
                        .virtual_state_e1dr(),
                        .virtual_state_cdr(cdr),
                        .virtual_state_udr(udr));
 
// verilator lint_on PINMISSING
JTAGBridge      JTAGBridge(.cpu_clk(sys_clk),
                           .*);
 
MemArbiter MemArbiter(.clk(sys_clk),
                      .data_m_data_in(mem_data),
                      .data_m_access(data_m_access & ~d_io),
                      .data_m_ack(data_mem_ack),
                      .*);
 
SDRAMController #(.size(`CONFIG_SDRAM_SIZE),
                  .clkf(50000000))
                SDRAMController(.clk(sys_clk),
                                .reset(reset),
                                .data_m_access(q_m_access),
                                .cs(sdram_access),
                                .h_addr({6'b0, q_m_addr}),
                                .h_wdata(q_m_data_out),
                                .h_rdata(sdram_data),
                                .h_wr_en(q_m_wr_en),
                                .h_bytesel(q_m_bytesel),
                                .h_compl(sdram_ack),
                                .h_config_done(sdram_config_done),
                                .*);
 
BIOS #(.depth(8192))
     BIOS(.clk(sys_clk),
          .cs(bios_access),
          .data_m_access(q_m_access),
          .data_m_ack(bios_ack),
          .data_m_addr(q_m_addr),
          .data_m_data_out(bios_data),
          .data_m_bytesel(q_m_bytesel));
 
BIOSControlRegister BIOSControlRegister(.clk(sys_clk),
                                        .cs(bios_control_access),
                                        .data_m_ack(bios_control_ack),
                                        .data_m_data_out(bios_control_data),
                                        .bios_enabled(bios_enabled),
                                        .*);
 
SDRAMConfigRegister SDRAMConfigRegister(.clk(sys_clk),
                                        .cs(sdram_config_access),
                                        .data_m_ack(sdram_config_ack),
                                        .data_m_data_out(sdram_config_data),
                                        .config_done(sdram_config_done),
                                        .*);
 
LEDSRegister     LEDSRegister(.clk(sys_clk),
                              .cs(leds_access),
                              .leds_val(leds),
                              .data_m_data_in(data_m_data_out),
                              .data_m_ack(leds_ack),
                              .*);
 
UartPorts #(.clk_freq(50000000))
          UartPorts(.clk(sys_clk),
                    .rx(uart_rx),
                    .tx(uart_tx),
                    .cs(uart_access),
                    .data_m_ack(uart_ack),
                    .data_m_data_out(uart_data),
                    .data_m_data_in(data_m_data_out),
                    .*);
 
SPIPorts SPIPorts(.clk(sys_clk),
                  .cs(spi_access),
                  .data_m_ack(spi_ack),
                  .data_m_data_out(spi_data),
                  .data_m_data_in(data_m_data_out),
                  .data_m_addr(data_m_addr[1]),
                  .miso(spi_miso),
                  .mosi(spi_mosi),
                  .sclk(spi_sclk),
                  .ncs(spi_ncs),
                  .*);
 
`ifndef verilator
SysPLL  SysPLL(.refclk(clk),
               .rst(1'b0),
               .locked(),
               .*);
`endif // verilator
 
Core Core(.clk(sys_clk),
          .lock(),
          .*);
 
IRQController IRQController(.clk(sys_clk),
                            .cs(irq_control_access),
                            .data_m_ack(irq_control_ack),
                            .data_m_data_out(irq_control_data),
                            .data_m_data_in(data_m_data_out),
                            .*);
 
PIC PIC(.clk(sys_clk),
        .cs(pic_access),
        .data_m_ack(pic_ack),
        .data_m_data_out(pic_data),
        .data_m_data_in(data_m_data_out),
        .intr_in(irqs),
        .*);
 
Timer Timer(.clk(sys_clk),
            .pit_clk(pit_clk),
            .cs(timer_access),
            .data_m_ack(timer_ack),
            .data_m_data_out(timer_data),
            .data_m_data_in(data_m_data_out),
            .data_m_addr(data_m_addr[1]),
            .intr(timer_intr),
            .*);
 
`ifdef CONFIG_VGA
wire cursor_enabled;
wire [14:0] cursor_pos;
wire [2:0] cursor_scan_start;
wire [2:0] cursor_scan_end;
 
VGAController VGAController(.clk(vga_clk),
                            .cs(vga_access),
                            .data_m_access(q_m_access),
                            .data_m_ack(vga_ack),
                            .data_m_addr(q_m_addr),
                            .data_m_data_out(vga_data),
                            .data_m_data_in(q_m_data_out),
                            .data_m_bytesel(q_m_bytesel),
                            .*);
 
VGARegisters VGARegisters(.clk(sys_clk),
                          .cs(vga_reg_access),
                          .data_m_ack(vga_reg_ack),
                          .data_m_data_out(vga_reg_data),
                          .data_m_data_in(data_m_data_out),
                          .*);
`endif
 
`ifdef CONFIG_PS2
PS2Controller #(.clkf(50000000))
              PS2Controller(.clk(sys_clk),
                            .cs(ps2_access),
                            .data_m_ack(ps2_ack),
                            .data_m_data_out(ps2_data),
                            .data_m_data_in(data_m_data_out),
                            .*);
`endif
 
always_ff @(posedge clk)
    poweron_reset <= 1'b0;
 
endmodule

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Subversion Repositories s80186

[/] [s80186/] [trunk/] [fpga/] [common/] [Top.sv] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jamieiles	`// Copyright Jamie Iles, 2017`
2			`//`
3			`// This file is part of s80x86.`
4			`//`
5			`// s80x86 is free software: you can redistribute it and/or modify`
6			`// it under the terms of the GNU General Public License as published by`
7			`// the Free Software Foundation, either version 3 of the License, or`
8			`// (at your option) any later version.`
9			`//`
10			`// s80x86 is distributed in the hope that it will be useful,`
11			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`// GNU General Public License for more details.`
14			`//`
15			`// You should have received a copy of the GNU General Public License`
16			`// along with s80x86. If not, see .`
17
18			`module Top(input logic clk,`
19			`input logic rst_in_n,`
20			`output logic s_ras_n,`
21			`output logic s_cas_n,`
22			`output logic s_wr_en,`
23			`output logic [1:0] s_bytesel,`
24			`output logic [12:0] s_addr,`
25			`output logic s_cs_n,`
26			`output logic s_clken,`
27			`inout [15:0] s_data,`
28			`output logic [1:0] s_banksel,`
29			`output logic sdr_clk,`
30			output logic [`CONFIG_NUM_LEDS-1:0] leds,
31			`ifdef CONFIG_VGA
32			`output logic vga_hsync,`
33			`output logic vga_vsync,`
34			`output logic [3:0] vga_r,`
35			`output logic [3:0] vga_g,`
36			`output logic [3:0] vga_b,`
37			`endif // CONFIG_VGA
38			`ifdef CONFIG_PS2
39			`inout ps2_clk,`
40			`inout ps2_dat,`
41			`endif // CONFIG_PS2
42			`input logic uart_rx,`
43			`output logic uart_tx,`
44			`output logic spi_sclk,`
45			`output logic spi_mosi,`
46			`input logic spi_miso,`
47			`output logic spi_ncs);`
48
49			`reg poweron_reset = 1'b1;`
50			`wire sys_clk;`
51			`wire reset_n;`
52			`wire reset = ~reset_n \| debug_reset \| poweron_reset;`
53
54			`ifdef CONFIG_VGA
55			`wire vga_clk;`
56
57			`wire vga_reg_access;`
58			`wire vga_reg_ack;`
59			`wire [15:0] vga_reg_data;`
60
61			`wire vga_access;`
62			`wire vga_ack;`
63			`wire [15:0] vga_data;`
64			`endif
65
66			`wire [1:0] ir;`
67			`wire tdo;`
68			`wire tck;`
69			`wire tdi;`
70			`wire sdr;`
71			`wire cdr;`
72			`wire udr;`
73			`wire debug_stopped;`
74			`wire debug_seize;`
75			`wire debug_reset;`
76			`wire debug_run;`
77			`wire [7:0] debug_addr;`
78			`wire [15:0] debug_wr_val;`
79			`wire [15:0] debug_val;`
80			`wire debug_wr_en;`
81
82			`wire [15:0] io_data = sdram_config_data \|`
83			`uart_data \|`
84			`spi_data \|`
85			`timer_data \|`
86			`irq_control_data \|`
87			`pic_data \|`
88			`ifdef CONFIG_VGA
89			`vga_reg_data \|`
90			`endif // CONFIG_VGA
91			`ifdef CONFIG_PS2
92			`ps2_data \|`
93			`endif // CONFIG_PS2
94			`bios_control_data;`
95			`wire [15:0] mem_data;`
96
97			`// Data bus`
98			`wire [19:1] data_m_addr;`
99			`wire [15:0] data_m_data_in = d_io ? io_data : mem_data;`
100			`wire [15:0] data_m_data_out;`
101			`wire data_m_access;`
102			`wire data_m_ack = data_mem_ack \| io_ack;`
103			`wire data_m_wr_en;`
104			`wire [1:0] data_m_bytesel;`
105
106			`// Instruction bus`
107			`wire [19:1] instr_m_addr;`
108			`wire [15:0] instr_m_data_in;`
109			`wire instr_m_access;`
110			`wire instr_m_ack;`
111
112			`// Multiplexed I/D bus.`
113			`wire [19:1] q_m_addr;`
114			`wire [15:0] q_m_data_out;`
115			`wire [15:0] q_m_data_in = sdram_data \|`
116			`ifdef CONFIG_VGA
117			`vga_data \|`
118			`endif // CONFIG_VGA
119			`bios_data;`
120			`wire q_m_ack = sdram_ack \|`
121			`ifdef CONFIG_VGA
122			`vga_ack \|`
123			`endif // CONFIG_VGA
124			`bios_ack;`
125			`wire q_m_access;`
126			`wire q_m_wr_en;`
127			`wire [1:0] q_m_bytesel;`
128
129			`wire d_io;`
130
131			`wire sdram_access;`
132			`wire sdram_ack;`
133			`wire [15:0] sdram_data;`
134
135			`wire leds_access;`
136			`wire leds_ack;`
137
138			`wire bios_access;`
139			`wire bios_ack;`
140			`wire [15:0] bios_data;`
141
142			`wire bios_control_access;`
143			`wire bios_control_ack;`
144			`wire bios_enabled;`
145			`wire [15:0] bios_control_data;`
146
147			`wire sdram_config_access;`
148			`wire sdram_config_ack;`
149			`wire sdram_config_done;`
150			`wire [15:0] sdram_config_data;`
151
152			`ifdef CONFIG_PS2
153			`wire ps2_access;`
154			`wire ps2_ack;`
155			`wire [15:0] ps2_data;`
156			`wire ps2_intr;`
157			`else
158			`wire ps2_intr = 1'b0;`
159			`endif // CONFIG_PS2
160
161			`wire uart_access;`
162			`wire uart_ack;`
163			`wire [15:0] uart_data;`
164
165			`wire spi_access;`
166			`wire spi_ack;`
167			`wire [15:0] spi_data;`
168
169			`wire nmi;`
170			`wire [6:0] intr_test;`
171			`wire intr;`
172			`wire inta;`
173			`wire [7:0] irq;`
174			`wire irq_control_access;`
175			`wire irq_control_ack;`
176			`wire [15:0] irq_control_data;`
177			`wire pic_access;`
178			`wire pic_ack;`
179			`wire [15:0] pic_data;`
180
181			`wire [7:0] irqs = {6'b0, ps2_intr, timer_intr} \| {1'b0, intr_test};`
182
183			`// Timer`
184			`wire pit_clk;`
185			`wire timer_intr;`
186			`wire timer_access;`
187			`wire timer_ack;`
188			`wire [15:0] timer_data;`
189
190			`wire default_io_access;`
191			`wire default_io_ack;`
192
193			`wire io_ack = sdram_config_ack \|`
194			`default_io_ack \|`
195			`uart_ack \|`
196			`leds_ack \|`
197			`spi_ack \|`
198			`irq_control_ack \|`
199			`pic_ack \|`
200			`timer_ack \|`
201			`ifdef CONFIG_VGA
202			`vga_reg_ack \|`
203			`endif // CONFIG_VGA
204			`ifdef CONFIG_PS2
205			`ps2_ack \|`
206			`endif // CONFIG_PS2
207			`bios_control_ack;`
208
209			`always_ff @(posedge clk)`
210			`default_io_ack <= default_io_access;`
211
212			`always_comb begin`
213			`leds_access = 1'b0;`
214			`sdram_config_access = 1'b0;`
215			`default_io_access = 1'b0;`
216			`uart_access = 1'b0;`
217			`spi_access = 1'b0;`
218			`irq_control_access = 1'b0;`
219			`pic_access = 1'b0;`
220			`timer_access = 1'b0;`
221			`bios_control_access = 1'b0;`
222			`ifdef CONFIG_VGA
223			`vga_reg_access = 1'b0;`
224			`endif // CONFIG_VGA
225			`ifdef CONFIG_PS2
226			`ps2_access = 1'b0;`
227			`endif // CONFIG_PS2
228
229			`if (d_io && data_m_access) begin`
230			`casez ({data_m_addr[15:1], 1'b0})`
231			`16'b1111_1111_1111_1110: leds_access = 1'b1;`
232			`16'b1111_1111_1111_1100: sdram_config_access = 1'b1;`
233			`16'b1111_1111_1111_1010: uart_access = 1'b1;`
234			`16'b1111_1111_1111_00z0: spi_access = 1'b1;`
235			`16'b1111_1111_1111_0110: irq_control_access = 1'b1;`
236			`16'b1111_1111_1110_1100: bios_control_access = 1'b1;`
237			`16'b0000_0000_0100_00z0: timer_access = 1'b1;`
238			`16'b0000_0000_0010_0000: pic_access = 1'b1;`
239			`ifdef CONFIG_VGA
240			`16'b0000_0011_1101_zzzz: vga_reg_access = 1'b1;`
241			`endif // CONFIG_VGA
242			`ifdef CONFIG_PS2
243			`16'b0000_0000_0110_0000: ps2_access = 1'b1;`
244			`endif // CONFIG_PS2
245			`default: default_io_access = 1'b1;`
246			`endcase`
247			`end`
248			`end`
249
250			`always_comb begin`
251			`sdram_access = 1'b0;`
252			`bios_access = 1'b0;`
253			`ifdef CONFIG_VGA
254			`vga_access = 1'b0;`
255			`endif // CONFIG_VGA
256
257			`if (q_m_access) begin`
258			`casez ({bios_enabled, q_m_addr, 1'b0})`
259			`{1'b1, 20'b1111_11??_????_????_????}: bios_access = 1'b1;`
260			`ifdef CONFIG_VGA
261			`{1'b?, 20'b1011_1000_????_????_????}: vga_access = 1'b1;`
262			`endif // CONFIG_VGA
263			`default: sdram_access = 1'b1;`
264			`endcase`
265			`end`
266			`end`
267
268			`wire data_mem_ack;`
269
270			`BitSync ResetSync(.clk(sys_clk),`
271			`.d(rst_in_n),`
272			`.q(reset_n));`
273
274			`// verilator lint_off PINMISSING`
275			`VirtualJTAG VirtualJTAG(.ir_out(),`
276			`.tdo(tdo),`
277			`.ir_in(ir),`
278			`.tck(tck),`
279			`.tdi(tdi),`
280			`.virtual_state_sdr(sdr),`
281			`.virtual_state_e1dr(),`
282			`.virtual_state_cdr(cdr),`
283			`.virtual_state_udr(udr));`
284
285			`// verilator lint_on PINMISSING`
286			`JTAGBridge JTAGBridge(.cpu_clk(sys_clk),`
287			`.*);`
288
289			`MemArbiter MemArbiter(.clk(sys_clk),`
290			`.data_m_data_in(mem_data),`
291			`.data_m_access(data_m_access & ~d_io),`
292			`.data_m_ack(data_mem_ack),`
293			`.*);`
294
295			SDRAMController #(.size(`CONFIG_SDRAM_SIZE),
296			`.clkf(50000000))`
297			`SDRAMController(.clk(sys_clk),`
298			`.reset(reset),`
299			`.data_m_access(q_m_access),`
300			`.cs(sdram_access),`
301			`.h_addr({6'b0, q_m_addr}),`
302			`.h_wdata(q_m_data_out),`
303			`.h_rdata(sdram_data),`
304			`.h_wr_en(q_m_wr_en),`
305			`.h_bytesel(q_m_bytesel),`
306			`.h_compl(sdram_ack),`
307			`.h_config_done(sdram_config_done),`
308			`.*);`
309
310			`BIOS #(.depth(8192))`
311			`BIOS(.clk(sys_clk),`
312			`.cs(bios_access),`
313			`.data_m_access(q_m_access),`
314			`.data_m_ack(bios_ack),`
315			`.data_m_addr(q_m_addr),`
316			`.data_m_data_out(bios_data),`
317			`.data_m_bytesel(q_m_bytesel));`
318
319			`BIOSControlRegister BIOSControlRegister(.clk(sys_clk),`
320			`.cs(bios_control_access),`
321			`.data_m_ack(bios_control_ack),`
322			`.data_m_data_out(bios_control_data),`
323			`.bios_enabled(bios_enabled),`
324			`.*);`
325
326			`SDRAMConfigRegister SDRAMConfigRegister(.clk(sys_clk),`
327			`.cs(sdram_config_access),`
328			`.data_m_ack(sdram_config_ack),`
329			`.data_m_data_out(sdram_config_data),`
330			`.config_done(sdram_config_done),`
331			`.*);`
332
333			`LEDSRegister LEDSRegister(.clk(sys_clk),`
334			`.cs(leds_access),`
335			`.leds_val(leds),`
336			`.data_m_data_in(data_m_data_out),`
337			`.data_m_ack(leds_ack),`
338			`.*);`
339
340			`UartPorts #(.clk_freq(50000000))`
341			`UartPorts(.clk(sys_clk),`
342			`.rx(uart_rx),`
343			`.tx(uart_tx),`
344			`.cs(uart_access),`
345			`.data_m_ack(uart_ack),`
346			`.data_m_data_out(uart_data),`
347			`.data_m_data_in(data_m_data_out),`
348			`.*);`
349
350			`SPIPorts SPIPorts(.clk(sys_clk),`
351			`.cs(spi_access),`
352			`.data_m_ack(spi_ack),`
353			`.data_m_data_out(spi_data),`
354			`.data_m_data_in(data_m_data_out),`
355			`.data_m_addr(data_m_addr[1]),`
356			`.miso(spi_miso),`
357			`.mosi(spi_mosi),`
358			`.sclk(spi_sclk),`
359			`.ncs(spi_ncs),`
360			`.*);`
361
362			`ifndef verilator
363			`SysPLL SysPLL(.refclk(clk),`
364			`.rst(1'b0),`
365			`.locked(),`
366			`.*);`
367			`endif // verilator
368
369			`Core Core(.clk(sys_clk),`
370			`.lock(),`
371			`.*);`
372
373			`IRQController IRQController(.clk(sys_clk),`
374			`.cs(irq_control_access),`
375			`.data_m_ack(irq_control_ack),`
376			`.data_m_data_out(irq_control_data),`
377			`.data_m_data_in(data_m_data_out),`
378			`.*);`
379
380			`PIC PIC(.clk(sys_clk),`
381			`.cs(pic_access),`
382			`.data_m_ack(pic_ack),`
383			`.data_m_data_out(pic_data),`
384			`.data_m_data_in(data_m_data_out),`
385			`.intr_in(irqs),`
386			`.*);`
387
388			`Timer Timer(.clk(sys_clk),`
389			`.pit_clk(pit_clk),`
390			`.cs(timer_access),`
391			`.data_m_ack(timer_ack),`
392			`.data_m_data_out(timer_data),`
393			`.data_m_data_in(data_m_data_out),`
394			`.data_m_addr(data_m_addr[1]),`
395			`.intr(timer_intr),`
396			`.*);`
397
398			`ifdef CONFIG_VGA
399			`wire cursor_enabled;`
400			`wire [14:0] cursor_pos;`
401			`wire [2:0] cursor_scan_start;`
402			`wire [2:0] cursor_scan_end;`
403
404			`VGAController VGAController(.clk(vga_clk),`
405			`.cs(vga_access),`
406			`.data_m_access(q_m_access),`
407			`.data_m_ack(vga_ack),`
408			`.data_m_addr(q_m_addr),`
409			`.data_m_data_out(vga_data),`
410			`.data_m_data_in(q_m_data_out),`
411			`.data_m_bytesel(q_m_bytesel),`
412			`.*);`
413
414			`VGARegisters VGARegisters(.clk(sys_clk),`
415			`.cs(vga_reg_access),`
416			`.data_m_ack(vga_reg_ack),`
417			`.data_m_data_out(vga_reg_data),`
418			`.data_m_data_in(data_m_data_out),`
419			`.*);`
420			`endif
421
422			`ifdef CONFIG_PS2
423			`PS2Controller #(.clkf(50000000))`
424			`PS2Controller(.clk(sys_clk),`
425			`.cs(ps2_access),`
426			`.data_m_ack(ps2_ack),`
427			`.data_m_data_out(ps2_data),`
428			`.data_m_data_in(data_m_data_out),`
429			`.*);`
430			`endif
431
432			`always_ff @(posedge clk)`
433			`poweron_reset <= 1'b0;`
434
435			`endmodule`