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jamieiles |
# Copyright Jamie Iles, 2017
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#
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# This file is part of s80x86.
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#
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# s80x86 is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# s80x86 is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with s80x86. If not, see .
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# JTAG
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set_input_delay -clock { altera_reserved_tck } 20 [get_ports altera_reserved_tdi]
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set_input_delay -clock { altera_reserved_tck } 20 [get_ports altera_reserved_tms]
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set_output_delay -clock { altera_reserved_tck } 20 [get_ports altera_reserved_tdo]
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set_false_path -from [get_clocks {altera_reserved_tck}] -to [get_clocks {altera_reserved_tck}]
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create_clock -period 20.000 -name clk clk
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derive_pll_clocks
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set sys_clk "SysPLL|altpll_component|auto_generated|pll1|clk[0]"
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set sdram_pll "SysPLL|altpll_component|auto_generated|pll1|clk[1]"
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# SPI clock
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create_generated_clock -name {spi_clk} \
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-source [get_pins {SysPLL|altpll_component|auto_generated|pll1|clk[0]}] \
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-divide_by 2 -master_clock {SysPLL|altpll_component|auto_generated|pll1|clk[0]} \
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[get_registers {SPIPorts:SPIPorts|SPIMaster:SPIMaster|sclk}]
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derive_clock_uncertainty
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# SDRAM
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set sdram_tsu 1.5
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set sdram_th 0.8
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set sdram_tco_min 2.7
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set sdram_tco_max 6.4
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# FPGA timing constraints
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set sdram_input_delay_min $sdram_tco_min
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set sdram_input_delay_max $sdram_tco_max
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set sdram_output_delay_min -$sdram_th
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set sdram_output_delay_max $sdram_tsu
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set_false_path -to [get_ports {sdr_clk}]
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# FPGA Outputs
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set sdram_outputs [get_ports {
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s_clken
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s_ras_n
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s_cas_n
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s_wr_en
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s_bytesel[*]
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s_addr[*]
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s_cs_n
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s_data[*]
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s_banksel[*]
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}]
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set_output_delay \
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-clock [get_clocks $sdram_pll] \
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-min $sdram_output_delay_min \
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$sdram_outputs
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set_output_delay \
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-clock [get_clocks $sdram_pll] \
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-max $sdram_output_delay_max \
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$sdram_outputs
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# FPGA Inputs
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set sdram_inputs [get_ports {
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s_data[*]
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}]
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set_input_delay \
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-clock [get_clocks $sdram_pll] \
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-min $sdram_input_delay_min \
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$sdram_inputs
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set_input_delay \
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-clock [get_clocks $sdram_pll] \
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-max $sdram_input_delay_max \
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$sdram_inputs
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# SDRAM-to-FPGA multi-cycle constraint
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#
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# * The PLL is configured so that SDRAM clock leads the system
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# clock by -2.79ns
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set_multicycle_path -setup -end -from [get_clocks $sdram_pll] -to [get_clocks $sys_clk] 2
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# Reset request
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set_false_path -from [get_ports {rst_in_n}]
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# uart
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set_false_path -from [get_ports uart_rx]
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set_false_path -to [get_ports uart_tx]
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# SPI bus
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set spi_delay_max 1
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set spi_delay_min 1
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# MOSI
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set_output_delay -add_delay -clock {spi_clk} -max [expr $spi_delay_max] [get_ports {spi_mosi}]
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set_output_delay -add_delay -clock {spi_clk} -min [expr $spi_delay_min] [get_ports {spi_mosi}]
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# MISO
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set_input_delay -add_delay -clock_fall -clock {spi_clk} -max [expr $spi_delay_max] [get_ports {spi_miso}]
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set_input_delay -add_delay -clock_fall -clock {spi_clk} -min [expr $spi_delay_min] [get_ports {spi_miso}]
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# CLK
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set_output_delay -add_delay -clock {spi_clk} -max [expr $spi_delay_max] [get_ports {spi_sclk}]
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set_output_delay -add_delay -clock {spi_clk} -min [expr $spi_delay_min] [get_ports {spi_sclk}]
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set_multicycle_path -setup -start -from [get_clocks $sys_clk] -to [get_clocks {spi_clk}] 1
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set_multicycle_path -hold -start -from [get_clocks $sys_clk] -to [get_clocks {spi_clk}] 1
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set_multicycle_path -setup -end -from [get_clocks {spi_clk}] -to [get_clocks $sys_clk] 1
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set_multicycle_path -hold -end -from [get_clocks {spi_clk}] -to [get_clocks $sys_clk] 1
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set_false_path -to [get_ports {spi_ncs}]
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set_false_path -to [get_ports {leds[*]}]
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