OpenCores
URL https://opencores.org/ocsvn/s80186/s80186/trunk

Subversion Repositories s80186

[/] [s80186/] [trunk/] [rtl/] [IP.sv] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jamieiles
// Copyright Jamie Iles, 2017
2
//
3
// This file is part of s80x86.
4
//
5
// s80x86 is free software: you can redistribute it and/or modify
6
// it under the terms of the GNU General Public License as published by
7
// the Free Software Foundation, either version 3 of the License, or
8
// (at your option) any later version.
9
//
10
// s80x86 is distributed in the hope that it will be useful,
11
// but WITHOUT ANY WARRANTY; without even the implied warranty of
12
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
// GNU General Public License for more details.
14
//
15
// You should have received a copy of the GNU General Public License
16
// along with s80x86.  If not, see .
17
 
18
module IP(input logic clk,
19
          input logic reset,
20
          input logic start_instruction,
21
          input logic rollback,
22
          input logic inc,
23
          input logic wr_en,
24
          input logic [15:0] wr_val,
25
          output logic [15:0] val);
26
 
27
reg [15:0] cur_val;
28
reg [15:0] instruction_start_addr;
29
assign val = cur_val;
30
 
31
always_ff @(posedge clk or posedge reset)
32
    if (reset)
33
        instruction_start_addr <= 16'b0;
34
    else if (start_instruction)
35
        instruction_start_addr <= wr_en ? wr_val : cur_val;
36
 
37
always @(posedge clk or posedge reset)
38
    if (reset)
39
        cur_val <= 16'b0;
40
    else if (wr_en)
41
        cur_val <= wr_val;
42
    else if (rollback)
43
        cur_val <= instruction_start_addr;
44
    else if (inc)
45
        cur_val <= cur_val + 1'b1;
46
 
47
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.