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jamieiles |
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see .
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module ImmediateReader(input logic clk,
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input logic reset,
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// Control.
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input logic start,
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output logic busy,
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output logic complete,
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input logic is_8bit,
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// Result.
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output logic [15:0] immediate,
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// Fifo Read Port.
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output logic fifo_rd_en,
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input logic [7:0] fifo_rd_data,
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input logic fifo_empty);
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assign fifo_rd_en = ~fifo_empty & (start | (_fetching & ~complete));
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reg [15:0] _immediate_buf;
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wire [1:0] _num_bytes = is_8bit ? 2'h1 : 2'h2;
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reg [1:0] _bytes_read;
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reg _fetch_busy;
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wire _fetching = _fetch_busy & ~complete;
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assign complete = reset ? 1'b0 : _bytes_read == _num_bytes - 1'b1 &&
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~fifo_empty && (start || _fetch_busy);
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assign busy = (start | _fetch_busy) & ~complete;
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always_comb begin
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if (_bytes_read == 2'd0 && ~fifo_empty && start)
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immediate = {{8{fifo_rd_data[7]}}, fifo_rd_data[7:0]};
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else if (_bytes_read == 2'd1 && ~fifo_empty && !is_8bit)
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immediate = {fifo_rd_data, _immediate_buf[7:0]};
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else
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immediate = _immediate_buf;
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end
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always_ff @(posedge clk or posedge reset)
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if (reset)
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_fetch_busy <= 1'b0;
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else if (complete)
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_fetch_busy <= 1'b0;
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else if (start)
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_fetch_busy <= 1'b1;
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always_ff @(posedge clk or posedge reset) begin
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if (reset) begin
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_bytes_read <= 2'b0;
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end else begin
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if ((start && !_fetch_busy) || complete)
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_bytes_read <= 2'b0;
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if (fifo_rd_en && !complete)
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_bytes_read <= _bytes_read + 2'b1;
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end
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end
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always_ff @(posedge clk or posedge reset) begin
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if (reset) begin
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_immediate_buf <= 16'b0;
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end else begin
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if (start && !_fetch_busy) begin
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_immediate_buf <= 16'b0;
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end
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if (_bytes_read == 2'b0 && ~fifo_empty && start) begin
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_immediate_buf[7:0] <= fifo_rd_data;
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if (is_8bit)
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_immediate_buf[15:8] <= {8{fifo_rd_data[7]}};
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end else if (_bytes_read == 2'd1 && ~fifo_empty)
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_immediate_buf[15:8] <= fifo_rd_data;
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end
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end
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endmodule
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