OpenCores
URL https://opencores.org/ocsvn/s80186/s80186/trunk

Subversion Repositories s80186

[/] [s80186/] [trunk/] [rtl/] [SegmentRegisterFile.sv] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jamieiles
// Copyright Jamie Iles, 2017
2
//
3
// This file is part of s80x86.
4
//
5
// s80x86 is free software: you can redistribute it and/or modify
6
// it under the terms of the GNU General Public License as published by
7
// the Free Software Foundation, either version 3 of the License, or
8
// (at your option) any later version.
9
//
10
// s80x86 is distributed in the hope that it will be useful,
11
// but WITHOUT ANY WARRANTY; without even the implied warranty of
12
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
// GNU General Public License for more details.
14
//
15
// You should have received a copy of the GNU General Public License
16
// along with s80x86.  If not, see .
17
 
18
module SegmentRegisterFile(input logic clk,
19
                           input logic reset,
20
                           // Read port.
21
                           input logic [1:0] rd_sel,
22
                           output logic [15:0] rd_val,
23
                           // Write port.
24
                           input logic wr_en,
25
                           input logic [1:0] wr_sel,
26
                           input logic [15:0] wr_val,
27
                           // CS port.
28
                           output logic [15:0] cs);
29
 
30
reg [15:0] registers[4];
31
 
32
wire rd_bypass = wr_en && wr_sel == rd_sel;
33
 
34
assign cs = registers[CS];
35
 
36
always_ff @(posedge reset)
37
    ; // Reset is handled by the microcode
38
 
39
always_ff @(posedge clk) begin
40
    if (wr_en)
41
        registers[wr_sel] <= wr_val;
42
end
43
 
44
always_ff @(posedge clk)
45
    rd_val <= rd_bypass ? wr_val : registers[rd_sel];
46
 
47
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.