OpenCores
URL https://opencores.org/ocsvn/s80186/s80186/trunk

Subversion Repositories s80186

[/] [s80186/] [trunk/] [rtl/] [alu/] [add.sv] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jamieiles
// Copyright Jamie Iles, 2017
2
//
3
// This file is part of s80x86.
4
//
5
// s80x86 is free software: you can redistribute it and/or modify
6
// it under the terms of the GNU General Public License as published by
7
// the Free Software Foundation, either version 3 of the License, or
8
// (at your option) any later version.
9
//
10
// s80x86 is distributed in the hope that it will be useful,
11
// but WITHOUT ANY WARRANTY; without even the implied warranty of
12
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
// GNU General Public License for more details.
14
//
15
// You should have received a copy of the GNU General Public License
16
// along with s80x86.  If not, see .
17
 
18
task do_add;
19
    output [15:0] out;
20
    input is_8_bit;
21
    input [15:0] a;
22
    input [15:0] b;
23
    input [15:0] flags_in;
24
    output [15:0] flags_out;
25
 
26
    begin
27
        flags_out = flags_in;
28
        if (!is_8_bit) begin
29
            {flags_out[CF_IDX], out} = a + b;
30
            flags_out[OF_IDX] = ~(a[15] ^ b[15]) & (out[15] ^ b[15]);
31
        end else begin
32
            out = a + b;
33
            flags_out[CF_IDX] = a[8] ^ b[8] ^ out[8];
34
            flags_out[OF_IDX] = ~(a[7] ^ b[7]) & (out[7] ^ b[7]);
35
        end
36
        common_flags(flags_out, is_8_bit, out, a, b);
37
    end
38
endtask

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.