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[/] [s80186/] [trunk/] [rtl/] [cdc/] [BitSync.sv] - Blame information for rev 2

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1 2 jamieiles
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86.  If not, see .
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module BitSync(input logic clk,
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               input logic d,
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               output logic q);
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reg p1;
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reg p2;
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assign q = p2;
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always_ff @(posedge clk)
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    p1 <= d;
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always_ff @(posedge clk)
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    p2 <= p1;
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endmodule

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