Subversion Repositories s80186

// Copyright Jamie Iles, 2017

//

// This file is part of s80x86.

//

// s80x86 is free software: you can redistribute it and/or modify

// it under the terms of the GNU General Public License as published by

// the Free Software Foundation, either version 3 of the License, or

// (at your option) any later version.

//

// s80x86 is distributed in the hope that it will be useful,

// but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

// GNU General Public License for more details.

//

// You should have received a copy of the GNU General Public License

// along with s80x86.  If not, see .

.at 0xe8;

    read_immed, jmp calle8, ra_sel SP;

.auto_address;

calle8:

    a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,

        rd_sel_source MICROCODE_RD_SEL, mar_write,

        mar_wr_sel Q;

    a_sel IP, alu_op SELA, mdr_write, ra_sel SP, segment SS, segment_force;

    segment SS, segment_force, mem_write, a_sel IP, b_sel IMMEDIATE,

        alu_op ADD, load_ip, next_instruction;

callff_indirect_intra_reg:

    a_sel RA, alu_op SELA, load_ip, jmp callff_indirect_intra_save,

        ra_sel SP;

callff_indirect_intra_mem:

    segment DS, mem_read;

    a_sel MDR, alu_op SELA, load_ip, jmp callff_indirect_intra_save,

        ra_sel SP;

callff_indirect_intra_save:

    a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,

        rd_sel_source MICROCODE_RD_SEL, mar_write,

        mar_wr_sel Q;

    a_sel IP, alu_op SELA, mdr_write, ra_sel SP, segment SS, segment_force;

    segment SS, segment_force, mem_write, next_instruction;

.at 0x9a;

    jmp call9a, read_immed, mdr_write, b_sel IMMEDIATE, alu_op SELB;

.auto_address;

call9a:

    read_immed;

    // New IP is now in MDR, new CS is in the immediate reader.

    //

    // This instruction implementation is very subtle - it's important to read

    // both immediates before performing any stack accesses so that IP is

    // correct in case of any kind of fault rather than being in the middle of

    // the instruction stream.

    a_sel MDR, alu_op SELA, load_ip, segment CS;

    b_sel SR, alu_op SELB, mdr_write, ra_sel SP;

    a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,

        rd_sel_source MICROCODE_RD_SEL, mar_write,

        mar_wr_sel Q, segment_force, segment SS;

    segment_force, segment SS, mem_write, ra_sel SP;

    a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,

        rd_sel_source MICROCODE_RD_SEL, mar_write,

        mar_wr_sel Q;

    a_sel IP, alu_op SELA, mdr_write, segment_force, segment SS;

    segment_force, segment SS, mem_write;

    b_sel IMMEDIATE, alu_op SELB, segment_force, segment CS,

        segment_wr_en, next_instruction;

callff_indirect_inter_reg:

    next_instruction;

callff_indirect_inter_mem:

    b_sel SR, alu_op SELB, mdr_write, ra_sel SP;

    a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,

        rd_sel_source MICROCODE_RD_SEL, mar_write,

        mar_wr_sel Q, segment_force, segment SS;

    segment_force, segment SS, mem_write, ra_sel SP;

    a_sel RA, b_sel IMMEDIATE, immediate 0x2, alu_op SUB, rd_sel SP,

        rd_sel_source MICROCODE_RD_SEL, mar_write,

        mar_wr_sel Q;

    a_sel IP, alu_op SELA, mdr_write, segment_force, segment SS;

    segment_force, segment SS, mem_write;

    mar_wr_sel EA, mar_write, segment DS;

    segment DS, mem_read;

    a_sel MDR, alu_op SELA, load_ip;

    a_sel MAR, b_sel IMMEDIATE, immediate 0x2, alu_op ADD,

        mar_wr_sel Q, mar_write, segment DS;

    segment DS, mem_read;

    a_sel MDR, alu_op SELA, segment_wr_en,

        segment_force, segment CS, next_instruction;