OpenCores
URL https://opencores.org/ocsvn/s80186/s80186/trunk

Subversion Repositories s80186

[/] [s80186/] [trunk/] [sim/] [CGA.h] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jamieiles
// Copyright Jamie Iles, 2017
2
//
3
// This file is part of s80x86.
4
//
5
// s80x86 is free software: you can redistribute it and/or modify
6
// it under the terms of the GNU General Public License as published by
7
// the Free Software Foundation, either version 3 of the License, or
8
// (at your option) any later version.
9
//
10
// s80x86 is distributed in the hope that it will be useful,
11
// but WITHOUT ANY WARRANTY; without even the implied warranty of
12
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
// GNU General Public License for more details.
14
//
15
// You should have received a copy of the GNU General Public License
16
// along with s80x86.  If not, see <http://www.gnu.org/licenses/>.
17
 
18
#pragma once
19
 
20
#include <boost/serialization/list.hpp>
21
#include <boost/serialization/string.hpp>
22
#include <boost/serialization/version.hpp>
23
 
24
#include "CPU.h"
25
#include "Cursor.h"
26
#include "Display.h"
27
 
28
class CGA : public IOPorts
29
{
30
private:
31
    enum CRTCRegs {
32
        CURSOR_SCAN_START = 0xa,
33
        CURSOR_SCAN_END = 0xb,
34
        CURSOR_HIGH = 0xe,
35
        CURSOR_LOW = 0xf,
36
    };
37
 
38
public:
39
    const phys_addr buffer_phys = 0xb8000;
40
 
41
    explicit CGA(Memory *mem)
42
        : IOPorts(0x03d4, 8), mem(mem), reg_idx(0), status(0)
43
    {
44
        memset(idx_regs, 0, sizeof(idx_regs));
45
    }
46
 
47
    void write8(uint16_t __unused port_num,
48
                unsigned __unused offs,
49
                uint8_t __unused v)
50
    {
51
        if (port_num == 0 && offs == 0) {
52
            reg_idx = v;
53
        } else if (port_num == 0 && offs == 1) {
54
            idx_regs[reg_idx] = v;
55
        }
56
    }
57
 
58
    uint8_t read8(uint16_t __unused port_num, unsigned __unused offs)
59
    {
60
        if (port_num == 0) {
61
            return offs == 0 ? reg_idx : idx_regs[reg_idx];
62
        } else if (port_num == 6 && offs == 0) {
63
            status ^= 0x1;
64
            return status;
65
        }
66
 
67
        return 0;
68
    }
69
 
70
    void update();
71
 
72
private:
73
    Cursor get_cursor() const
74
    {
75
        auto cursor_loc = (static_cast<uint16_t>(idx_regs[CURSOR_HIGH]) << 8) |
76
                          idx_regs[CURSOR_LOW];
77
        auto cursor_row = cursor_loc / 80;
78
        auto cursor_col = cursor_loc % 80;
79
        auto cursor_scan_start = idx_regs[CURSOR_SCAN_START] & 0xf;
80
        auto cursor_scan_end = idx_regs[CURSOR_SCAN_END] & 0xf;
81
        auto cursor_enabled = (idx_regs[CURSOR_SCAN_START] & 0x30) != 0x10;
82
 
83
        return Cursor(cursor_row * 8 + (cursor_scan_start),
84
                      cursor_row * 8 + (cursor_scan_end), cursor_col * 8,
85
                      cursor_col * 8 + 8, cursor_enabled);
86
    }
87
 
88
    Memory *mem;
89
    Display display;
90
    uint8_t reg_idx;
91
    uint8_t idx_regs[256];
92
    uint8_t status;
93
 
94
    friend class boost::serialization::access;
95
    template <class Archive>
96
    void serialize(Archive &ar, const unsigned int __unused version)
97
    {
98
        // clang-format off
99
        ar & mem;
100
        ar & reg_idx;
101
        ar & idx_regs;
102
        ar & status;
103
        // clang-format on
104
    }
105
};
106
 
107
void CGA::update()
108
{
109
    int cols = 80;
110
    int rows = 25;
111
 
112
    for (auto row = 0; row < rows; ++row) {
113
        for (auto col = 0; col < cols; ++col) {
114
            auto addr = buffer_phys + ((row * cols) + col) * sizeof(uint16_t);
115
            auto char_attr = mem->read<uint16_t>(addr);
116
 
117
            display.set_cursor(row, col);
118
            display.write_char(char_attr);
119
        }
120
    }
121
 
122
    display.refresh(get_cursor());
123
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.