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[/] [s80186/] [trunk/] [sim/] [RTLCPU/] [RTLCPU.h] - Blame information for rev 2

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1 2 jamieiles
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86.  If not, see <http://www.gnu.org/licenses/>.
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#pragma once
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#include <functional>
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#include <map>
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#include <string>
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#include <VerilogDriver.h>
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#include <VRTLCPU.h>
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#include "CPU.h"
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#include "RegisterFile.h"
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static inline void null_io(unsigned long __unused v)
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{
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}
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template <bool debug_enabled = verilator_debug_enabled>
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class RTLCPU : public VerilogDriver<VRTLCPU, debug_enabled>, public SimCPU
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{
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public:
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    RTLCPU(const std::string &test_name);
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    void write_coverage();
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    void reset();
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    void write_reg(GPR regnum, uint16_t val);
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    uint16_t read_reg(GPR regnum) const;
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    void start_instruction();
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    void cycle_cpu()
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    {
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        this->cycle();
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    }
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    size_t step_with_io(std::function<void(unsigned long)> io_callback);
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    void cycle_cpu_with_io(std::function<void(unsigned long)> io_callback);
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    void complete_instruction();
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    bool int_yield_ready();
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    void debug_detach();
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    size_t step();
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    void idle(int count);
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    int time_step();
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    void write_flags(uint16_t val);
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    uint16_t read_flags() const;
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    bool has_trapped();
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    int debug_run_proc(
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        unsigned addr,
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        std::function<void(unsigned long)> io_callback = null_io);
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    void debug_seize();
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    int debug_step(std::function<void(unsigned long)> io_callback);
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    bool debug_is_stopped() const
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    {
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        return is_stopped;
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    }
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    bool instruction_had_side_effects() const
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    {
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        return mem.has_written();
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    }
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    void clear_side_effects()
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    {
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        mem.clear_has_written();
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    }
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    void write_mem8(uint16_t segment, uint16_t addr, uint8_t val);
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    void write_mem16(uint16_t segment, uint16_t addr, uint16_t val);
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    void write_mem32(uint16_t segment, uint16_t addr, uint32_t val);
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    uint8_t read_mem8(uint16_t segment, uint16_t addr);
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    uint16_t read_mem16(uint16_t segment, uint16_t addr);
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    uint32_t read_mem32(uint16_t segment, uint16_t addr);
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    void write_io8(uint32_t addr, uint8_t val);
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    void write_io16(uint32_t addr, uint16_t val);
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    uint8_t read_io8(uint32_t addr);
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    uint16_t read_io16(uint32_t addr);
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    void add_ioport(IOPorts *p)
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    {
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        for (size_t m = 0; m < p->get_num_ports(); ++m)
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            io[p->get_base() + m * sizeof(uint16_t)] = p;
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    }
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    void write_vector8(uint16_t segment,
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                       uint16_t addr,
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                       const std::vector<uint8_t> &v);
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    void write_vector16(uint16_t segment,
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                        uint16_t addr,
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                        const std::vector<uint16_t> &v);
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    virtual bool has_instruction_length() const
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    {
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        return true;
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    }
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    virtual void raise_nmi()
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    {
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        this->after_n_cycles(0, [this] {
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            this->dut.nmi = 1;
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            this->after_n_cycles(1, [this] { this->dut.nmi = 0; });
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        });
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        this->cycle();
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    }
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    virtual void raise_irq(int irq_num)
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    {
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        pending_irq = irq_num;
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    }
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    unsigned long cycle_count() const
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    {
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        return static_cast<unsigned long>(this->cur_cycle());
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    }
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private:
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    uint16_t get_microcode_address();
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    void mem_access();
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    void io_access();
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    uint16_t read_ip() const;
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    uint16_t read_sr(GPR regnum) const;
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    uint16_t read_gpr(GPR regnum) const;
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    void write_ip(uint16_t v);
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    void write_sr(GPR regnum, uint16_t v);
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    void write_gpr(GPR regnum, uint16_t v);
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    size_t get_and_clear_instr_length();
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    void debug_write_data(uint16_t v);
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    void write_mar(uint16_t v);
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    void write_mdr(uint16_t v);
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    bool mem_in_progress;
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    bool io_in_progress;
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    int mem_latency;
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    std::string test_name;
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    bool is_stopped;
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    std::map<uint16_t, IOPorts *> io;
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    uint8_t pending_irq;
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    bool int_in_progress;
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};

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