OpenCores
URL https://opencores.org/ocsvn/s80186/s80186/trunk

Subversion Repositories s80186

[/] [s80186/] [trunk/] [sim/] [cppmodel/] [instructions/] [xchg.cpp] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jamieiles
// Copyright Jamie Iles, 2017
2
//
3
// This file is part of s80x86.
4
//
5
// s80x86 is free software: you can redistribute it and/or modify
6
// it under the terms of the GNU General Public License as published by
7
// the Free Software Foundation, either version 3 of the License, or
8
// (at your option) any later version.
9
//
10
// s80x86 is distributed in the hope that it will be useful,
11
// but WITHOUT ANY WARRANTY; without even the implied warranty of
12
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
// GNU General Public License for more details.
14
//
15
// You should have received a copy of the GNU General Public License
16
// along with s80x86.  If not, see <http://www.gnu.org/licenses/>.
17
 
18
// xchg r, r/m, 8-bit
19
void EmulatorPimpl::xchg86()
20
{
21
    modrm_decoder->set_width(OP_WIDTH_8);
22
    modrm_decoder->decode();
23
 
24
    auto v1 = read_data<uint8_t>();
25
    auto v2 = registers->get(modrm_decoder->reg());
26
 
27
    write_data<uint8_t>(v2);
28
    registers->set(modrm_decoder->reg(), v1);
29
}
30
 
31
// xchg r, r/m, 16-bit
32
void EmulatorPimpl::xchg87()
33
{
34
    modrm_decoder->set_width(OP_WIDTH_16);
35
    modrm_decoder->decode();
36
 
37
    auto v1 = read_data<uint16_t>();
38
    auto v2 = registers->get(modrm_decoder->reg());
39
 
40
    write_data<uint16_t>(v2);
41
    registers->set(modrm_decoder->reg(), v1);
42
}
43
 
44
// xchg accumulator, r
45
void EmulatorPimpl::xchg90_97()
46
{
47
    auto reg = static_cast<GPR>(static_cast<int>(AX) + (opcode & 0x7));
48
 
49
    auto v1 = registers->get(AX);
50
    auto v2 = registers->get(reg);
51
 
52
    registers->set(AX, v2);
53
    registers->set(reg, v1);
54
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.