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jamieiles |
http://sf.net/apps/mediawiki/urjtag/index.php?title=Cable_Altera_USB-Blaster
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----------------------------------------------------------------------------
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Altera USB-Blaster
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------------------
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General
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-------
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_________
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| AT93C46 |
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|_________|
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__|__________ _________
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USB__| FTDI 245BM |__| EPM7064 |__JTAG (B_TDO,B_TDI,B_TMS,B_TCK)
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|_____________| |_________|
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__|__________ _|___________
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| 6 MHz XTAL | | 24 MHz Osc. |
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|_____________| |_____________|
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Quoting from ixo.de (http://www.ixo.de/info/usb_jtag/)
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usb_jtag/device/c51/usbjtag.c comments:
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usb_jtag firmware now happens to behave just like the combination of
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FT245BM and Altera-programmed EPM7064 CPLD in Altera's USB-Blaster.
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The CPLD knows two major modes: Bit banging mode and Byte shift mode.
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It starts in Bit banging mode. While bytes are received from the host
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on EP2OUT, each byte B of them is processed as follows:
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Bit banging mode
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----------------
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1. Remember bit 6 (0x40) in B as the "Read bit".
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2. If bit 7 (0x80) is set, switch to Byte shift mode for the coming X
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bytes ( X := B & 0x3F ), and don't do anything else now.
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3. Otherwise, set the JTAG signals as follows:
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- TCK/DCLK high if bit 0 was set (0x01), otherwise low
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- TMS/nCONFIG high if bit 1 was set (0x02), otherwise low
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- nCE high if bit 2 was set (0x04), otherwise low
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- nCS high if bit 3 was set (0x08), otherwise low
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- TDI/ASDI/DATAO high if bit 4 was set (0x10), otherwise low
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- Output Enable/LED active if bit 5 was set (0x20), otherwise low
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4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and
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DATAOUT/(nSTATUS) pins and put is as a byte( (DATAOUT<<1)|TDO) in the
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output FIFO _to_ the host.
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Byte shift mode
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---------------
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1. Load shift register with byte from host
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2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51)
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- if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT
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(Active Serial mode)
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- Rotate shift register through carry bit
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- TDI := Carry bit
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- Raise TCK, then lower TCK.
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3. If "Read bit" was set when switching into byte shift mode, record the
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shift register content and put it into the FIFO to the host.
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