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//! Memory model for 5-stage version of MIPS
//
// $Id: memory2.cpp,v 1.1 2006-01-25 17:00:11 igorloi Exp $
//
 
#include "memory2.h"
#include <iomanip.h>
#include <iostream.h>
 
//! Bla bla..
//
// Get the memory module @ memaddr
// Output to memdata...
//
void memory2::mread()
{
  sc_lv<32> fd3_map = FD3_MAP;
  sc_uint<32> uifd3_map = fd3_map;
  sc_lv<32> stop_cpu_map = STOP_CPU_MAP;
  sc_uint<32> uistop_cpu_map = stop_cpu_map;
 
  if(memaddr == uistop_cpu_map)
     sc_stop();
  else ;
 
  sc_lv<32> lmemaddr;
  sc_uint<32> imemaddr;
  sc_lv<2> byteselect;
  sc_uint<32> lmemdataread;
 
  if (memreq.read() == SC_LOGIC_1)
    {}
 
  if ((memreq.read() == 1) && (memrw.read() == 0) && (reset.read() == false))
    {
      imemaddr = memaddr.read();
      lmemaddr = memaddr.read();
      if (lmemaddr(1,0) != "00")
        {
          // cout << "UNALIGNED ADDRESS" << endl;
        }
 
      byteselect = membs.read();
      if (lmemaddr(1,0) == "01") // Unaligned...
        {
          lmemdataread = x[imemaddr >> 2];
          if (byteselect == "01") // Select byte, zero rest
            lmemdataread = ("000000000000000000000000", lmemdataread.range(15,8));
          else if (byteselect == "10") // Select halfword, zero rest
            lmemdataread = ("0000000000000000", lmemdataread.range(23,8));
          else // Select word, this line doesn't work properly because of unalignment!
            lmemdataread = lmemdataread;
        }
      else if (lmemaddr(1,0) == "10") // Unaligned...
        {
          lmemdataread = x[imemaddr >> 2];
          // cout << "test  " << lmemdataread << endl;
          if (byteselect == "01")
            lmemdataread = ("000000000000000000000000", lmemdataread.range(23,16));
          else
            lmemdataread = ("0000000000000000", lmemdataread.range(31,16));
          // cout << "test2 " << lmemdataread << endl;
        }
      else if (lmemaddr(1,0) == "11") // Unaligned...
        {
          lmemdataread = x[imemaddr >> 2];
          lmemdataread = ("000000000000000000000000", lmemdataread.range(31,24));
        }
      else // Aligned!
        {
          // cout << "go! " << byteselect << endl;
          lmemdataread = x[imemaddr >> 2];
          // cout << "lmemdataread = " << lmemdataread << endl;
          if (byteselect == "01")
            lmemdataread = ("000000000000000000000000", lmemdataread.range(7,0));
          else if (byteselect == "10")
            lmemdataread = ("0000000000000000", lmemdataread.range(15,0));
          else
            lmemdataread = lmemdataread;
        }
    }
  else
    {
      lmemdataread = WORD_ZERO;
    }
 
  memdataread = lmemdataread;
}
 
//! Bla bla
//
// For writing - read input from data and write to memaddr...
//
void memory2::mwrite()
{
  sc_lv<32> lmemdata;
  sc_lv<32> lmemdatawrite;
  sc_lv<32> lmemaddr;
  sc_uint<32> imemaddr;
  sc_lv<2> byteselect = membs;
 
#ifdef _CC_MEMDUMP_
  // For writing
  unsigned int i;
  int j;
#endif
  sc_uint<32> imemdata;
 
  if (memrw.read() == SC_LOGIC_1)
    {}
 
  if ((memreq.read() == 1) && (memrw.read() == 1) && (reset.read() == false))
    {
      lmemdatawrite = memdatawrite.read();
 
      imemaddr = memaddr.read();
      lmemaddr = memaddr.read();
      if (lmemaddr.range(1,0) != "00")
        {
          // imemaddr = imemaddr + 4;
        }
 
      if (lmemaddr.range(1,0) == "00")
        {
          lmemdata = x[imemaddr >> 2];
          if (byteselect == "01")
            lmemdata = (lmemdata.range(31,8), lmemdatawrite.range(7,0));
          else if (byteselect == "10")
            lmemdata = (lmemdata.range(31,16), lmemdatawrite.range(15,0));
          else
            lmemdata = lmemdatawrite;
        }
      else if (lmemaddr.range(1,0) == "01")
        {
          lmemdata = x[imemaddr >> 2];
          if (byteselect == "01") // Write one byte
            lmemdata = (lmemdata.range(31,16), lmemdatawrite.range(7,0), lmemdata.range(7,0));
          else if (byteselect == "10")
            lmemdata = (lmemdata.range(31,24), lmemdatawrite.range(15,0), lmemdata.range(7,0));
          else // NB! Doesn't work to write entire words unaligned!
            lmemdata = (lmemdatawrite.range(23,0), lmemdata.range(7,0));
        }
      else if (lmemaddr.range(1,0) == "10")
        {
          lmemdata = x[imemaddr >> 2];
          if (byteselect == "01")
            lmemdata = (lmemdata.range(31,24), lmemdatawrite.range(7,0), lmemdata.range(15,0));
          else
            lmemdata = (lmemdatawrite.range(15,0), lmemdata.range(15,0));
        }
      else // if (lmemaddr.range(1,0) == "11")
        {
          lmemdata = x[imemaddr >> 2];
          lmemdata = (lmemdatawrite.range(7,0), lmemdata.range(23,0));
        }
 
#ifdef _DEBUG_MEMORY_
      cout << memoryname << ": lmemdata = " << lmemdata << endl;
#endif
      imemdata = lmemdata;
      x[imemaddr >> 2] = imemdata;
 
#ifdef _CC_MEMDUMP_
      i = imemdata;
      memcontents = open("mem.bin", O_CREAT | O_RDWR, 0666);
      for (j = 0; j < 10000; j++)
        {
          i = x[j];
          write(memcontents, &i, 4);
        }
      close(memcontents);
#endif
    }
}
 
void memory2::page_fault_analyzer()
{
        if(memreq == SC_LOGIC_1)
        {
           if(( (unsigned int) memaddr.read() )  < MEMSIZE)
              page_fault.write(SC_LOGIC_0);
           else
              page_fault.write(SC_LOGIC_1);
        }
        else page_fault.write(SC_LOGIC_0);
}
 
 
void memory2::check_load_aligned()
{
        sc_uint<2>      twobit;
        sc_uint<1>      onebit;
 
        twobit = (memaddr.read()).range(1,0);
        onebit = (memaddr.read()).range(0,0);
 
        if(memreq == SC_LOGIC_1 )
        {
                if(membs.read() == "00")  //accesso ad una word
                {
                   if(twobit == 0)
                        addrl.write(SC_LOGIC_0);  //dato allineato
                   else
                        addrl.write(SC_LOGIC_1); // dato disallineato
                }
                else
                   if(membs.read() == "10")  // accesso ad una half word
                   {
                      if(memreq == SC_LOGIC_1)
                         if(onebit == 0 )
                            addrl.write(SC_LOGIC_0);  //dato allineato
                         else
                            addrl.write(SC_LOGIC_1); // dato disallineato
                   }
                // L'accesso a singolo byte non genera mai errori
        }
        else
           addrl.write(SC_LOGIC_0);
}
 
void memory2::check_store_aligned()
{
        sc_uint<2>      twobit;
        sc_uint<1>      onebit;
 
        twobit = (memaddr.read()).range(1,0);
        onebit = (memaddr.read()).range(0,0);
 
        if((memreq.read() == SC_LOGIC_1 ) && (memrw.read() == SC_LOGIC_1 ) )
        {
                if(membs.read() == "00")  //aligned data accesso a word
                {
                   if(twobit == 0)
                        addrs.write(SC_LOGIC_0);  //dato allineato
                   else
                        addrs.write(SC_LOGIC_1); // dato disallineato
                }
                else
                   if(membs.read() == "10")  // accesso ad una half word
                   {
                      if(onebit == 0)
                        addrs.write(SC_LOGIC_0);  //dato allineato
                      else
                        addrs.write(SC_LOGIC_1); // dato disallineato
                }
                // L'accesso a singolo byte non genera mai errori
        }
        else
           addrs.write(SC_LOGIC_0);
}
 
 
 

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[/] [sardmips/] [branches/] [avendor/] [source/] [memory/] [memory2.cpp] - Blame information for rev 7

Line No.	Rev	Author	Line
1	4	igorloi	`//! Memory model for 5-stage version of MIPS`
2			`//`
3			`// $Id: memory2.cpp,v 1.1 2006-01-25 17:00:11 igorloi Exp $`
4			`//`
5
6			`#include "memory2.h"`
7			`#include <iomanip.h>`
8			`#include <iostream.h>`
9
10			`//! Bla bla..`
11			`//`
12			`// Get the memory module @ memaddr`
13			`// Output to memdata...`
14			`//`
15			`void memory2::mread()`
16			`{`
17			`sc_lv<32> fd3_map = FD3_MAP;`
18			`sc_uint<32> uifd3_map = fd3_map;`
19			`sc_lv<32> stop_cpu_map = STOP_CPU_MAP;`
20			`sc_uint<32> uistop_cpu_map = stop_cpu_map;`
21
22			`if(memaddr == uistop_cpu_map)`
23			`sc_stop();`
24			`else ;`
25
26			`sc_lv<32> lmemaddr;`
27			`sc_uint<32> imemaddr;`
28			`sc_lv<2> byteselect;`
29			`sc_uint<32> lmemdataread;`
30
31			`if (memreq.read() == SC_LOGIC_1)`
32			`{}`
33
34			`if ((memreq.read() == 1) && (memrw.read() == 0) && (reset.read() == false))`
35			`{`
36			`imemaddr = memaddr.read();`
37			`lmemaddr = memaddr.read();`
38			`if (lmemaddr(1,0) != "00")`
39			`{`
40			`// cout << "UNALIGNED ADDRESS" << endl;`
41			`}`
42
43			`byteselect = membs.read();`
44			`if (lmemaddr(1,0) == "01") // Unaligned...`
45			`{`
46			`lmemdataread = x[imemaddr >> 2];`
47			`if (byteselect == "01") // Select byte, zero rest`
48			`lmemdataread = ("000000000000000000000000", lmemdataread.range(15,8));`
49			`else if (byteselect == "10") // Select halfword, zero rest`
50			`lmemdataread = ("0000000000000000", lmemdataread.range(23,8));`
51			`else // Select word, this line doesn't work properly because of unalignment!`
52			`lmemdataread = lmemdataread;`
53			`}`
54			`else if (lmemaddr(1,0) == "10") // Unaligned...`
55			`{`
56			`lmemdataread = x[imemaddr >> 2];`
57			`// cout << "test " << lmemdataread << endl;`
58			`if (byteselect == "01")`
59			`lmemdataread = ("000000000000000000000000", lmemdataread.range(23,16));`
60			`else`
61			`lmemdataread = ("0000000000000000", lmemdataread.range(31,16));`
62			`// cout << "test2 " << lmemdataread << endl;`
63			`}`
64			`else if (lmemaddr(1,0) == "11") // Unaligned...`
65			`{`
66			`lmemdataread = x[imemaddr >> 2];`
67			`lmemdataread = ("000000000000000000000000", lmemdataread.range(31,24));`
68			`}`
69			`else // Aligned!`
70			`{`
71			`// cout << "go! " << byteselect << endl;`
72			`lmemdataread = x[imemaddr >> 2];`
73			`// cout << "lmemdataread = " << lmemdataread << endl;`
74			`if (byteselect == "01")`
75			`lmemdataread = ("000000000000000000000000", lmemdataread.range(7,0));`
76			`else if (byteselect == "10")`
77			`lmemdataread = ("0000000000000000", lmemdataread.range(15,0));`
78			`else`
79			`lmemdataread = lmemdataread;`
80			`}`
81			`}`
82			`else`
83			`{`
84			`lmemdataread = WORD_ZERO;`
85			`}`
86
87			`memdataread = lmemdataread;`
88			`}`
89
90			`//! Bla bla`
91			`//`
92			`// For writing - read input from data and write to memaddr...`
93			`//`
94			`void memory2::mwrite()`
95			`{`
96			`sc_lv<32> lmemdata;`
97			`sc_lv<32> lmemdatawrite;`
98			`sc_lv<32> lmemaddr;`
99			`sc_uint<32> imemaddr;`
100			`sc_lv<2> byteselect = membs;`
101
102			`#ifdef _CC_MEMDUMP_`
103			`// For writing`
104			`unsigned int i;`
105			`int j;`
106			`#endif`
107			`sc_uint<32> imemdata;`
108
109			`if (memrw.read() == SC_LOGIC_1)`
110			`{}`
111
112			`if ((memreq.read() == 1) && (memrw.read() == 1) && (reset.read() == false))`
113			`{`
114			`lmemdatawrite = memdatawrite.read();`
115
116			`imemaddr = memaddr.read();`
117			`lmemaddr = memaddr.read();`
118			`if (lmemaddr.range(1,0) != "00")`
119			`{`
120			`// imemaddr = imemaddr + 4;`
121			`}`
122
123			`if (lmemaddr.range(1,0) == "00")`
124			`{`
125			`lmemdata = x[imemaddr >> 2];`
126			`if (byteselect == "01")`
127			`lmemdata = (lmemdata.range(31,8), lmemdatawrite.range(7,0));`
128			`else if (byteselect == "10")`
129			`lmemdata = (lmemdata.range(31,16), lmemdatawrite.range(15,0));`
130			`else`
131			`lmemdata = lmemdatawrite;`
132			`}`
133			`else if (lmemaddr.range(1,0) == "01")`
134			`{`
135			`lmemdata = x[imemaddr >> 2];`
136			`if (byteselect == "01") // Write one byte`
137			`lmemdata = (lmemdata.range(31,16), lmemdatawrite.range(7,0), lmemdata.range(7,0));`
138			`else if (byteselect == "10")`
139			`lmemdata = (lmemdata.range(31,24), lmemdatawrite.range(15,0), lmemdata.range(7,0));`
140			`else // NB! Doesn't work to write entire words unaligned!`
141			`lmemdata = (lmemdatawrite.range(23,0), lmemdata.range(7,0));`
142			`}`
143			`else if (lmemaddr.range(1,0) == "10")`
144			`{`
145			`lmemdata = x[imemaddr >> 2];`
146			`if (byteselect == "01")`
147			`lmemdata = (lmemdata.range(31,24), lmemdatawrite.range(7,0), lmemdata.range(15,0));`
148			`else`
149			`lmemdata = (lmemdatawrite.range(15,0), lmemdata.range(15,0));`
150			`}`
151			`else // if (lmemaddr.range(1,0) == "11")`
152			`{`
153			`lmemdata = x[imemaddr >> 2];`
154			`lmemdata = (lmemdatawrite.range(7,0), lmemdata.range(23,0));`
155			`}`
156
157			`#ifdef _DEBUG_MEMORY_`
158			`cout << memoryname << ": lmemdata = " << lmemdata << endl;`
159			`#endif`
160			`imemdata = lmemdata;`
161			`x[imemaddr >> 2] = imemdata;`
162
163			`#ifdef _CC_MEMDUMP_`
164			`i = imemdata;`
165			`memcontents = open("mem.bin", O_CREAT \| O_RDWR, 0666);`
166			`for (j = 0; j < 10000; j++)`
167			`{`
168			`i = x[j];`
169			`write(memcontents, &i, 4);`
170			`}`
171			`close(memcontents);`
172			`#endif`
173			`}`
174			`}`
175
176			`void memory2::page_fault_analyzer()`
177			`{`
178			`if(memreq == SC_LOGIC_1)`
179			`{`
180			`if(( (unsigned int) memaddr.read() ) < MEMSIZE)`
181			`page_fault.write(SC_LOGIC_0);`
182			`else`
183			`page_fault.write(SC_LOGIC_1);`
184			`}`
185			`else page_fault.write(SC_LOGIC_0);`
186			`}`
187
188
189			`void memory2::check_load_aligned()`
190			`{`
191			`sc_uint<2> twobit;`
192			`sc_uint<1> onebit;`
193
194			`twobit = (memaddr.read()).range(1,0);`
195			`onebit = (memaddr.read()).range(0,0);`
196
197			`if(memreq == SC_LOGIC_1 )`
198			`{`
199			`if(membs.read() == "00") //accesso ad una word`
200			`{`
201			`if(twobit == 0)`
202			`addrl.write(SC_LOGIC_0); //dato allineato`
203			`else`
204			`addrl.write(SC_LOGIC_1); // dato disallineato`
205			`}`
206			`else`
207			`if(membs.read() == "10") // accesso ad una half word`
208			`{`
209			`if(memreq == SC_LOGIC_1)`
210			`if(onebit == 0 )`
211			`addrl.write(SC_LOGIC_0); //dato allineato`
212			`else`
213			`addrl.write(SC_LOGIC_1); // dato disallineato`
214			`}`
215			`// L'accesso a singolo byte non genera mai errori`
216			`}`
217			`else`
218			`addrl.write(SC_LOGIC_0);`
219			`}`
220
221			`void memory2::check_store_aligned()`
222			`{`
223			`sc_uint<2> twobit;`
224			`sc_uint<1> onebit;`
225
226			`twobit = (memaddr.read()).range(1,0);`
227			`onebit = (memaddr.read()).range(0,0);`
228
229			`if((memreq.read() == SC_LOGIC_1 ) && (memrw.read() == SC_LOGIC_1 ) )`
230			`{`
231			`if(membs.read() == "00") //aligned data accesso a word`
232			`{`
233			`if(twobit == 0)`
234			`addrs.write(SC_LOGIC_0); //dato allineato`
235			`else`
236			`addrs.write(SC_LOGIC_1); // dato disallineato`
237			`}`
238			`else`
239			`if(membs.read() == "10") // accesso ad una half word`
240			`{`
241			`if(onebit == 0)`
242			`addrs.write(SC_LOGIC_0); //dato allineato`
243			`else`
244			`addrs.write(SC_LOGIC_1); // dato disallineato`
245			`}`
246			`// L'accesso a singolo byte non genera mai errori`
247			`}`
248			`else`
249			`addrs.write(SC_LOGIC_0);`
250			`}`
251
252
253