OpenCores
URL https://opencores.org/ocsvn/sardmips/sardmips/trunk

Subversion Repositories sardmips

[/] [sardmips/] [trunk/] [source/] [cpu/] [mux_instaddr.cpp] - Blame information for rev 18

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 igorloi
#include "mux_instaddr.h"
2
 
3
void mux_instaddr::do_mux_instaddr()
4
{
5
        if(m_wb_interrupt_signal.read() == true)
6
        {
7
           sc_lv<16> temp_1;
8
           sc_lv<5>  temp_2;
9
           sc_lv<6>  temp_3;
10
 
11
           temp_1 = (ex_mem_inst.read()).range(31,16);          // upper 16 bit 
12
           temp_2 = (ex_mem_inst.read()).range(10,6);           //
13
           temp_3 = (ex_mem_inst.read()).range(5,0);             //opcode
14
 
15
           cout << " interrupt" << endl;
16
           cout << " temp1 = " << temp_1 << endl;
17
           cout << " temp2 = " << temp_2 << endl;
18
           cout << " temp3 = " << temp_3 << endl;
19
           cout << " inst = " << ex_mem_inst.read() << endl;
20
 
21
           //|| 
22
 
23
 
24
           if(((ex_m_instaddr.read() - m_wb_instaddr.read()) == 4))
25
           {
26
              if(((temp_1 == HALFWORD_ZERO) && (temp_2 == "00000") && ((temp_3 == "010010") || (temp_3 == "010000") )))
27
              {
28
                 m_wb_instaddr_s.write(m_wb_instaddr.read() - 4 );
29
                 cout << " Istruz MFLO o MFHI durante l'interrupt" << endl;
30
              }
31
              else
32
              {
33
                 m_wb_instaddr_s.write(m_wb_instaddr.read());
34
                 cout << " Indirizzi consecutivi delle ultime 2 istruz durante l'interrupt" << endl;
35
              }
36
           }
37
           else
38
           {
39
              m_wb_instaddr_s.write(ex_m_instaddr.read());
40
              cout << " indirizzi delle ultime due istruz non consecutivi durante l'interrupt" << endl;
41
           }
42
         }
43
        else
44
           m_wb_instaddr_s.write(m_wb_instaddr.read());
45
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.