Subversion Repositories sasc

SASC (Simple Asynchronous Serial Controller)

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Status

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This core is done. It was tested on a XESS XCV800 board with

a Maxim transceiver.

Test Bench

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There is no test bench, period !

Please don't email me asking for one, unless you want to hire

me to write one ! As I said above I have tested this core in

real hardware and it works just fine.

Documentation

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Sorry, there is none. I just don't have the time to write it.

It's a very simple core, has two 4 byte deep FIFOs, that are

read or written to synchronously by asserting read enable (re)

or write enable (we) while applying or reading data. It does

use flow control, which basically indicates the status of the

internal FIFOs.

Misc

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The SASC Project Page is:

http://www.opencores.org/cores/sasc/

To find out more about me (Rudolf Usselmann), please visit:

http://www.asics.ws

Directory Structure

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[core_root]

 |

 +-doc                        Documentation

 |

 +-bench--+                   Test Bench

 |        +- verilog          Verilog Sources

 |        +-vhdl              VHDL Sources

 |

 +-rtl----+                   Core RTL Sources

 |        +-verilog           Verilog Sources

 |        +-vhdl              VHDL Sources

 |

 +-sim----+

 |        +-rtl_sim---+       Functional verification Directory

 |        |           +-bin   Makefiles/Run Scripts

 |        |           +-run   Working Directory

 |        |

 |        +-gate_sim--+       Functional & Timing Gate Level

 |                    |       Verification Directory

 |                    +-bin   Makefiles/Run Scripts

 |                    +-run   Working Directory

 |

 +-lint--+                    Lint Directory Tree

 |       +-bin                Makefiles/Run Scripts

 |       +-run                Working Directory

 |       +-log                Linter log & result files

 |

 +-syn---+                    Synthesis Directory Tree

 |       +-bin                Synthesis Scripts

 |       +-run                Working Directory

 |       +-log                Synthesis log files

 |       +-out                Synthesis Output