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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Simple Baud Rate Generator                                 ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/sasc/      ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: sasc_brg.v,v 1.1.1.1 2002-09-16 16:16:40 rudi Exp $
//
//  $Date: 2002-09-16 16:16:40 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//
//
//
 
`include "timescale.v"
 
/*
        Baud rate Generator
        ==================
 
        div0 -  is the first stage divider
                Set this to the desired number of cycles less two
        div1 -  is the second stage divider
                Set this to the actual number of cycles
 
        Remember you have to generate a baud rate that is 4 higher than what
        you really want. This is because of the DPLL in the RX section ...
 
        Example:
        If your system clock is 50MHz and you want to generate a 9.6 Kbps baud rate:
        9600*4 = 38400KHz
        50MHz/38400KHz=1302 or 6*217
        set div0=4 (6-2) and set div1=217
 
*/
 
module sasc_brg(clk, rst, div0, div1, sio_ce, sio_ce_x4);
input           clk;
input           rst;
input   [7:0]    div0, div1;
output          sio_ce, sio_ce_x4;
 
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
reg     [7:0]    ps;
reg             ps_clr;
reg     [7:0]    br_cnt;
reg             br_clr;
reg             sio_ce_x4_r;
reg     [1:0]    cnt;
reg             sio_ce, sio_ce_x4;
reg             sio_ce_r ;
reg             sio_ce_x4_t;
 
///////////////////////////////////////////////////////////////////
//
// Boud Rate Generator
//
 
// -----------------------------------------------------
// Prescaler
always @(posedge clk)
        if(!rst)        ps <= #1 8'h0;
        else
        if(ps_clr)      ps <= #1 8'h0;
        else            ps <= #1 ps + 8'h1;
 
always @(posedge clk)
        ps_clr <= #1 (ps == div0);      // Desired number of cycles less 2
 
// -----------------------------------------------------
// Oversampled Boud Rate (x4)
always @(posedge clk)
        if(!rst)        br_cnt <= #1 8'h0;
        else
        if(br_clr)      br_cnt <= #1 8'h0;
        else            br_cnt <= #1 br_cnt + 8'h1;
 
always @(posedge clk)
        br_clr <= #1 (br_cnt == div1); // Prciese number of PS cycles
 
always @(posedge clk)
        sio_ce_x4_r <= #1 br_clr;
 
always @(posedge clk)
        sio_ce_x4_t <= #1 !sio_ce_x4_r & br_clr;
 
always @(posedge clk)
        sio_ce_x4 <= #1 sio_ce_x4_t;
 
// -----------------------------------------------------
// Actual Boud rate
always @(posedge clk)
        if(!rst)                        cnt <= #1 2'h0;
        else
        if(!sio_ce_x4_r & br_clr)       cnt <= #1 cnt + 2'h1;
 
always @(posedge clk)
        sio_ce_r <= #1 (cnt == 2'h0);
 
always @(posedge clk)
        sio_ce <= #1 !sio_ce_r & (cnt == 2'h0);
 
endmodule
 

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Simple Baud Rate Generator ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/sasc/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: sasc_brg.v,v 1.1.1.1 2002-09-16 16:16:40 rudi Exp $`
42			`//`
43			`// $Date: 2002-09-16 16:16:40 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53			`//`
54			`//`
55			`//`
56			`//`
57			`//`
58
59			`include "timescale.v"
60
61			`/*`
62			`Baud rate Generator`
63			`==================`
64
65			`div0 - is the first stage divider`
66			`Set this to the desired number of cycles less two`
67			`div1 - is the second stage divider`
68			`Set this to the actual number of cycles`
69
70			`Remember you have to generate a baud rate that is 4 higher than what`
71			`you really want. This is because of the DPLL in the RX section ...`
72
73			`Example:`
74			`If your system clock is 50MHz and you want to generate a 9.6 Kbps baud rate:`
75			`9600*4 = 38400KHz`
76			`50MHz/38400KHz=1302 or 6*217`
77			`set div0=4 (6-2) and set div1=217`
78
79			`*/`
80
81			`module sasc_brg(clk, rst, div0, div1, sio_ce, sio_ce_x4);`
82			`input clk;`
83			`input rst;`
84			`input [7:0] div0, div1;`
85			`output sio_ce, sio_ce_x4;`
86
87			`///////////////////////////////////////////////////////////////////`
88			`//`
89			`// Local Wires and Registers`
90			`//`
91
92			`reg [7:0] ps;`
93			`reg ps_clr;`
94			`reg [7:0] br_cnt;`
95			`reg br_clr;`
96			`reg sio_ce_x4_r;`
97			`reg [1:0] cnt;`
98			`reg sio_ce, sio_ce_x4;`
99			`reg sio_ce_r ;`
100			`reg sio_ce_x4_t;`
101
102			`///////////////////////////////////////////////////////////////////`
103			`//`
104			`// Boud Rate Generator`
105			`//`
106
107			`// -----------------------------------------------------`
108			`// Prescaler`
109			`always @(posedge clk)`
110			`if(!rst) ps <= #1 8'h0;`
111			`else`
112			`if(ps_clr) ps <= #1 8'h0;`
113			`else ps <= #1 ps + 8'h1;`
114
115			`always @(posedge clk)`
116			`ps_clr <= #1 (ps == div0); // Desired number of cycles less 2`
117
118			`// -----------------------------------------------------`
119			`// Oversampled Boud Rate (x4)`
120			`always @(posedge clk)`
121			`if(!rst) br_cnt <= #1 8'h0;`
122			`else`
123			`if(br_clr) br_cnt <= #1 8'h0;`
124			`else br_cnt <= #1 br_cnt + 8'h1;`
125
126			`always @(posedge clk)`
127			`br_clr <= #1 (br_cnt == div1); // Prciese number of PS cycles`
128
129			`always @(posedge clk)`
130			`sio_ce_x4_r <= #1 br_clr;`
131
132			`always @(posedge clk)`
133			`sio_ce_x4_t <= #1 !sio_ce_x4_r & br_clr;`
134
135			`always @(posedge clk)`
136			`sio_ce_x4 <= #1 sio_ce_x4_t;`
137
138			`// -----------------------------------------------------`
139			`// Actual Boud rate`
140			`always @(posedge clk)`
141			`if(!rst) cnt <= #1 2'h0;`
142			`else`
143			`if(!sio_ce_x4_r & br_clr) cnt <= #1 cnt + 2'h1;`
144
145			`always @(posedge clk)`
146			`sio_ce_r <= #1 (cnt == 2'h0);`
147
148			`always @(posedge clk)`
149			`sio_ce <= #1 !sio_ce_r & (cnt == 2'h0);`
150
151			`endmodule`
152

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[/] [sasc/] [tags/] [start/] [rtl/] [verilog/] [sasc_brg.v] - Blame information for rev 6