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[/] [sasc/] [tags/] [start/] [rtl/] [verilog/] [sasc_fifo4.v] - Blame information for rev 6

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  FIFO 4 entries deep                                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/sasc/      ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: sasc_fifo4.v,v 1.1.1.1 2002-09-16 16:16:41 rudi Exp $
//
//  $Date: 2002-09-16 16:16:41 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//
 
`include "timescale.v"
 
// 4 entry deep fast fifo
module sasc_fifo4(clk, rst, clr,  din, we, dout, re, full, empty);
 
input           clk, rst;
input           clr;
input   [7:0]    din;
input           we;
output  [7:0]    dout;
input           re;
output          full, empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [7:0]    mem[0:3];
reg     [1:0]   wp;
reg     [1:0]   rp;
wire    [1:0]   wp_p1;
wire    [1:0]   wp_p2;
wire    [1:0]   rp_p1;
wire            full, empty;
reg             gb;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk or negedge rst)
        if(!rst)        wp <= #1 2'h0;
        else
        if(clr)         wp <= #1 2'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;
 
always @(posedge clk or negedge rst)
        if(!rst)        rp <= #1 2'h0;
        else
        if(clr)         rp <= #1 2'h0;
        else
        if(re)          rp <= #1 rp_p1;
 
assign rp_p1 = rp + 2'h1;
 
// Fifo Output
assign  dout = mem[ rp ];
 
// Fifo Input 
always @(posedge clk)
        if(we)     mem[ wp ] <= #1 din;
 
// Status
assign empty = (wp == rp) & !gb;
assign full  = (wp == rp) &  gb;
 
// Guard Bit ...
always @(posedge clk)
        if(!rst)                        gb <= #1 1'b0;
        else
        if(clr)                         gb <= #1 1'b0;
        else
        if((wp_p1 == rp) & we)          gb <= #1 1'b1;
        else
        if(re)                          gb <= #1 1'b0;
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// FIFO 4 entries deep ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/sasc/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: sasc_fifo4.v,v 1.1.1.1 2002-09-16 16:16:41 rudi Exp $`
42			`//`
43			`// $Date: 2002-09-16 16:16:41 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53			`//`
54			`//`
55			`//`
56
57			`include "timescale.v"
58
59			`// 4 entry deep fast fifo`
60			`module sasc_fifo4(clk, rst, clr, din, we, dout, re, full, empty);`
61
62			`input clk, rst;`
63			`input clr;`
64			`input [7:0] din;`
65			`input we;`
66			`output [7:0] dout;`
67			`input re;`
68			`output full, empty;`
69
70
71			`////////////////////////////////////////////////////////////////////`
72			`//`
73			`// Local Wires`
74			`//`
75
76			`reg [7:0] mem[0:3];`
77			`reg [1:0] wp;`
78			`reg [1:0] rp;`
79			`wire [1:0] wp_p1;`
80			`wire [1:0] wp_p2;`
81			`wire [1:0] rp_p1;`
82			`wire full, empty;`
83			`reg gb;`
84
85			`////////////////////////////////////////////////////////////////////`
86			`//`
87			`// Misc Logic`
88			`//`
89
90			`always @(posedge clk or negedge rst)`
91			`if(!rst) wp <= #1 2'h0;`
92			`else`
93			`if(clr) wp <= #1 2'h0;`
94			`else`
95			`if(we) wp <= #1 wp_p1;`
96
97			`assign wp_p1 = wp + 2'h1;`
98			`assign wp_p2 = wp + 2'h2;`
99
100			`always @(posedge clk or negedge rst)`
101			`if(!rst) rp <= #1 2'h0;`
102			`else`
103			`if(clr) rp <= #1 2'h0;`
104			`else`
105			`if(re) rp <= #1 rp_p1;`
106
107			`assign rp_p1 = rp + 2'h1;`
108
109			`// Fifo Output`
110			`assign dout = mem[ rp ];`
111
112			`// Fifo Input`
113			`always @(posedge clk)`
114			`if(we) mem[ wp ] <= #1 din;`
115
116			`// Status`
117			`assign empty = (wp == rp) & !gb;`
118			`assign full = (wp == rp) & gb;`
119
120			`// Guard Bit ...`
121			`always @(posedge clk)`
122			`if(!rst) gb <= #1 1'b0;`
123			`else`
124			`if(clr) gb <= #1 1'b0;`
125			`else`
126			`if((wp_p1 == rp) & we) gb <= #1 1'b1;`
127			`else`
128			`if(re) gb <= #1 1'b0;`
129
130			`endmodule`
131
132

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[/] [sasc/] [tags/] [start/] [rtl/] [verilog/] [sasc_fifo4.v] - Blame information for rev 6