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[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [README] - Blame information for rev 11

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1 11 ashwin_men
This Xilinx Base System (created with 12.2) includes the SATA2 Core with
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 interfaces to PLB for command, control and status and to DDR through
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NPI for data. A C test program which runs on Microblaze to exercise the core
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is under "sata_test".
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Note: Use Makefiles under the respective coregen directories of the SATA
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and NPI cores to generate netlists for FIFOs and ILAs. Then copy or link
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these to the netlist directories.

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