OpenCores
URL https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk

Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [__xps/] [system.xml] - Blame information for rev 11

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      NPI_CORE
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      SATA_CORE
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      MicroBlaze
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      The MicroBlaze 32 bit soft processor
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          Select implementation to optimize area (with lower instruction throughput)
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          Select Bus Interfaces
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          Enable Additional Machine Status Register Instructions
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          Enable Pattern Comparator
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          Enable Barrel Shifter
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          Enable Integer Divider
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          Enable Integer Multiplier
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          Enable Floating Point Unit
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          Enable Unaligned Data Exception
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          Enable Illegal Instruction Exception
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          Enable Instruction-side PLB Exception
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          Enable Data-side PLB Exception
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          Enable Integer Divide Exception
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          Enable Floating Point Unit Exceptions
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          Enable FSL Exception
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          Specifies Processor Version Register
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          Specify USER1 Bits in Processor Version Register
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          Specify USER2 Bits in Processor Version Registers
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          Enable MicroBlaze Debug Module Interface
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          Number of PC Breakpoints 
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          Number of Read Address Watchpoints 
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          Number of Write Address Watchpoints 
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          Sense Interrupt on Edge vs. Level 
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          Sense Interrupt on Rising vs. Falling Edge 
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          Specify Reset Value for Select MSR Bits
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          <qt>Generate Illegal Instruction Exception for NULL Instruction</qt>
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          Number of FSL Links 
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          Enable Additional FSL Instructions
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          I-Cache Base Address 
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          I-Cache High Address 
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          Enable Instruction Cache 
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          Enable I-Cache Writes
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          Size of the I-Cache in Bytes
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          Instruction Cache Line Length
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          Use Cache Links for All I-Cache Memory Accesses 
330
        
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          Number of I-Cache Victims
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          Number of I-Cache Streams
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          D-Cache Base Address
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          D-Cache High Address
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          Enable Data Cache
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          Enable D-Cache Writes
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          Size of D-Cache in Bytes
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          Data Cache Line Length
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          Use Cache Links for All D-Cache Memory Accesses 
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          Enable Write-back Storage Policy
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          Number of D-Cache Victims
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          Memory Management
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          Data Shadow Translation Look-Aside Buffer Size
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          Instruction Shadow Translation Look-Aside Buffer Size
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          Enable Access to Memory Management Special Registers
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          Number of Memory Protection Zones
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          Enable Branch Target Cache
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          Branch Target Cache Size
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      Processor Local Bus (PLB) 4.6
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      'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'
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815
        
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819
        
820
          Number of PLB Masters
821
        
822
        
823
          Number of PLB Slaves
824
        
825
        
826
          PLB Master ID Bus Width
827
        
828
        
829
          PLB Address Bus Width
830
        
831
        
832
          PLB Data Bus Width
833
        
834
        
835
          Include DCR Interface and Error Registers
836
        
837
        
838
          Base Address
839
        
840
        
841
          High Address
842
        
843
        
844
          DCR Address Bus Width
845
        
846
        
847
          DCR Data Bus Width
848
        
849
        
850
          External Reset Active High 
851
        
852
        
853
          IRQ Active State 
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855
        
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          <qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt>
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858
        
859
          Enable Address Pipelining Type
860
        
861
        
862
          Device Family
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864
        
865
          Optimize PLB for Point-to-point Topology
866
        
867
        
868
          Selects the Arbitration Scheme
869
        
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975
          
976
            
977
          
978
        
979
      
980
    
981
    
982
      Local Memory Bus (LMB) 1.0
983
      'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
984
      
985
        
986
      
987
      
988
      
989
        
990
          Number of Bus Slaves 
991
        
992
        
993
          LMB Address Bus Width 
994
        
995
        
996
          LMB Data Bus Width 
997
        
998
        
999
          Active High External Reset
1000
        
1001
      
1002
      
1003
        
1004
        
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1008
        
1009
        
1010
        
1011
        
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1014
        
1015
        
1016
        
1017
        
1018
        
1019
        
1020
        
1021
        
1022
      
1023
      
1024
    
1025
    
1026
      Local Memory Bus (LMB) 1.0
1027
      'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
1028
      
1029
        
1030
      
1031
      
1032
      
1033
        
1034
          Number of Bus Slaves 
1035
        
1036
        
1037
          LMB Address Bus Width 
1038
        
1039
        
1040
          LMB Data Bus Width 
1041
        
1042
        
1043
          Active High External Reset
1044
        
1045
      
1046
      
1047
        
1048
        
1049
        
1050
        
1051
        
1052
        
1053
        
1054
        
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1060
        
1061
        
1062
        
1063
        
1064
        
1065
        
1066
      
1067
      
1068
    
1069
    
1070
      LMB BRAM Controller
1071
      Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
1072
      
1073
        
1074
      
1075
      
1076
      
1077
        
1078
          LMB BRAM Base Address
1079
        
1080
        
1081
          LMB BRAM High Address
1082
        
1083
        
1084
          LMB Address Decode Mask
1085
        
1086
        
1087
          LMB Address Bus Width 
1088
        
1089
        
1090
          LMB Data Bus Width 
1091
        
1092
      
1093
      
1094
        
1095
        
1096
        
1097
        
1098
        
1099
        
1100
        
1101
        
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1111
      
1112
      
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1114
        
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1116
      
1117
        
1118
          
1119
            
1120
          
1121
        
1122
      
1123
    
1124
    
1125
      LMB BRAM Controller
1126
      Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
1127
      
1128
        
1129
      
1130
      
1131
      
1132
        
1133
          LMB BRAM Base Address
1134
        
1135
        
1136
          LMB BRAM High Address
1137
        
1138
        
1139
          LMB Address Decode Mask
1140
        
1141
        
1142
          LMB Address Bus Width 
1143
        
1144
        
1145
          LMB Data Bus Width 
1146
        
1147
      
1148
      
1149
        
1150
        
1151
        
1152
        
1153
        
1154
        
1155
        
1156
        
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1171
      
1172
        
1173
          
1174
            
1175
          
1176
        
1177
      
1178
    
1179
    
1180
      Block RAM (BRAM) Block
1181
      The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
1182
      
1183
        
1184
      
1185
      
1186
      
1187
        
1188
          Size of BRAM(s) in Bytes
1189
        
1190
        
1191
          Data Width of Port A and B
1192
        
1193
        
1194
          Address Width of Port A and B
1195
        
1196
        
1197
          Number of Byte Write Enables
1198
        
1199
        
1200
          Device Family
1201
        
1202
      
1203
      
1204
        
1205
        
1206
        
1207
        
1208
        
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1210
        
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1217
        
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1219
      
1220
        
1221
        
1222
      
1223
    
1224
    
1225
      XPS UART (Lite)
1226
      Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.
1227
      
1228
        
1229
      
1230
      
1231
      
1232
        
1233
          Device Family
1234
        
1235
        
1236
          Clock Frequency of PLB Slave
1237
        
1238
        
1239
          Base Address
1240
        
1241
        
1242
          High Address
1243
        
1244
        
1245
          PLB Address Bus Width
1246
        
1247
        
1248
          PLB Data Bus Width
1249
        
1250
        
1251
          PLB Slave Uses P2P Topology
1252
        
1253
        
1254
          Master ID Bus Width of PLB
1255
        
1256
        
1257
          Number of PLB Masters
1258
        
1259
        
1260
          PLB Slave is Capable of Bursts
1261
        
1262
        
1263
          Native Data Bus Width of PLB Slave
1264
        
1265
        
1266
          UART Lite Baud Rate 
1267
          Baud Rate
1268
        
1269
        
1270
          Number of Data Bits in a Serial Frame
1271
          Data Bits
1272
        
1273
        
1274
          Use Parity 
1275
        
1276
        
1277
          Parity Type 
1278
        
1279
      
1280
      
1281
        
1282
          Serial Data In
1283
        
1284
        
1285
          Serial Data Out
1286
        
1287
        
1288
        
1289
        
1290
        
1291
        
1292
        
1293
        
1294
        
1295
        
1296
        
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1301
        
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1340
      
1341
    
1342
    
1343
      Multi-Port Memory Controller(DDR/DDR2/SDRAM)
1344
      Multi-port memory controller.
1345
      
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1347
      
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          Address Width
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1507
        
1508
          Bank Address Width
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1510
        
1511
          Data Width
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1513
        
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          Data Mask Width
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          DQS Width
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2240
        
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2250
        
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4048
            
4049
            
4050
            
4051
            
4052
            
4053
            
4054
            
4055
            
4056
            
4057
            
4058
            
4059
            
4060
            
4061
            
4062
            
4063
            
4064
            
4065
            
4066
            
4067
            
4068
            
4069
            
4070
            
4071
            
4072
          
4073
        
4074
        
4075
        
4076
          
4077
            
4078
            
4079
            
4080
            
4081
            
4082
            
4083
            
4084
            
4085
          
4086
        
4087
        
4088
          
4089
            
4090
          
4091
        
4092
        
4093
          
4094
            
4095
            
4096
            
4097
            
4098
            
4099
            
4100
          
4101
        
4102
        
4103
          
4104
            
4105
          
4106
        
4107
        
4108
          
4109
            
4110
            
4111
            
4112
            
4113
            
4114
            
4115
          
4116
        
4117
        
4118
          
4119
            
4120
          
4121
        
4122
        
4123
          
4124
            
4125
            
4126
            
4127
            
4128
            
4129
            
4130
          
4131
        
4132
        
4133
          
4134
            
4135
          
4136
        
4137
        
4138
          
4139
            
4140
            
4141
            
4142
            
4143
            
4144
            
4145
          
4146
        
4147
        
4148
          
4149
            
4150
          
4151
        
4152
        
4153
          
4154
            
4155
            
4156
            
4157
            
4158
            
4159
            
4160
          
4161
        
4162
        
4163
          
4164
            
4165
          
4166
        
4167
        
4168
          
4169
            
4170
            
4171
            
4172
            
4173
            
4174
            
4175
          
4176
        
4177
        
4178
          
4179
            
4180
          
4181
        
4182
        
4183
          
4184
            
4185
            
4186
            
4187
            
4188
            
4189
            
4190
          
4191
        
4192
        
4193
          
4194
            
4195
          
4196
        
4197
        
4198
          
4199
            
4200
            
4201
            
4202
            
4203
            
4204
            
4205
          
4206
        
4207
        
4208
          
4209
            
4210
          
4211
        
4212
      
4213
    
4214
    
4215
      Clock Generator
4216
      Clock generator for processor system.
4217
      
4218
        
4219
      
4220
      
4221
      
4222
        
4223
          Family
4224
        
4225
        
4226
          Device
4227
        
4228
        
4229
          Package
4230
        
4231
        
4232
          Speed Grade
4233
        
4234
        
4235
          Input Clock Frequency (Hz) 
4236
        
4237
        
4238
          Required Frequency (Hz)
4239
        
4240
        
4241
          Required Phase 
4242
        
4243
        
4244
          Required Group
4245
        
4246
        
4247
          Buffered 
4248
        
4249
        
4250
          Variable Phase
4251
        
4252
        
4253
          Required Frequency (Hz)
4254
        
4255
        
4256
          Required Phase
4257
        
4258
        
4259
          Required Group 
4260
        
4261
        
4262
          Buffered
4263
        
4264
        
4265
          Variable Phase
4266
        
4267
        
4268
          Required Frequency (Hz)
4269
        
4270
        
4271
          Required Phase
4272
        
4273
        
4274
          Required Group 
4275
        
4276
        
4277
          Buffered
4278
        
4279
        
4280
          Varaible Phase
4281
        
4282
        
4283
          Required Frequency (Hz)
4284
        
4285
        
4286
          Required Phase
4287
        
4288
        
4289
          Required Group
4290
        
4291
        
4292
          Buffered
4293
        
4294
        
4295
          Variable Phase
4296
        
4297
        
4298
          Required Frequency (Hz)
4299
        
4300
        
4301
          Required Phase
4302
        
4303
        
4304
          Required Group 
4305
        
4306
        
4307
          Buffered
4308
        
4309
        
4310
          Variable Phase
4311
        
4312
        
4313
          Required Frequency (Hz)
4314
        
4315
        
4316
          Required Phase
4317
        
4318
        
4319
          Required Group
4320
        
4321
        
4322
          Buffered
4323
        
4324
        
4325
          Variable Phase
4326
        
4327
        
4328
          Required Frequency (Hz)
4329
        
4330
        
4331
          Required Phase 
4332
        
4333
        
4334
          Required Group
4335
        
4336
        
4337
          Buffered
4338
        
4339
        
4340
          Variable Phase
4341
        
4342
        
4343
          Required Frequency (Hz)
4344
        
4345
        
4346
          Required Phase
4347
        
4348
        
4349
          Required Group
4350
        
4351
        
4352
          Buffered
4353
        
4354
        
4355
          Variable Phase
4356
        
4357
        
4358
          Required Frequency (Hz)
4359
        
4360
        
4361
          Required Phase
4362
        
4363
        
4364
          Required Group
4365
        
4366
        
4367
          Buffered
4368
        
4369
        
4370
          Variable Phase
4371
        
4372
        
4373
          Required Frequency (Hz)
4374
        
4375
        
4376
          Required Phase
4377
        
4378
        
4379
          Required Group
4380
        
4381
        
4382
          Buffered
4383
        
4384
        
4385
           Varaible Phase
4386
        
4387
        
4388
          Required Frequency (Hz)
4389
        
4390
        
4391
          Required Phase
4392
        
4393
        
4394
          Required Group
4395
        
4396
        
4397
          Buffered
4398
        
4399
        
4400
          Variable Phase
4401
        
4402
        
4403
          Required Frequency (Hz)
4404
        
4405
        
4406
          Required Phase
4407
        
4408
        
4409
          Required Group
4410
        
4411
        
4412
          Buffered
4413
        
4414
        
4415
          Variable Phase
4416
        
4417
        
4418
          Required Frequency (Hz)
4419
        
4420
        
4421
          Required Phase
4422
        
4423
        
4424
          Required Group
4425
        
4426
        
4427
          Buffered
4428
        
4429
        
4430
           Variable Phase
4431
        
4432
        
4433
          Required Frequency (Hz)
4434
        
4435
        
4436
          Required Phase
4437
        
4438
        
4439
          Required Group
4440
        
4441
        
4442
          Buffered
4443
        
4444
        
4445
          Variable Phase
4446
        
4447
        
4448
          Required Frequency (Hz)
4449
        
4450
        
4451
          Required Phase
4452
        
4453
        
4454
          Required Group
4455
        
4456
        
4457
          Buffered
4458
        
4459
        
4460
          Variable Phase
4461
        
4462
        
4463
          Required Frequency (Hz)
4464
        
4465
        
4466
          Required Phase
4467
        
4468
        
4469
          Required Group
4470
        
4471
        
4472
          Buffered
4473
        
4474
        
4475
           Variable Phase
4476
        
4477
        
4478
          Required Frequency (Hz)
4479
        
4480
        
4481
          Clock Deskew
4482
        
4483
        
4484
          Required Frequency (Hz)
4485
        
4486
        
4487
          Required Phase
4488
        
4489
        
4490
          Required Group
4491
        
4492
        
4493
          Buffered
4494
        
4495
        
4496
          Variable Phase Shift
4497
        
4498
        
4499
          External Reset
4500
        
4501
        
4502
          C_CLK_GEN
4503
        
4504
      
4505
      
4506
        
4507
        
4508
        
4509
        
4510
        
4511
        
4512
        
4513
        
4514
        
4515
        
4516
        
4517
        
4518
        
4519
        
4520
        
4521
        
4522
        
4523
        
4524
        
4525
        
4526
        
4527
        
4528
        
4529
        
4530
        
4531
      
4532
      
4533
    
4534
    
4535
      MicroBlaze Debug Module (MDM)
4536
      Debug module for MicroBlaze Soft Processor.
4537
      
4538
        
4539
      
4540
      
4541
      
4542
        
4543
          Device Family
4544
        
4545
        
4546
          Specifies the JTAG user-defined register used 
4547
        
4548
        
4549
          Specifies the Bus Interface for the JTAG UART 
4550
        
4551
        
4552
          Base Address
4553
        
4554
        
4555
          High Address
4556
        
4557
        
4558
          PLB Address Bus Width
4559
        
4560
        
4561
          PLB Data Bus Width
4562
        
4563
        
4564
          PLB Slave Uses P2P Topology
4565
        
4566
        
4567
          Master ID Bus Width of PLB
4568
        
4569
        
4570
          Number of PLB Masters
4571
        
4572
        
4573
          Native Data Bus Width of PLB Slave
4574
        
4575
        
4576
          PLB Slave is Capable of Bursts
4577
        
4578
        
4579
          OPB Data Bus Width
4580
        
4581
        
4582
          OPB Address Bus Width
4583
        
4584
        
4585
          Number of MicroBlaze debug ports 
4586
        
4587
        
4588
          Enable JTAG UART 
4589
        
4590
        
4591
          UART Data size 
4592
        
4593
        
4594
          Enable Write FSL Port
4595
        
4596
      
4597
      
4598
        
4599
        
4600
        
4601
        
4602
        
4603
        
4604
        
4605
        
4606
        
4607
        
4608
        
4609
        
4610
        
4611
        
4612
        
4613
        
4614
        
4615
        
4616
        
4617
        
4618
        
4619
        
4620
        
4621
        
4622
        
4623
        
4624
        
4625
        
4626
        
4627
        
4628
        
4629
        
4630
        
4631
        
4632
        
4633
        
4634
        
4635
        
4636
        
4637
        
4638
        
4639
        
4640
        
4641
        
4642
        
4643
        
4644
        
4645
        
4646
        
4647
        
4648
        
4649
        
4650
        
4651
        
4652
        
4653
        
4654
        
4655
        
4656
        
4657
        
4658
        
4659
        
4660
        
4661
        
4662
        
4663
        
4664
        
4665
        
4666
        
4667
        
4668
        
4669
        
4670
        
4671
        
4672
        
4673
        
4674
        
4675
        
4676
        
4677
        
4678
        
4679
        
4680
        
4681
        
4682
        
4683
        
4684
        
4685
        
4686
        
4687
        
4688
        
4689
        
4690
        
4691
        
4692
        
4693
        
4694
        
4695
        
4696
        
4697
        
4698
        
4699
        
4700
        
4701
        
4702
        
4703
        
4704
        
4705
        
4706
        
4707
        
4708
        
4709
        
4710
        
4711
        
4712
        
4713
        
4714
        
4715
        
4716
        
4717
        
4718
        
4719
        
4720
        
4721
        
4722
        
4723
        
4724
        
4725
        
4726
        
4727
        
4728
        
4729
        
4730
        
4731
        
4732
        
4733
        
4734
        
4735
        
4736
        
4737
        
4738
        
4739
        
4740
        
4741
        
4742
        
4743
        
4744
        
4745
        
4746
        
4747
      
4748
      
4749
        
4750
        
4751
        
4752
        
4753
        
4754
        
4755
        
4756
        
4757
        
4758
        
4759
        
4760
        
4761
        
4762
      
4763
      
4764
        
4765
          
4766
            
4767
            
4768
          
4769
        
4770
      
4771
    
4772
    
4773
      Processor System Reset Module
4774
      Reset management module
4775
      
4776
        
4777
      
4778
      
4779
      
4780
        
4781
          Device Subfamily
4782
        
4783
        
4784
          Number of Clocks Before Input Change is Recognized On The External Reset Input 
4785
        
4786
        
4787
          Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input 
4788
        
4789
        
4790
          External Reset Active High 
4791
        
4792
        
4793
          Auxiliary Reset Active High 
4794
        
4795
        
4796
          Number of Bus Structure Reset Registered Outputs 
4797
        
4798
        
4799
          Number of Peripheral Reset Registered Outputs 
4800
        
4801
        
4802
          Device Family
4803
        
4804
      
4805
      
4806
        
4807
        
4808
        
4809
        
4810
        
4811
        
4812
        
4813
        
4814
        
4815
        
4816
        
4817
        
4818
        
4819
        
4820
        
4821
        
4822
        
4823
        
4824
        
4825
        
4826
      
4827
      
4828
        
4829
        
4830
      
4831
    
4832
    
4833
      Chipscope Integrated Controller
4834
      'The Chipscope ICON core provides a communication path between the FPGA Boundary Scan port and the other Chipscope Cores OPB IBA, PLB IBA, VIO, and the ILA.'
4835
      
4836
        
4837
      
4838
      
4839
      
4840
        
4841
          Device Family
4842
        
4843
        
4844
          Device Name
4845
        
4846
        
4847
          Package Name
4848
        
4849
        
4850
          Speed Grade Name
4851
        
4852
        
4853
          Number of Control Ports 
4854
        
4855
        
4856
          System Contains MDM Peripheral or Not 
4857
        
4858
        
4859
          Use a specific BSCAN user port
4860
        
4861
      
4862
      
4863
        
4864
        
4865
        
4866
        
4867
        
4868
        
4869
        
4870
        
4871
        
4872
        
4873
        
4874
        
4875
        
4876
        
4877
        
4878
        
4879
        
4880
        
4881
        
4882
        
4883
        
4884
        
4885
        
4886
      
4887
      
4888
    
4889
  
4890
 
4891

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