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ashwin_men |
# Virtex 6 ML605 Evaluation Platform
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################################## Clock Constraints ##########################
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# SATA Port J11 #J64 FMC pins
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Net FMC_HPC_DP2_C2M_N LOC = AF2; #A27
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Net FMC_HPC_DP2_C2M_P LOC = AF1; #A26
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Net FMC_HPC_DP2_M2C_N LOC = AF6; #A7
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Net FMC_HPC_DP2_M2C_P LOC = AF5; #A6
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# GTX Clock Module constraints
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#NET TILE0_REFCLK_PAD_N_IN_pin LOC=AK5; #FMC_HPC_CLK2_M2C_MGT_C_N
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#NET TILE0_REFCLK_PAD_P_IN_pin LOC=AK6; #FMC_HPC_CLK2_M2C_MGT_C_P
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### Push Button Reset and NEW CMD
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#NET GTX_RESET_IN LOC = "G26"; ##SW9 C
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#NET NEW_CMD LOC = "G17"; ##SW7 E
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#### Module LEDs_8Bit constraints
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NET TILE0_PLLLKDET_OUT_N LOC= "AC22" |IOSTANDARD=LVCMOS25; #LED 0
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NET DCMLOCKED_OUT LOC= "AC24" |IOSTANDARD=LVCMOS25; #LED 1
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NET LINKUP_led LOC= "AE22" |IOSTANDARD=LVCMOS25; #LED 2
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Net fpga_0_RS232_Uart_1_RX_pin LOC = J24 | IOSTANDARD=LVCMOS25;
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Net fpga_0_RS232_Uart_1_TX_pin LOC = J25 | IOSTANDARD=LVCMOS25;
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Net fpga_0_DDR3_SDRAM_DDR3_Clk_pin LOC=G18 | IOSTANDARD = DIFF_SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin LOC=H18 | IOSTANDARD = DIFF_SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_CE_pin LOC=M18 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_CS_n_pin LOC=K18 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_ODT_pin LOC=F18 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin LOC=L19 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin LOC=C17 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_WE_n_pin LOC=B17 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin<0> LOC=K19 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin<1> LOC=J19 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin<2> LOC=L15 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<0> LOC=L14 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<1> LOC=A16 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<2> LOC=B16 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<3> LOC=E16 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<4> LOC=D16 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<5> LOC=J17 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<6> LOC=A15 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<7> LOC=B15 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<8> LOC=G15 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<9> LOC=F15 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<10> LOC=M16 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<11> LOC=M15 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Addr_pin<12> LOC=H15 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<0> LOC=J11 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<1> LOC=E13 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<2> LOC=F13 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<3> LOC=K11 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<4> LOC=L11 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<5> LOC=K13 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<6> LOC=K12 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<7> LOC=D11 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<8> LOC=M13 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<9> LOC=J14 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<10> LOC=B13 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<11> LOC=B12 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<12> LOC=G10 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<13> LOC=M11 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<14> LOC=C12 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<15> LOC=A11 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<16> LOC=G11 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<17> LOC=F11 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<18> LOC=D14 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<19> LOC=C14 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<20> LOC=G12 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<21> LOC=G13 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<22> LOC=F14 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<23> LOC=H14 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<24> LOC=D26 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<25> LOC=F26 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<26> LOC=B26 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<27> LOC=E26 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<28> LOC=C24 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<29> LOC=D25 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<30> LOC=D27 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQ_pin<31> LOC=C25 | IOSTANDARD = SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DM_pin<0> LOC=E11 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_DM_pin<1> LOC=B11 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_DM_pin<2> LOC=E14 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_DM_pin<3> LOC=A26 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin LOC=E18 | IOSTANDARD = SSTL15;
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Net fpga_0_DDR3_SDRAM_DDR3_DQS_pin<0> LOC=D12 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQS_pin<1> LOC=H12 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQS_pin<2> LOC=A13 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQS_pin<3> LOC=B25 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin<0> LOC=E12 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin<1> LOC=J12 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin<2> LOC=A14 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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Net fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin<3> LOC=A25 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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Net fpga_0_clk_1_sys_clk_p_pin TNM_NET = sys_clk_pin;
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TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
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Net fpga_0_clk_1_sys_clk_p_pin LOC = J9 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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Net fpga_0_clk_1_sys_clk_n_pin LOC = H9 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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Net fpga_0_rst_1_sys_rst_pin TIG;
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Net fpga_0_rst_1_sys_rst_pin LOC = H10 | IOSTANDARD=SSTL15 | PULLUP | TIG;
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###### DDR3_SDRAM
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disable = reg_sr_o;
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disable = reg_sr_r;
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CONFIG DCI_CASCADE = "36 35";
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CONFIG DCI_CASCADE = "26 25";
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#clock_generator
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#INST "clock_generator_0/clock_generator_0/Using_MMCM0.MMCM0_INST/MMCM_INST/MMCM_ADV_inst" LOC = "MMCM_ADV_X0Y9";
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#INST "*/u_mmcm_clk_base" LOC = "MMCM_ADV_X0Y8";
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###############################################################################
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# Define multicycle paths - these paths may take longer because additional
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# time allowed for logic to settle in calibration/initialization FSM
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###############################################################################
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#NET "fpga_0_DDR3_SDRAM_DDR3_Clk_pin*" TIG;
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#NET "fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin*" TIG;
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###############################################################################
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# Capture Clock Constraints
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# Available sites are:
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# Bank 35:
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# C13: IO_L11P_SRCC_35 : X2Y137 : CPT[0]
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# M12: IO_L10P_MRCC_35 : X2Y139 : RSYNC[0]
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# L13: IO_L9P_MRCC_35 : X2Y141 : CPT[1]
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# K14: IO_L8P_SRCC_35 : X2Y143 : CPT[2]
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# Bank 26:
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# F21: IO_L10P_MRCC_26 : X1Y179 : CPT[3]
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# B20: IO_L9P_MRCC_26 : X1Y181 : CPT[4]
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# F19: IO_L8P_SRCC_26 : X1Y183 :
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# Bank 25:
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# F25: IO_L11P_SRCC_25 : X1Y137 : CPT[5]
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# C29: IO_L10P_MRCC_25 : X1Y139 : RSYNC[1]
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# C28: IO_L9P_MRCC_25 : X1Y141 : CPT[6]
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# D24: IO_L8P_SRCC_25 : X1Y143 : CPT[7]
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###############################################################################
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#####################################################################
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# Place RSYNC OSERDES and IODELAY:
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#####################################################################
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# CLK_RSYNC[0]: Site M12
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INST "*/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
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LOC = "OLOGIC_X2Y139";
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INST "*/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
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LOC = "IODELAY_X2Y139";
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INST "*/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync"
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LOC = "BUFR_X2Y6";
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# CLK_RSYNC[1]: Site C29
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INST "*/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync"
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LOC = "OLOGIC_X1Y139";
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INST "*/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync"
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LOC = "IODELAY_X1Y139";
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INST "*/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync"
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LOC = "BUFR_X1Y6";
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# Place CPT OSERDES and IODELAY:
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# DQS[0]: Site C13
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INST "*/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt"
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LOC = "OLOGIC_X2Y137";
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INST "*/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt"
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LOC = "IODELAY_X2Y137";
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# DQS[1]: Site L13
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INST "*/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt"
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LOC = "OLOGIC_X2Y141";
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INST "*/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt"
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LOC = "IODELAY_X2Y141";
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# DQS[2]: Site K14
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INST "*/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt"
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LOC = "OLOGIC_X2Y143";
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INST "*/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt"
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LOC = "IODELAY_X2Y143";
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# DQS[3]: Site F25
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INST "*/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt"
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LOC = "OLOGIC_X1Y137";
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INST "*/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt"
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LOC = "IODELAY_X1Y137";
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###############################################################################
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# OCB Monitor Constraints
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###############################################################################
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# Site J10
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#INST "*/gen_enable_ocb_mon.u_phy_ocb_mon_top/u_oserdes_ocb_mon"
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# LOC = "OLOGIC_X2Y130";
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