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###################################################################
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##
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## Name : npi_core
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## Desc : Microprocessor Peripheral Description
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## : Automatically generated by PsfUtility
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##
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###################################################################
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BEGIN npi_core
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## Peripheral Options
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OPTION IPTYPE = PERIPHERAL
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OPTION IMP_NETLIST = TRUE
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OPTION HDL = VHDL
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OPTION IP_GROUP = MICROBLAZE:PPC:USER
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OPTION DESC = NPI_CORE
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OPTION STYLE = MIX
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## Native Port Interface for MPMC
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BUS_INTERFACE BUS = XIL_NPI, BUS_STD = XIL_NPI, BUS_TYPE = INITIATOR
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## Generics
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PARAMETER CHIPSCOPE = false, DT = boolean
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PARAMETER RAM_OFFSET = 0x00, DT = std_logic_vector
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PARAMETER BLOCK_SIZE = 1024, DT = integer
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## ChipScope ILA Controllers
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PORT npi_if_ila_control = "", DIR = I, VEC = [35:0]
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PORT npi_if_tx_ila_control = "", DIR = I, VEC = [35:0]
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PORT npi_ila_control = "", DIR = I, VEC = [35:0]
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## Clock and Reset Signals
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PORT MPMC_Clk = "", DIR = I
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PORT user_clk = "", DIR = I
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PORT reset = "", DIR = I
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PORT NPI_CORE_DIN = "", DIR = I, VEC = [31:0]
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PORT NPI_CORE_WE = "", DIR = I
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PORT NPI_CORE_FULL = "", DIR = O
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PORT NPI_CORE_DOUT = "", DIR = O, VEC = [31:0]
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PORT NPI_CORE_DOUT_WE = "", DIR = O
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PORT SATA_CORE_FULL = "", DIR = I
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PORT req_type = "", DIR = I, VEC = [1:0]
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PORT new_cmd = "", DIR = I
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PORT num_read_bytes_in = "", DIR = I, VEC = [31:0]
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PORT num_write_bytes_in = "", DIR = I, VEC = [31:0]
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PORT NPI_init_wr_addr_in = "", DIR = I, VEC = [31:0]
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PORT NPI_init_rd_addr_in = "", DIR = I, VEC = [31:0]
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PORT NPI_ready_for_cmd = "", DIR = O
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## Native Port Interface PORT
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PORT NPI_Addr = "Addr", DIR = O, BUS = XIL_NPI, VEC = [31:0], ENDIAN = LITTLE
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PORT NPI_AddrReq = "AddrReq", DIR = O, BUS = XIL_NPI
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PORT NPI_AddrAck = "AddrAck", DIR = I, BUS = XIL_NPI
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PORT NPI_RNW = "RNW", DIR = O, BUS = XIL_NPI
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PORT NPI_Size = "Size", DIR = O, BUS = XIL_NPI, VEC = [3:0], ENDIAN = LITTLE
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PORT NPI_WrFIFO_Data = "WrFIFO_Data", DIR = O, BUS = XIL_NPI, VEC = [63:0], ENDIAN = LITTLE
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PORT NPI_WrFIFO_BE = "WrFIFO_BE", DIR = O, BUS = XIL_NPI, VEC = [7:0], ENDIAN = LITTLE
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PORT NPI_WrFIFO_Push = "WrFIFO_Push", DIR = O, BUS = XIL_NPI
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PORT NPI_RdFIFO_Data = "RdFIFO_Data", DIR = I, BUS = XIL_NPI, VEC = [63:0], ENDIAN = LITTLE
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PORT NPI_RdFIFO_Pop = "RdFIFO_Pop", DIR = O, BUS = XIL_NPI
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PORT NPI_RdFIFO_RdWdAddr = "RdFIFO_RdWdAddr", DIR = I, BUS = XIL_NPI, VEC = [3:0], ENDIAN = LITTLE
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PORT NPI_WrFIFO_AlmostFull = "WrFIFO_AlmostFull", DIR = I, BUS = XIL_NPI
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PORT NPI_WrFIFO_Flush = "WrFIFO_Flush", DIR = O, BUS = XIL_NPI
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PORT NPI_WrFIFO_Empty = "WrFIFO_Empty", DIR = I, BUS = XIL_NPI
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PORT NPI_RdFIFO_Empty = "RdFIFO_Empty", DIR = I, BUS = XIL_NPI
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PORT NPI_RdFIFO_Flush = "RdFIFO_Flush", DIR = O, BUS = XIL_NPI
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PORT NPI_RdModWr = "RdModWr", DIR = O, BUS = XIL_NPI
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PORT NPI_InitDone = "InitDone", DIR = I, BUS = XIL_NPI
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PORT NPI_RdFIFO_Latency = "RdFIFO_Latency", DIR = I, BUS = XIL_NPI, VEC = [1:0], ENDIAN = LITTLE
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END
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