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[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [pcores/] [sata_core_v1_00_a/] [data/] [sata_core_v2_1_0.mpd] - Blame information for rev 11

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1 11 ashwin_men 
###################################################################
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##
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## Name     : sata_core
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## Desc     : Microprocessor Peripheral Description
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##          : Automatically generated by PsfUtility
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##
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###################################################################
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BEGIN sata_core
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## Peripheral Options
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OPTION IPTYPE = PERIPHERAL
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OPTION IMP_NETLIST = TRUE
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OPTION HDL = VHDL
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OPTION IP_GROUP = MICROBLAZE:PPC:USER
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OPTION DESC = SATA_CORE
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OPTION STYLE = MIX
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## Bus Interfaces
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BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
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## Generics for VHDL or Parameters for Verilog
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PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
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PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
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PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
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PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
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PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
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PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
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PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
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PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
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PARAMETER C_INCLUDE_DPHASE_TIMER = 1, DT = INTEGER, RANGE = (0, 1)
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PARAMETER C_FAMILY = virtex5, DT = STRING
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## Ports
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PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
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PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
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PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
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PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
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PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
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PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
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PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
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PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
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PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
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PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
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PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
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PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
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PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
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PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
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PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
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PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
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PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
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PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
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PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
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PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
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PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
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PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
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PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
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PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
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PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
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PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
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PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
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PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
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PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
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PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
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PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
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PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
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PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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## PORTS from SATA CORE
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#PORT TILE0_REFCLK_PAD_P_IN  = "", DIR = I
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#PORT TILE0_REFCLK_PAD_N_IN  = "", DIR = I
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PORT TXP0_OUT              = "", DIR = O
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PORT TXN0_OUT              = "", DIR = O
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PORT RXP0_IN               = "", DIR = I
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PORT RXN0_IN               = "", DIR = I
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PORT TILE0_PLLLKDET_OUT_N  = "", DIR = O
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PORT DCMLOCKED_OUT         = "", DIR = O
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PORT LINKUP_led            = "", DIR = O
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PORT GEN2_led              = "", DIR = O
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PORT RESET                 = "", DIR = I
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PORT CLKIN_150             = "", DIR = I
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# SATA-NPI
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PORT SATA_CORE_DOUT        = "", DIR = O, VEC = [31:0]
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PORT SATA_CORE_DOUT_WE     = "", DIR = O
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PORT SATA_CORE_CLK_OUT     = "", DIR = O
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PORT SATA_CORE_DIN         = "", DIR = I, VEC = [31:0]
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PORT SATA_CORE_DIN_WE      = "", DIR = I
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PORT SATA_CORE_FULL        = "", DIR = O
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PORT NPI_CORE_REQ_TYPE     = "", DIR = O, VEC = [1:0]
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PORT NPI_CORE_NEW_CMD      = "", DIR = O
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PORT NPI_CORE_NUM_RD_BYTES = "", DIR = O, VEC = [31:0]
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PORT NPI_CORE_NUM_WR_BYTES = "", DIR = O, VEC = [31:0]
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PORT NPI_CORE_INIT_WR_ADDR = "", DIR = O, VEC = [31:0]
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PORT NPI_CORE_INIT_RD_ADDR = "", DIR = O, VEC = [31:0]
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PORT NPI_CORE_READY_FOR_CMD = "", DIR = I
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## Chipscope ILAs
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PORT user_logic_ila_control   = "", DIR = I, VEC = [35:0]
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PORT cmd_layer_ila_control   = "", DIR = I, VEC = [35:0]
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PORT sata_rx_frame_ila_control   = "", DIR = I, VEC = [35:0]
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PORT sata_tx_frame_ila_control   = "", DIR = I, VEC = [35:0]
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PORT sata_phy_ila_control   = "", DIR = I, VEC = [35:0]
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PORT oob_control_ila_control   = "", DIR = I, VEC = [35:0]
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PORT scrambler_ila_control   = "", DIR = I, VEC = [35:0]
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PORT descrambler_ila_control   = "", DIR = I, VEC = [35:0]
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## Generics
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PARAMETER CHIPSCOPE  = true, DT = boolean
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PARAMETER DATA_WIDTH = 32, DT = natural
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END

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