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----------------------------------------------------------------------------
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-- Design Analysis --
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----------------------------------------------------------------------------
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Analyze pcore sata_core ...
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----------------------------------------------------------------------------
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-- File Generation --
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----------------------------------------------------------------------------
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Creating HDL source directory ...
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Generating top peripheral VHDL template ...
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Generating stub user logic VHDL template ...
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HDL templates successfully generated ...
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Creating data directory ...
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Generating XPS inteface files ...
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/
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hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
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Package compiled.
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Package body compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/
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hdl/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/
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hdl/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
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Package compiled.
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Package body compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/
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hdl/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/
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hdl/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/
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hdl/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/
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hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
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Package compiled.
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Package body compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_
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v1_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library
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plbv46_slave_single_v1_01_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_
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v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library
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plbv46_slave_single_v1_01_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file
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"/opt/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_
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v1_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library
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plbv46_slave_single_v1_01_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file
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"/home/ashwin/work/SATA/ml605/12.2/base/pcores/sata_core_v1_00_a/data/../hdl/vhd
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l/user_logic.vhd" in Library sata_core_v1_00_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling vhdl file
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"/home/ashwin/work/SATA/ml605/12.2/base/pcores/sata_core_v1_00_a/data/../hdl/vhd
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l/sata_core.vhd" in Library sata_core_v1_00_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Analyzing HDL attributes ...
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Entity name = sata_core
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INFO:EDK:1607 - IPTYPE set to value : PERIPHERAL
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INFO:EDK:1511 - IMP_NETLIST set to value : TRUE
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INFO:EDK:1486 - HDL set to value : VHDL
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XPS interface files successfully generated ...
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Creating development directory ...
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Generating command option file ...
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Generating readme file ...
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Development misc files successfully generated ...
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No ProjNavigator support files will be generated at this time ...
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No XST synthesis support files will be generated at this time ...
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No BFM simulation files will be generated at this time ...
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No software driver files will be generated at this time ...
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----------------------------------------------------------------------------
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-- Final Report --
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----------------------------------------------------------------------------
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Thank you for using Create and Import Peripheral Wizard! Please find your
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peripheral hardware templates under
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/home/ashwin/work/SATA/ml605/12.2/base/pcores/sata_core_v1_00_a.
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Peripheral Summary:
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top name : sata_core
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version : 1.00.a
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type : PLB (v4.6) slave
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features : slave attachment
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user s/w registers
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Address Block Summary:
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user logic slv : C_BASEADDR + 0x00000000
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: C_BASEADDR + 0x000000FF
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File Summary
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- HDL source -
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/home/ashwin/work/SATA/ml605/12.2/base/pcores/sata_core_v1_00_a/hdl
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top entity : vhdl/sata_core.vhd
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user logic : vhdl/user_logic.vhd
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- XPS interface -
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/home/ashwin/work/SATA/ml605/12.2/base/pcores/sata_core_v1_00_a/data
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mpd : sata_core_v2_1_0.mpd
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pao : sata_core_v2_1_0.pao
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- Misc file -
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/home/ashwin/work/SATA/ml605/12.2/base/pcores/sata_core_v1_00_a/devl
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help : README.txt
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option : ipwiz.opt
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log : ipwiz.log
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