Subversion Repositories sata_controller_core

///////////////////////////////////////////////////////////////////////////////

//   ____  ____

//  /   /\/   / 

// /___/  \  /    Vendor: Xilinx 

// \   \   \/     Version : 1.8

//  \   \         Application :  Virtex-6 FPGA GTX Transceiver Wizard

//  /   /         Filename : mgt_usrclk_source_mmcm.v

// /___/   /\     Timestamp : 

// \   \  /  \ 

//  \___\/\___\ 

//

//

// Module MGT_USRCLK_SOURCE (for use with GTX Transceivers)

// Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard

// 

// 

// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.

// 

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`timescale 1ns / 1ps

//***********************************Entity Declaration*******************************

module MGT_USRCLK_SOURCE_MMCM #

(

    parameter   MULT            =   2,

    parameter   DIVIDE          =   2,

    parameter   CLK_PERIOD      =   6.4,

    parameter   OUT0_DIVIDE     =   2,

    parameter   OUT1_DIVIDE     =   2,

    parameter   OUT2_DIVIDE     =   2,

    parameter   OUT3_DIVIDE     =   2

)

(

    output          CLK0_OUT,

    output          CLK1_OUT,

    output          CLK2_OUT,

    output          CLK3_OUT,

    input           CLK_IN,

    output          MMCM_LOCKED_OUT,

    input           MMCM_RESET_IN

);

`define DLY #1

//*********************************Wire Declarations**********************************

    wire    [15:0]  tied_to_ground_vec_i;

    wire            tied_to_ground_i;

    wire            clkout0_i;

    wire            clkout1_i;

    wire            clkout2_i;

    wire            clkout3_i;

    wire            clkfbout_i;

//*********************************** Beginning of Code *******************************

    //  Static signal Assigments    

    assign tied_to_ground_i             = 1'b0;

    assign tied_to_ground_vec_i         = 16'h0000;

    // Instantiate a MMCM module to divide the reference clock. Uses internal feedback

    // for improved jitter performance, and to avoid consuming an additional BUFG

    MMCM_ADV #

    (

         .COMPENSATION      ("ZHOLD"),

         .CLKFBOUT_MULT_F   (MULT),

         .DIVCLK_DIVIDE     (DIVIDE),

         .CLKFBOUT_PHASE    (0),

         .CLKIN1_PERIOD     (CLK_PERIOD),

         .CLKIN2_PERIOD     (10),   //Not used

         .CLKOUT0_DIVIDE_F  (OUT0_DIVIDE),

         .CLKOUT0_PHASE     (0),

         .CLKOUT1_DIVIDE    (OUT1_DIVIDE),

         .CLKOUT1_PHASE     (0),

         .CLKOUT2_DIVIDE    (OUT2_DIVIDE),

         .CLKOUT2_PHASE     (0),

         .CLKOUT3_DIVIDE    (OUT3_DIVIDE),

         .CLKOUT3_PHASE     (0),

         .CLOCK_HOLD        ("TRUE")

    )

    mmcm_adv_i

    (

         .CLKIN1            (CLK_IN),

         .CLKIN2            (1'b0),

         .CLKINSEL          (1'b1),

         .CLKFBIN           (clkfbout_i),

         .CLKOUT0           (clkout0_i),

         .CLKOUT0B          (),

         .CLKOUT1           (clkout1_i),

         .CLKOUT1B          (),

         .CLKOUT2           (clkout2_i),

         .CLKOUT2B          (),

         .CLKOUT3           (clkout3_i),

         .CLKOUT3B          (),

         .CLKOUT4           (),

         .CLKOUT5           (),

         .CLKOUT6           (),

         .CLKFBOUT          (clkfbout_i),

         .CLKFBOUTB         (),

         .CLKFBSTOPPED      (),

         .CLKINSTOPPED      (),

         .DO                (),

         .DRDY              (),

         .DADDR             (7'd0),

         .DCLK              (1'b0),

         .DEN               (1'b0),

         .DI                (16'd0),

         .DWE               (1'b0),

         .LOCKED            (MMCM_LOCKED_OUT),

         .PSCLK             (1'b0),

         .PSEN              (1'b0),

         .PSINCDEC          (1'b0),

         .PSDONE            (),

         .PWRDWN            (1'b0),

         .RST               (MMCM_RESET_IN)

    );

    BUFG clkout0_bufg_i

    (

        .O              (CLK0_OUT),

        .I              (clkout0_i)

    );

    BUFG clkout1_bufg_i

    (

        .O              (CLK1_OUT),

        .I              (clkout1_i)

    );

    BUFG clkout2_bufg_i

    (

        .O              (CLK2_OUT),

        .I              (clkout2_i)

    );

    BUFG clkout3_bufg_i

    (

        .O              (CLK3_OUT),

        .I              (clkout3_i)

    );

endmodule